1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9	sms: system-controller@44083000 {
10		compatible = "ti,k2g-sci";
11		ti,host-id = <12>;
12
13		mbox-names = "rx", "tx";
14
15		mboxes= <&secure_proxy_main 11>,
16			<&secure_proxy_main 13>;
17
18		reg-names = "debug_messages";
19		reg = <0x00 0x44083000 0x00 0x1000>;
20
21		k3_pds: power-controller {
22			compatible = "ti,sci-pm-domain";
23			#power-domain-cells = <2>;
24		};
25
26		k3_clks: clock-controller {
27			compatible = "ti,k2g-sci-clk";
28			#clock-cells = <2>;
29		};
30
31		k3_reset: reset-controller {
32			compatible = "ti,sci-reset";
33			#reset-cells = <2>;
34		};
35	};
36
37	chipid@43000014 {
38		compatible = "ti,am654-chipid";
39		reg = <0x00 0x43000014 0x00 0x4>;
40	};
41
42	mcu_ram: sram@41c00000 {
43		compatible = "mmio-sram";
44		reg = <0x00 0x41c00000 0x00 0x100000>;
45		ranges = <0x00 0x00 0x41c00000 0x100000>;
46		#address-cells = <1>;
47		#size-cells = <1>;
48	};
49
50	wkup_pmx0: pinctrl@4301c000 {
51		compatible = "pinctrl-single";
52		/* Proxy 0 addressing */
53		reg = <0x00 0x4301c000 0x00 0x178>;
54		#pinctrl-cells = <1>;
55		pinctrl-single,register-width = <32>;
56		pinctrl-single,function-mask = <0xffffffff>;
57	};
58
59	wkup_gpio_intr: interrupt-controller@42200000 {
60		compatible = "ti,sci-intr";
61		reg = <0x00 0x42200000 0x00 0x400>;
62		ti,intr-trigger-type = <1>;
63		interrupt-controller;
64		interrupt-parent = <&gic500>;
65		#interrupt-cells = <1>;
66		ti,sci = <&sms>;
67		ti,sci-dev-id = <125>;
68		ti,interrupt-ranges = <16 928 16>;
69	};
70
71	mcu_conf: syscon@40f00000 {
72		compatible = "syscon", "simple-mfd";
73		reg = <0x0 0x40f00000 0x0 0x20000>;
74		#address-cells = <1>;
75		#size-cells = <1>;
76		ranges = <0x0 0x0 0x40f00000 0x20000>;
77
78		phy_gmii_sel: phy@4040 {
79			compatible = "ti,am654-phy-gmii-sel";
80			reg = <0x4040 0x4>;
81			#phy-cells = <1>;
82		};
83
84	};
85
86	wkup_uart0: serial@42300000 {
87		compatible = "ti,j721e-uart", "ti,am654-uart";
88		reg = <0x00 0x42300000 0x00 0x200>;
89		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
90		current-speed = <115200>;
91		clocks = <&k3_clks 359 3>;
92		clock-names = "fclk";
93		power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
94	};
95
96	mcu_uart0: serial@40a00000 {
97		compatible = "ti,j721e-uart", "ti,am654-uart";
98		reg = <0x00 0x40a00000 0x00 0x200>;
99		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
100		current-speed = <115200>;
101		clocks = <&k3_clks 149 3>;
102		clock-names = "fclk";
103		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
104	};
105
106	wkup_gpio0: gpio@42110000 {
107		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
108		reg = <0x00 0x42110000 0x00 0x100>;
109		gpio-controller;
110		#gpio-cells = <2>;
111		interrupt-parent = <&main_gpio_intr>;
112		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
113		interrupt-controller;
114		#interrupt-cells = <2>;
115		ti,ngpio = <89>;
116		ti,davinci-gpio-unbanked = <0>;
117		power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
118		clocks = <&k3_clks 115 0>;
119		clock-names = "gpio";
120	};
121
122	wkup_gpio1: gpio@42100000 {
123		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
124		reg = <0x00 0x42100000 0x00 0x100>;
125		gpio-controller;
126		#gpio-cells = <2>;
127		interrupt-parent = <&main_gpio_intr>;
128		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
129		interrupt-controller;
130		#interrupt-cells = <2>;
131		ti,ngpio = <89>;
132		ti,davinci-gpio-unbanked = <0>;
133		power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
134		clocks = <&k3_clks 116 0>;
135		clock-names = "gpio";
136	};
137
138	wkup_i2c0: i2c@42120000 {
139		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
140		reg = <0x00 0x42120000 0x00 0x100>;
141		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
142		#address-cells = <1>;
143		#size-cells = <0>;
144		clocks = <&k3_clks 223 1>;
145		clock-names = "fck";
146		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
147	};
148
149	mcu_i2c0: i2c@40b00000 {
150		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
151		reg = <0x00 0x40b00000 0x00 0x100>;
152		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
153		#address-cells = <1>;
154		#size-cells = <0>;
155		clocks = <&k3_clks 221 1>;
156		clock-names = "fck";
157		power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
158	};
159
160	mcu_i2c1: i2c@40b10000 {
161		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
162		reg = <0x00 0x40b10000 0x00 0x100>;
163		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
164		#address-cells = <1>;
165		#size-cells = <0>;
166		clocks = <&k3_clks 222 1>;
167		clock-names = "fck";
168		power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
169	};
170
171	mcu_mcan0: can@40528000 {
172		compatible = "bosch,m_can";
173		reg = <0x00 0x40528000 0x00 0x200>,
174		      <0x00 0x40500000 0x00 0x8000>;
175		reg-names = "m_can", "message_ram";
176		power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
177		clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
178		clock-names = "hclk", "cclk";
179		interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
180			     <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
181		interrupt-names = "int0", "int1";
182		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
183	};
184
185	mcu_mcan1: can@40568000 {
186		compatible = "bosch,m_can";
187		reg = <0x00 0x40568000 0x00 0x200>,
188		      <0x00 0x40540000 0x00 0x8000>;
189		reg-names = "m_can", "message_ram";
190		power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
191		clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
192		clock-names = "hclk", "cclk";
193		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
194			     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
195		interrupt-names = "int0", "int1";
196		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
197	};
198
199	mcu_navss: bus@28380000{
200		compatible = "simple-mfd";
201		#address-cells = <2>;
202		#size-cells = <2>;
203		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
204		dma-coherent;
205		dma-ranges;
206
207		ti,sci-dev-id = <267>;
208
209		mcu_ringacc: ringacc@2b800000 {
210			compatible = "ti,am654-navss-ringacc";
211			reg = <0x0 0x2b800000 0x0 0x400000>,
212			      <0x0 0x2b000000 0x0 0x400000>,
213			      <0x0 0x28590000 0x0 0x100>,
214			      <0x0 0x2a500000 0x0 0x40000>;
215			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
216			ti,num-rings = <286>;
217			ti,sci-rm-range-gp-rings = <0x1>;
218			ti,sci = <&sms>;
219			ti,sci-dev-id = <272>;
220			msi-parent = <&main_udmass_inta>;
221		};
222
223		mcu_udmap: dma-controller@285c0000 {
224			compatible = "ti,j721e-navss-mcu-udmap";
225			reg = <0x0 0x285c0000 0x0 0x100>,
226			      <0x0 0x2a800000 0x0 0x40000>,
227			      <0x0 0x2aa00000 0x0 0x40000>;
228			reg-names = "gcfg", "rchanrt", "tchanrt";
229			msi-parent = <&main_udmass_inta>;
230			#dma-cells = <1>;
231
232			ti,sci = <&sms>;
233			ti,sci-dev-id = <273>;
234			ti,ringacc = <&mcu_ringacc>;
235			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
236						<0x0f>; /* TX_HCHAN */
237			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
238						<0x0b>; /* RX_HCHAN */
239			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
240		};
241	};
242
243	mcu_cpsw: ethernet@46000000 {
244		compatible = "ti,j721e-cpsw-nuss";
245		#address-cells = <2>;
246		#size-cells = <2>;
247		reg = <0x0 0x46000000 0x0 0x200000>;
248		reg-names = "cpsw_nuss";
249		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
250		dma-coherent;
251		clocks = <&k3_clks 29 28>;
252		clock-names = "fck";
253		power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
254
255		dmas = <&mcu_udmap 0xf000>,
256		       <&mcu_udmap 0xf001>,
257		       <&mcu_udmap 0xf002>,
258		       <&mcu_udmap 0xf003>,
259		       <&mcu_udmap 0xf004>,
260		       <&mcu_udmap 0xf005>,
261		       <&mcu_udmap 0xf006>,
262		       <&mcu_udmap 0xf007>,
263		       <&mcu_udmap 0x7000>;
264		dma-names = "tx0", "tx1", "tx2", "tx3",
265			    "tx4", "tx5", "tx6", "tx7",
266			    "rx";
267
268		ethernet-ports {
269			#address-cells = <1>;
270			#size-cells = <0>;
271
272			cpsw_port1: port@1 {
273				reg = <1>;
274				ti,mac-only;
275				label = "port1";
276				ti,syscon-efuse = <&mcu_conf 0x200>;
277				phys = <&phy_gmii_sel 1>;
278			};
279		};
280
281		davinci_mdio: mdio@f00 {
282			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
283			reg = <0x0 0xf00 0x0 0x100>;
284			#address-cells = <1>;
285			#size-cells = <0>;
286			clocks = <&k3_clks 29 28>;
287			clock-names = "fck";
288			bus_freq = <1000000>;
289		};
290
291		cpts@3d000 {
292			compatible = "ti,am65-cpts";
293			reg = <0x0 0x3d000 0x0 0x400>;
294			clocks = <&k3_clks 29 3>;
295			clock-names = "cpts";
296			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
297			interrupt-names = "cpts";
298			ti,cpts-ext-ts-inputs = <4>;
299			ti,cpts-periodic-outputs = <2>;
300		};
301	};
302};
303