1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 chipid@43000014 { 38 compatible = "ti,am654-chipid"; 39 reg = <0x00 0x43000014 0x00 0x4>; 40 }; 41 42 secure_proxy_sa3: mailbox@43600000 { 43 compatible = "ti,am654-secure-proxy"; 44 #mbox-cells = <1>; 45 reg-names = "target_data", "rt", "scfg"; 46 reg = <0x00 0x43600000 0x00 0x10000>, 47 <0x00 0x44880000 0x00 0x20000>, 48 <0x00 0x44860000 0x00 0x20000>; 49 /* 50 * Marked Disabled: 51 * Node is incomplete as it is meant for bootloaders and 52 * firmware on non-MPU processors 53 */ 54 status = "disabled"; 55 }; 56 57 mcu_ram: sram@41c00000 { 58 compatible = "mmio-sram"; 59 reg = <0x00 0x41c00000 0x00 0x100000>; 60 ranges = <0x00 0x00 0x41c00000 0x100000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 }; 64 65 wkup_pmx0: pinctrl@4301c000 { 66 compatible = "pinctrl-single"; 67 /* Proxy 0 addressing */ 68 reg = <0x00 0x4301c000 0x00 0x034>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <32>; 71 pinctrl-single,function-mask = <0xffffffff>; 72 }; 73 74 wkup_pmx1: pinctrl@4301c038 { 75 compatible = "pinctrl-single"; 76 /* Proxy 0 addressing */ 77 reg = <0x00 0x4301c038 0x00 0x02C>; 78 #pinctrl-cells = <1>; 79 pinctrl-single,register-width = <32>; 80 pinctrl-single,function-mask = <0xffffffff>; 81 }; 82 83 wkup_pmx2: pinctrl@4301c068 { 84 compatible = "pinctrl-single"; 85 /* Proxy 0 addressing */ 86 reg = <0x00 0x4301c068 0x00 0x120>; 87 #pinctrl-cells = <1>; 88 pinctrl-single,register-width = <32>; 89 pinctrl-single,function-mask = <0xffffffff>; 90 }; 91 92 wkup_pmx3: pinctrl@4301c190 { 93 compatible = "pinctrl-single"; 94 /* Proxy 0 addressing */ 95 reg = <0x00 0x4301c190 0x00 0x004>; 96 #pinctrl-cells = <1>; 97 pinctrl-single,register-width = <32>; 98 pinctrl-single,function-mask = <0xffffffff>; 99 }; 100 101 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 102 mcu_timerio_input: pinctrl@40f04200 { 103 compatible = "pinctrl-single"; 104 reg = <0x00 0x40f04200 0x00 0x28>; 105 #pinctrl-cells = <1>; 106 pinctrl-single,register-width = <32>; 107 pinctrl-single,function-mask = <0x0000000f>; 108 /* Non-MPU Firmware usage */ 109 status = "reserved"; 110 }; 111 112 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 113 mcu_timerio_output: pinctrl@40f04280 { 114 compatible = "pinctrl-single"; 115 reg = <0x00 0x40f04280 0x00 0x28>; 116 #pinctrl-cells = <1>; 117 pinctrl-single,register-width = <32>; 118 pinctrl-single,function-mask = <0x0000000f>; 119 /* Non-MPU Firmware usage */ 120 status = "reserved"; 121 }; 122 123 wkup_gpio_intr: interrupt-controller@42200000 { 124 compatible = "ti,sci-intr"; 125 reg = <0x00 0x42200000 0x00 0x400>; 126 ti,intr-trigger-type = <1>; 127 interrupt-controller; 128 interrupt-parent = <&gic500>; 129 #interrupt-cells = <1>; 130 ti,sci = <&sms>; 131 ti,sci-dev-id = <125>; 132 ti,interrupt-ranges = <16 960 16>; 133 }; 134 135 mcu_conf: syscon@40f00000 { 136 compatible = "syscon", "simple-mfd"; 137 reg = <0x0 0x40f00000 0x0 0x20000>; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges = <0x0 0x0 0x40f00000 0x20000>; 141 142 phy_gmii_sel: phy@4040 { 143 compatible = "ti,am654-phy-gmii-sel"; 144 reg = <0x4040 0x4>; 145 #phy-cells = <1>; 146 }; 147 148 }; 149 150 mcu_timer0: timer@40400000 { 151 compatible = "ti,am654-timer"; 152 reg = <0x00 0x40400000 0x00 0x400>; 153 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&k3_clks 35 1>; 155 clock-names = "fck"; 156 assigned-clocks = <&k3_clks 35 1>; 157 assigned-clock-parents = <&k3_clks 35 2>; 158 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 159 ti,timer-pwm; 160 /* Non-MPU Firmware usage */ 161 status = "reserved"; 162 }; 163 164 mcu_timer1: timer@40410000 { 165 compatible = "ti,am654-timer"; 166 reg = <0x00 0x40410000 0x00 0x400>; 167 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&k3_clks 83 1>; 169 clock-names = "fck"; 170 assigned-clocks = <&k3_clks 83 1>; 171 assigned-clock-parents = <&k3_clks 83 2>; 172 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 173 ti,timer-pwm; 174 /* Non-MPU Firmware usage */ 175 status = "reserved"; 176 }; 177 178 mcu_timer2: timer@40420000 { 179 compatible = "ti,am654-timer"; 180 reg = <0x00 0x40420000 0x00 0x400>; 181 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&k3_clks 84 1>; 183 clock-names = "fck"; 184 assigned-clocks = <&k3_clks 84 1>; 185 assigned-clock-parents = <&k3_clks 84 2>; 186 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 187 ti,timer-pwm; 188 /* Non-MPU Firmware usage */ 189 status = "reserved"; 190 }; 191 192 mcu_timer3: timer@40430000 { 193 compatible = "ti,am654-timer"; 194 reg = <0x00 0x40430000 0x00 0x400>; 195 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&k3_clks 85 1>; 197 clock-names = "fck"; 198 assigned-clocks = <&k3_clks 85 1>; 199 assigned-clock-parents = <&k3_clks 85 2>; 200 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 201 ti,timer-pwm; 202 /* Non-MPU Firmware usage */ 203 status = "reserved"; 204 }; 205 206 mcu_timer4: timer@40440000 { 207 compatible = "ti,am654-timer"; 208 reg = <0x00 0x40440000 0x00 0x400>; 209 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&k3_clks 86 1>; 211 clock-names = "fck"; 212 assigned-clocks = <&k3_clks 86 1>; 213 assigned-clock-parents = <&k3_clks 86 2>; 214 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 215 ti,timer-pwm; 216 /* Non-MPU Firmware usage */ 217 status = "reserved"; 218 }; 219 220 mcu_timer5: timer@40450000 { 221 compatible = "ti,am654-timer"; 222 reg = <0x00 0x40450000 0x00 0x400>; 223 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&k3_clks 87 1>; 225 clock-names = "fck"; 226 assigned-clocks = <&k3_clks 87 1>; 227 assigned-clock-parents = <&k3_clks 87 2>; 228 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 229 ti,timer-pwm; 230 /* Non-MPU Firmware usage */ 231 status = "reserved"; 232 }; 233 234 mcu_timer6: timer@40460000 { 235 compatible = "ti,am654-timer"; 236 reg = <0x00 0x40460000 0x00 0x400>; 237 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&k3_clks 88 1>; 239 clock-names = "fck"; 240 assigned-clocks = <&k3_clks 88 1>; 241 assigned-clock-parents = <&k3_clks 88 2>; 242 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 243 ti,timer-pwm; 244 /* Non-MPU Firmware usage */ 245 status = "reserved"; 246 }; 247 248 mcu_timer7: timer@40470000 { 249 compatible = "ti,am654-timer"; 250 reg = <0x00 0x40470000 0x00 0x400>; 251 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&k3_clks 89 1>; 253 clock-names = "fck"; 254 assigned-clocks = <&k3_clks 89 1>; 255 assigned-clock-parents = <&k3_clks 89 2>; 256 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 257 ti,timer-pwm; 258 /* Non-MPU Firmware usage */ 259 status = "reserved"; 260 }; 261 262 mcu_timer8: timer@40480000 { 263 compatible = "ti,am654-timer"; 264 reg = <0x00 0x40480000 0x00 0x400>; 265 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&k3_clks 90 1>; 267 clock-names = "fck"; 268 assigned-clocks = <&k3_clks 90 1>; 269 assigned-clock-parents = <&k3_clks 90 2>; 270 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 271 ti,timer-pwm; 272 /* Non-MPU Firmware usage */ 273 status = "reserved"; 274 }; 275 276 mcu_timer9: timer@40490000 { 277 compatible = "ti,am654-timer"; 278 reg = <0x00 0x40490000 0x00 0x400>; 279 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&k3_clks 91 1>; 281 clock-names = "fck"; 282 assigned-clocks = <&k3_clks 91 1>; 283 assigned-clock-parents = <&k3_clks 91 2>; 284 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 285 ti,timer-pwm; 286 /* Non-MPU Firmware usage */ 287 status = "reserved"; 288 }; 289 290 wkup_uart0: serial@42300000 { 291 compatible = "ti,j721e-uart", "ti,am654-uart"; 292 reg = <0x00 0x42300000 0x00 0x200>; 293 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 294 current-speed = <115200>; 295 clocks = <&k3_clks 359 3>; 296 clock-names = "fclk"; 297 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 298 status = "disabled"; 299 }; 300 301 mcu_uart0: serial@40a00000 { 302 compatible = "ti,j721e-uart", "ti,am654-uart"; 303 reg = <0x00 0x40a00000 0x00 0x200>; 304 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 305 current-speed = <115200>; 306 clocks = <&k3_clks 149 3>; 307 clock-names = "fclk"; 308 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 309 status = "disabled"; 310 }; 311 312 wkup_gpio0: gpio@42110000 { 313 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 314 reg = <0x00 0x42110000 0x00 0x100>; 315 gpio-controller; 316 #gpio-cells = <2>; 317 interrupt-parent = <&wkup_gpio_intr>; 318 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 ti,ngpio = <89>; 322 ti,davinci-gpio-unbanked = <0>; 323 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 324 clocks = <&k3_clks 115 0>; 325 clock-names = "gpio"; 326 }; 327 328 wkup_gpio1: gpio@42100000 { 329 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 330 reg = <0x00 0x42100000 0x00 0x100>; 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-parent = <&wkup_gpio_intr>; 334 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 ti,ngpio = <89>; 338 ti,davinci-gpio-unbanked = <0>; 339 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 340 clocks = <&k3_clks 116 0>; 341 clock-names = "gpio"; 342 }; 343 344 wkup_i2c0: i2c@42120000 { 345 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 346 reg = <0x00 0x42120000 0x00 0x100>; 347 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 clocks = <&k3_clks 223 1>; 351 clock-names = "fck"; 352 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 353 status = "disabled"; 354 }; 355 356 mcu_i2c0: i2c@40b00000 { 357 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 358 reg = <0x00 0x40b00000 0x00 0x100>; 359 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 clocks = <&k3_clks 221 1>; 363 clock-names = "fck"; 364 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 365 status = "disabled"; 366 }; 367 368 mcu_i2c1: i2c@40b10000 { 369 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 370 reg = <0x00 0x40b10000 0x00 0x100>; 371 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 clocks = <&k3_clks 222 1>; 375 clock-names = "fck"; 376 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 377 status = "disabled"; 378 }; 379 380 mcu_mcan0: can@40528000 { 381 compatible = "bosch,m_can"; 382 reg = <0x00 0x40528000 0x00 0x200>, 383 <0x00 0x40500000 0x00 0x8000>; 384 reg-names = "m_can", "message_ram"; 385 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; 386 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; 387 clock-names = "hclk", "cclk"; 388 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-names = "int0", "int1"; 391 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 392 status = "disabled"; 393 }; 394 395 mcu_mcan1: can@40568000 { 396 compatible = "bosch,m_can"; 397 reg = <0x00 0x40568000 0x00 0x200>, 398 <0x00 0x40540000 0x00 0x8000>; 399 reg-names = "m_can", "message_ram"; 400 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; 402 clock-names = "hclk", "cclk"; 403 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-names = "int0", "int1"; 406 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 407 status = "disabled"; 408 }; 409 410 mcu_spi0: spi@40300000 { 411 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 412 reg = <0x00 0x040300000 0x00 0x400>; 413 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 417 clocks = <&k3_clks 347 0>; 418 status = "disabled"; 419 }; 420 421 mcu_spi1: spi@40310000 { 422 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 423 reg = <0x00 0x040310000 0x00 0x400>; 424 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 428 clocks = <&k3_clks 348 0>; 429 status = "disabled"; 430 }; 431 432 mcu_spi2: spi@40320000 { 433 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 434 reg = <0x00 0x040320000 0x00 0x400>; 435 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 439 clocks = <&k3_clks 349 0>; 440 status = "disabled"; 441 }; 442 443 mcu_navss: bus@28380000 { 444 compatible = "simple-mfd"; 445 #address-cells = <2>; 446 #size-cells = <2>; 447 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 448 dma-coherent; 449 dma-ranges; 450 451 ti,sci-dev-id = <267>; 452 453 mcu_ringacc: ringacc@2b800000 { 454 compatible = "ti,am654-navss-ringacc"; 455 reg = <0x0 0x2b800000 0x0 0x400000>, 456 <0x0 0x2b000000 0x0 0x400000>, 457 <0x0 0x28590000 0x0 0x100>, 458 <0x0 0x2a500000 0x0 0x40000>, 459 <0x0 0x28440000 0x0 0x40000>; 460 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 461 ti,num-rings = <286>; 462 ti,sci-rm-range-gp-rings = <0x1>; 463 ti,sci = <&sms>; 464 ti,sci-dev-id = <272>; 465 msi-parent = <&main_udmass_inta>; 466 }; 467 468 mcu_udmap: dma-controller@285c0000 { 469 compatible = "ti,j721e-navss-mcu-udmap"; 470 reg = <0x0 0x285c0000 0x0 0x100>, 471 <0x0 0x2a800000 0x0 0x40000>, 472 <0x0 0x2aa00000 0x0 0x40000>; 473 reg-names = "gcfg", "rchanrt", "tchanrt"; 474 msi-parent = <&main_udmass_inta>; 475 #dma-cells = <1>; 476 477 ti,sci = <&sms>; 478 ti,sci-dev-id = <273>; 479 ti,ringacc = <&mcu_ringacc>; 480 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 481 <0x0f>; /* TX_HCHAN */ 482 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 483 <0x0b>; /* RX_HCHAN */ 484 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 485 }; 486 }; 487 488 secure_proxy_mcu: mailbox@2a480000 { 489 compatible = "ti,am654-secure-proxy"; 490 #mbox-cells = <1>; 491 reg-names = "target_data", "rt", "scfg"; 492 reg = <0x00 0x2a480000 0x00 0x80000>, 493 <0x00 0x2a380000 0x00 0x80000>, 494 <0x00 0x2a400000 0x00 0x80000>; 495 /* 496 * Marked Disabled: 497 * Node is incomplete as it is meant for bootloaders and 498 * firmware on non-MPU processors 499 */ 500 status = "disabled"; 501 }; 502 503 mcu_cpsw: ethernet@46000000 { 504 compatible = "ti,j721e-cpsw-nuss"; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 reg = <0x0 0x46000000 0x0 0x200000>; 508 reg-names = "cpsw_nuss"; 509 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 510 dma-coherent; 511 clocks = <&k3_clks 29 28>; 512 clock-names = "fck"; 513 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 514 515 dmas = <&mcu_udmap 0xf000>, 516 <&mcu_udmap 0xf001>, 517 <&mcu_udmap 0xf002>, 518 <&mcu_udmap 0xf003>, 519 <&mcu_udmap 0xf004>, 520 <&mcu_udmap 0xf005>, 521 <&mcu_udmap 0xf006>, 522 <&mcu_udmap 0xf007>, 523 <&mcu_udmap 0x7000>; 524 dma-names = "tx0", "tx1", "tx2", "tx3", 525 "tx4", "tx5", "tx6", "tx7", 526 "rx"; 527 528 ethernet-ports { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 cpsw_port1: port@1 { 533 reg = <1>; 534 ti,mac-only; 535 label = "port1"; 536 ti,syscon-efuse = <&mcu_conf 0x200>; 537 phys = <&phy_gmii_sel 1>; 538 }; 539 }; 540 541 davinci_mdio: mdio@f00 { 542 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 543 reg = <0x0 0xf00 0x0 0x100>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&k3_clks 29 28>; 547 clock-names = "fck"; 548 bus_freq = <1000000>; 549 }; 550 551 cpts@3d000 { 552 compatible = "ti,am65-cpts"; 553 reg = <0x0 0x3d000 0x0 0x400>; 554 clocks = <&k3_clks 29 3>; 555 clock-names = "cpts"; 556 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ 557 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ 558 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 559 interrupt-names = "cpts"; 560 ti,cpts-ext-ts-inputs = <4>; 561 ti,cpts-periodic-outputs = <2>; 562 }; 563 }; 564 565 tscadc0: tscadc@40200000 { 566 compatible = "ti,am3359-tscadc"; 567 reg = <0x00 0x40200000 0x00 0x1000>; 568 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 569 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 570 clocks = <&k3_clks 0 0>; 571 assigned-clocks = <&k3_clks 0 2>; 572 assigned-clock-rates = <60000000>; 573 clock-names = "fck"; 574 dmas = <&main_udmap 0x7400>, 575 <&main_udmap 0x7401>; 576 dma-names = "fifo0", "fifo1"; 577 status = "disabled"; 578 579 adc { 580 #io-channel-cells = <1>; 581 compatible = "ti,am3359-adc"; 582 }; 583 }; 584 585 tscadc1: tscadc@40210000 { 586 compatible = "ti,am3359-tscadc"; 587 reg = <0x00 0x40210000 0x00 0x1000>; 588 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 589 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 590 clocks = <&k3_clks 1 0>; 591 assigned-clocks = <&k3_clks 1 2>; 592 assigned-clock-rates = <60000000>; 593 clock-names = "fck"; 594 dmas = <&main_udmap 0x7402>, 595 <&main_udmap 0x7403>; 596 dma-names = "fifo0", "fifo1"; 597 status = "disabled"; 598 599 adc { 600 #io-channel-cells = <1>; 601 compatible = "ti,am3359-adc"; 602 }; 603 }; 604 605 fss: bus@47000000 { 606 compatible = "simple-bus"; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 610 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 611 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 612 613 ospi0: spi@47040000 { 614 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 615 reg = <0x00 0x47040000 0x00 0x100>, 616 <0x05 0x00000000 0x01 0x00000000>; 617 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 618 cdns,fifo-depth = <256>; 619 cdns,fifo-width = <4>; 620 cdns,trigger-address = <0x0>; 621 clocks = <&k3_clks 109 5>; 622 assigned-clocks = <&k3_clks 109 5>; 623 assigned-clock-parents = <&k3_clks 109 7>; 624 assigned-clock-rates = <166666666>; 625 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 629 status = "disabled"; /* Needs pinmux */ 630 }; 631 632 ospi1: spi@47050000 { 633 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 634 reg = <0x00 0x47050000 0x00 0x100>, 635 <0x07 0x00000000 0x01 0x00000000>; 636 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 637 cdns,fifo-depth = <256>; 638 cdns,fifo-width = <4>; 639 cdns,trigger-address = <0x0>; 640 clocks = <&k3_clks 110 5>; 641 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 status = "disabled"; /* Needs pinmux */ 646 }; 647 }; 648 649 wkup_vtm0: temperature-sensor@42040000 { 650 compatible = "ti,j7200-vtm"; 651 reg = <0x00 0x42040000 0x0 0x350>, 652 <0x00 0x42050000 0x0 0x350>; 653 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; 654 #thermal-sensor-cells = <1>; 655 }; 656}; 657