1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 msmc_ram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x0 0x70000000 0x0 0x400000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x0 0x70000000 0x400000>; 26 27 atf-sram@0 { 28 reg = <0x0 0x20000>; 29 }; 30 31 tifs-sram@1f0000 { 32 reg = <0x1f0000 0x10000>; 33 }; 34 35 l3cache-sram@200000 { 36 reg = <0x200000 0x200000>; 37 }; 38 }; 39 40 scm_conf: syscon@104000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x00 0x00104000 0x00 0x18000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x00 0x00 0x00104000 0x18000>; 46 47 usb_serdes_mux: mux-controller@0 { 48 compatible = "mmio-mux"; 49 reg = <0x0 0x4>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 52 }; 53 54 serdes_ln_ctrl: mux-controller@80 { 55 compatible = "mmio-mux"; 56 reg = <0x80 0x10>; 57 #mux-control-cells = <1>; 58 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ 59 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ 60 }; 61 }; 62 63 gic500: interrupt-controller@1800000 { 64 compatible = "arm,gic-v3"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 #interrupt-cells = <3>; 69 interrupt-controller; 70 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 71 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 72 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 73 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 74 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 75 76 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 77 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 78 79 gic_its: msi-controller@1820000 { 80 compatible = "arm,gic-v3-its"; 81 reg = <0x00 0x01820000 0x00 0x10000>; 82 socionext,synquacer-pre-its = <0x1000000 0x400000>; 83 msi-controller; 84 #msi-cells = <1>; 85 }; 86 }; 87 88 main_gpio_intr: interrupt-controller@a00000 { 89 compatible = "ti,sci-intr"; 90 reg = <0x00 0x00a00000 0x00 0x800>; 91 ti,intr-trigger-type = <1>; 92 interrupt-controller; 93 interrupt-parent = <&gic500>; 94 #interrupt-cells = <1>; 95 ti,sci = <&sms>; 96 ti,sci-dev-id = <148>; 97 ti,interrupt-ranges = <8 392 56>; 98 }; 99 100 main_pmx0: pinctrl@11c000 { 101 compatible = "pinctrl-single"; 102 /* Proxy 0 addressing */ 103 reg = <0x0 0x11c000 0x0 0x120>; 104 #pinctrl-cells = <1>; 105 pinctrl-single,register-width = <32>; 106 pinctrl-single,function-mask = <0xffffffff>; 107 }; 108 109 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 110 main_timerio_input: pinctrl@104200 { 111 compatible = "pinctrl-single"; 112 reg = <0x00 0x104200 0x00 0x50>; 113 #pinctrl-cells = <1>; 114 pinctrl-single,register-width = <32>; 115 pinctrl-single,function-mask = <0x00000007>; 116 }; 117 118 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 119 main_timerio_output: pinctrl@104280 { 120 compatible = "pinctrl-single"; 121 reg = <0x00 0x104280 0x00 0x20>; 122 #pinctrl-cells = <1>; 123 pinctrl-single,register-width = <32>; 124 pinctrl-single,function-mask = <0x0000001f>; 125 }; 126 127 main_crypto: crypto@4e00000 { 128 compatible = "ti,j721e-sa2ul"; 129 reg = <0x00 0x04e00000 0x00 0x1200>; 130 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 134 135 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 136 <&main_udmap 0x4a41>; 137 dma-names = "tx", "rx1", "rx2"; 138 139 rng: rng@4e10000 { 140 compatible = "inside-secure,safexcel-eip76"; 141 reg = <0x00 0x04e10000 0x00 0x7d>; 142 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 }; 145 146 main_timer0: timer@2400000 { 147 compatible = "ti,am654-timer"; 148 reg = <0x00 0x2400000 0x00 0x400>; 149 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&k3_clks 63 1>; 151 clock-names = "fck"; 152 assigned-clocks = <&k3_clks 63 1>; 153 assigned-clock-parents = <&k3_clks 63 2>; 154 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 155 ti,timer-pwm; 156 }; 157 158 main_timer1: timer@2410000 { 159 compatible = "ti,am654-timer"; 160 reg = <0x00 0x2410000 0x00 0x400>; 161 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&k3_clks 64 1>; 163 clock-names = "fck"; 164 assigned-clocks = <&k3_clks 64 1>; 165 assigned-clock-parents = <&k3_clks 64 2>; 166 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 167 ti,timer-pwm; 168 }; 169 170 main_timer2: timer@2420000 { 171 compatible = "ti,am654-timer"; 172 reg = <0x00 0x2420000 0x00 0x400>; 173 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&k3_clks 65 1>; 175 clock-names = "fck"; 176 assigned-clocks = <&k3_clks 65 1>; 177 assigned-clock-parents = <&k3_clks 65 2>; 178 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 179 ti,timer-pwm; 180 }; 181 182 main_timer3: timer@2430000 { 183 compatible = "ti,am654-timer"; 184 reg = <0x00 0x2430000 0x00 0x400>; 185 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&k3_clks 66 1>; 187 clock-names = "fck"; 188 assigned-clocks = <&k3_clks 66 1>; 189 assigned-clock-parents = <&k3_clks 66 2>; 190 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 191 ti,timer-pwm; 192 }; 193 194 main_timer4: timer@2440000 { 195 compatible = "ti,am654-timer"; 196 reg = <0x00 0x2440000 0x00 0x400>; 197 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&k3_clks 67 1>; 199 clock-names = "fck"; 200 assigned-clocks = <&k3_clks 67 1>; 201 assigned-clock-parents = <&k3_clks 67 2>; 202 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 203 ti,timer-pwm; 204 }; 205 206 main_timer5: timer@2450000 { 207 compatible = "ti,am654-timer"; 208 reg = <0x00 0x2450000 0x00 0x400>; 209 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&k3_clks 68 1>; 211 clock-names = "fck"; 212 assigned-clocks = <&k3_clks 68 1>; 213 assigned-clock-parents = <&k3_clks 68 2>; 214 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 215 ti,timer-pwm; 216 }; 217 218 main_timer6: timer@2460000 { 219 compatible = "ti,am654-timer"; 220 reg = <0x00 0x2460000 0x00 0x400>; 221 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&k3_clks 69 1>; 223 clock-names = "fck"; 224 assigned-clocks = <&k3_clks 69 1>; 225 assigned-clock-parents = <&k3_clks 69 2>; 226 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 227 ti,timer-pwm; 228 }; 229 230 main_timer7: timer@2470000 { 231 compatible = "ti,am654-timer"; 232 reg = <0x00 0x2470000 0x00 0x400>; 233 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&k3_clks 70 1>; 235 clock-names = "fck"; 236 assigned-clocks = <&k3_clks 70 1>; 237 assigned-clock-parents = <&k3_clks 70 2>; 238 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 239 ti,timer-pwm; 240 }; 241 242 main_timer8: timer@2480000 { 243 compatible = "ti,am654-timer"; 244 reg = <0x00 0x2480000 0x00 0x400>; 245 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&k3_clks 71 1>; 247 clock-names = "fck"; 248 assigned-clocks = <&k3_clks 71 1>; 249 assigned-clock-parents = <&k3_clks 71 2>; 250 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 251 ti,timer-pwm; 252 }; 253 254 main_timer9: timer@2490000 { 255 compatible = "ti,am654-timer"; 256 reg = <0x00 0x2490000 0x00 0x400>; 257 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&k3_clks 72 1>; 259 clock-names = "fck"; 260 assigned-clocks = <&k3_clks 72 1>; 261 assigned-clock-parents = <&k3_clks 72 2>; 262 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 263 ti,timer-pwm; 264 }; 265 266 main_timer10: timer@24a0000 { 267 compatible = "ti,am654-timer"; 268 reg = <0x00 0x24a0000 0x00 0x400>; 269 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&k3_clks 73 1>; 271 clock-names = "fck"; 272 assigned-clocks = <&k3_clks 73 1>; 273 assigned-clock-parents = <&k3_clks 73 2>; 274 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 275 ti,timer-pwm; 276 }; 277 278 main_timer11: timer@24b0000 { 279 compatible = "ti,am654-timer"; 280 reg = <0x00 0x24b0000 0x00 0x400>; 281 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&k3_clks 74 1>; 283 clock-names = "fck"; 284 assigned-clocks = <&k3_clks 74 1>; 285 assigned-clock-parents = <&k3_clks 74 2>; 286 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 287 ti,timer-pwm; 288 }; 289 290 main_timer12: timer@24c0000 { 291 compatible = "ti,am654-timer"; 292 reg = <0x00 0x24c0000 0x00 0x400>; 293 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&k3_clks 75 1>; 295 clock-names = "fck"; 296 assigned-clocks = <&k3_clks 75 1>; 297 assigned-clock-parents = <&k3_clks 75 2>; 298 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 299 ti,timer-pwm; 300 }; 301 302 main_timer13: timer@24d0000 { 303 compatible = "ti,am654-timer"; 304 reg = <0x00 0x24d0000 0x00 0x400>; 305 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&k3_clks 76 1>; 307 clock-names = "fck"; 308 assigned-clocks = <&k3_clks 76 1>; 309 assigned-clock-parents = <&k3_clks 76 2>; 310 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 311 ti,timer-pwm; 312 }; 313 314 main_timer14: timer@24e0000 { 315 compatible = "ti,am654-timer"; 316 reg = <0x00 0x24e0000 0x00 0x400>; 317 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&k3_clks 77 1>; 319 clock-names = "fck"; 320 assigned-clocks = <&k3_clks 77 1>; 321 assigned-clock-parents = <&k3_clks 77 2>; 322 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 323 ti,timer-pwm; 324 }; 325 326 main_timer15: timer@24f0000 { 327 compatible = "ti,am654-timer"; 328 reg = <0x00 0x24f0000 0x00 0x400>; 329 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&k3_clks 78 1>; 331 clock-names = "fck"; 332 assigned-clocks = <&k3_clks 78 1>; 333 assigned-clock-parents = <&k3_clks 78 2>; 334 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 335 ti,timer-pwm; 336 }; 337 338 main_timer16: timer@2500000 { 339 compatible = "ti,am654-timer"; 340 reg = <0x00 0x2500000 0x00 0x400>; 341 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&k3_clks 79 1>; 343 clock-names = "fck"; 344 assigned-clocks = <&k3_clks 79 1>; 345 assigned-clock-parents = <&k3_clks 79 2>; 346 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 347 ti,timer-pwm; 348 }; 349 350 main_timer17: timer@2510000 { 351 compatible = "ti,am654-timer"; 352 reg = <0x00 0x2510000 0x00 0x400>; 353 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&k3_clks 80 1>; 355 clock-names = "fck"; 356 assigned-clocks = <&k3_clks 80 1>; 357 assigned-clock-parents = <&k3_clks 80 2>; 358 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 359 ti,timer-pwm; 360 }; 361 362 main_timer18: timer@2520000 { 363 compatible = "ti,am654-timer"; 364 reg = <0x00 0x2520000 0x00 0x400>; 365 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&k3_clks 81 1>; 367 clock-names = "fck"; 368 assigned-clocks = <&k3_clks 81 1>; 369 assigned-clock-parents = <&k3_clks 81 2>; 370 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 371 ti,timer-pwm; 372 }; 373 374 main_timer19: timer@2530000 { 375 compatible = "ti,am654-timer"; 376 reg = <0x00 0x2530000 0x00 0x400>; 377 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&k3_clks 82 1>; 379 clock-names = "fck"; 380 assigned-clocks = <&k3_clks 82 1>; 381 assigned-clock-parents = <&k3_clks 82 2>; 382 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 383 ti,timer-pwm; 384 }; 385 386 main_uart0: serial@2800000 { 387 compatible = "ti,j721e-uart", "ti,am654-uart"; 388 reg = <0x00 0x02800000 0x00 0x200>; 389 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 390 current-speed = <115200>; 391 clocks = <&k3_clks 146 3>; 392 clock-names = "fclk"; 393 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 394 status = "disabled"; 395 }; 396 397 main_uart1: serial@2810000 { 398 compatible = "ti,j721e-uart", "ti,am654-uart"; 399 reg = <0x00 0x02810000 0x00 0x200>; 400 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 401 current-speed = <115200>; 402 clocks = <&k3_clks 350 3>; 403 clock-names = "fclk"; 404 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 405 status = "disabled"; 406 }; 407 408 main_uart2: serial@2820000 { 409 compatible = "ti,j721e-uart", "ti,am654-uart"; 410 reg = <0x00 0x02820000 0x00 0x200>; 411 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 412 current-speed = <115200>; 413 clocks = <&k3_clks 351 3>; 414 clock-names = "fclk"; 415 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 416 status = "disabled"; 417 }; 418 419 main_uart3: serial@2830000 { 420 compatible = "ti,j721e-uart", "ti,am654-uart"; 421 reg = <0x00 0x02830000 0x00 0x200>; 422 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 423 current-speed = <115200>; 424 clocks = <&k3_clks 352 3>; 425 clock-names = "fclk"; 426 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 427 status = "disabled"; 428 }; 429 430 main_uart4: serial@2840000 { 431 compatible = "ti,j721e-uart", "ti,am654-uart"; 432 reg = <0x00 0x02840000 0x00 0x200>; 433 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 434 current-speed = <115200>; 435 clocks = <&k3_clks 353 3>; 436 clock-names = "fclk"; 437 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 438 status = "disabled"; 439 }; 440 441 main_uart5: serial@2850000 { 442 compatible = "ti,j721e-uart", "ti,am654-uart"; 443 reg = <0x00 0x02850000 0x00 0x200>; 444 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 445 current-speed = <115200>; 446 clocks = <&k3_clks 354 3>; 447 clock-names = "fclk"; 448 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 449 status = "disabled"; 450 }; 451 452 main_uart6: serial@2860000 { 453 compatible = "ti,j721e-uart", "ti,am654-uart"; 454 reg = <0x00 0x02860000 0x00 0x200>; 455 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 456 current-speed = <115200>; 457 clocks = <&k3_clks 355 3>; 458 clock-names = "fclk"; 459 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 460 status = "disabled"; 461 }; 462 463 main_uart7: serial@2870000 { 464 compatible = "ti,j721e-uart", "ti,am654-uart"; 465 reg = <0x00 0x02870000 0x00 0x200>; 466 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 467 current-speed = <115200>; 468 clocks = <&k3_clks 356 3>; 469 clock-names = "fclk"; 470 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 471 status = "disabled"; 472 }; 473 474 main_uart8: serial@2880000 { 475 compatible = "ti,j721e-uart", "ti,am654-uart"; 476 reg = <0x00 0x02880000 0x00 0x200>; 477 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 478 current-speed = <115200>; 479 clocks = <&k3_clks 357 3>; 480 clock-names = "fclk"; 481 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 482 status = "disabled"; 483 }; 484 485 main_uart9: serial@2890000 { 486 compatible = "ti,j721e-uart", "ti,am654-uart"; 487 reg = <0x00 0x02890000 0x00 0x200>; 488 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 489 current-speed = <115200>; 490 clocks = <&k3_clks 358 3>; 491 clock-names = "fclk"; 492 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 493 status = "disabled"; 494 }; 495 496 main_gpio0: gpio@600000 { 497 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 498 reg = <0x00 0x00600000 0x00 0x100>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-parent = <&main_gpio_intr>; 502 interrupts = <145>, <146>, <147>, <148>, <149>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 ti,ngpio = <66>; 506 ti,davinci-gpio-unbanked = <0>; 507 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 508 clocks = <&k3_clks 111 0>; 509 clock-names = "gpio"; 510 }; 511 512 main_gpio2: gpio@610000 { 513 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 514 reg = <0x00 0x00610000 0x00 0x100>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-parent = <&main_gpio_intr>; 518 interrupts = <154>, <155>, <156>, <157>, <158>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 ti,ngpio = <66>; 522 ti,davinci-gpio-unbanked = <0>; 523 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 524 clocks = <&k3_clks 112 0>; 525 clock-names = "gpio"; 526 }; 527 528 main_gpio4: gpio@620000 { 529 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 530 reg = <0x00 0x00620000 0x00 0x100>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-parent = <&main_gpio_intr>; 534 interrupts = <163>, <164>, <165>, <166>, <167>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 ti,ngpio = <66>; 538 ti,davinci-gpio-unbanked = <0>; 539 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 113 0>; 541 clock-names = "gpio"; 542 }; 543 544 main_gpio6: gpio@630000 { 545 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 546 reg = <0x00 0x00630000 0x00 0x100>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 interrupt-parent = <&main_gpio_intr>; 550 interrupts = <172>, <173>, <174>, <175>, <176>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 ti,ngpio = <66>; 554 ti,davinci-gpio-unbanked = <0>; 555 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 556 clocks = <&k3_clks 114 0>; 557 clock-names = "gpio"; 558 }; 559 560 main_i2c0: i2c@2000000 { 561 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 562 reg = <0x00 0x02000000 0x00 0x100>; 563 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 clocks = <&k3_clks 214 1>; 567 clock-names = "fck"; 568 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 569 }; 570 571 main_i2c1: i2c@2010000 { 572 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 573 reg = <0x00 0x02010000 0x00 0x100>; 574 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 clocks = <&k3_clks 215 1>; 578 clock-names = "fck"; 579 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 580 status = "disabled"; 581 }; 582 583 main_i2c2: i2c@2020000 { 584 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 585 reg = <0x00 0x02020000 0x00 0x100>; 586 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 clocks = <&k3_clks 216 1>; 590 clock-names = "fck"; 591 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 592 status = "disabled"; 593 }; 594 595 main_i2c3: i2c@2030000 { 596 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 597 reg = <0x00 0x02030000 0x00 0x100>; 598 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 clocks = <&k3_clks 217 1>; 602 clock-names = "fck"; 603 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 604 status = "disabled"; 605 }; 606 607 main_i2c4: i2c@2040000 { 608 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 609 reg = <0x00 0x02040000 0x00 0x100>; 610 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 clocks = <&k3_clks 218 1>; 614 clock-names = "fck"; 615 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 616 status = "disabled"; 617 }; 618 619 main_i2c5: i2c@2050000 { 620 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 621 reg = <0x00 0x02050000 0x00 0x100>; 622 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clocks = <&k3_clks 219 1>; 626 clock-names = "fck"; 627 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 628 status = "disabled"; 629 }; 630 631 main_i2c6: i2c@2060000 { 632 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 633 reg = <0x00 0x02060000 0x00 0x100>; 634 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 clocks = <&k3_clks 220 1>; 638 clock-names = "fck"; 639 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 640 status = "disabled"; 641 }; 642 643 main_sdhci0: mmc@4f80000 { 644 compatible = "ti,j721e-sdhci-8bit"; 645 reg = <0x00 0x04f80000 0x00 0x1000>, 646 <0x00 0x04f88000 0x00 0x400>; 647 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 648 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 649 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 650 clock-names = "clk_ahb", "clk_xin"; 651 assigned-clocks = <&k3_clks 98 1>; 652 assigned-clock-parents = <&k3_clks 98 2>; 653 bus-width = <8>; 654 ti,otap-del-sel-legacy = <0x0>; 655 ti,otap-del-sel-mmc-hs = <0x0>; 656 ti,otap-del-sel-ddr52 = <0x6>; 657 ti,otap-del-sel-hs200 = <0x8>; 658 ti,otap-del-sel-hs400 = <0x5>; 659 ti,itap-del-sel-legacy = <0x10>; 660 ti,itap-del-sel-mmc-hs = <0xa>; 661 ti,strobe-sel = <0x77>; 662 ti,clkbuf-sel = <0x7>; 663 ti,trm-icp = <0x8>; 664 mmc-ddr-1_8v; 665 mmc-hs200-1_8v; 666 mmc-hs400-1_8v; 667 dma-coherent; 668 }; 669 670 main_sdhci1: mmc@4fb0000 { 671 compatible = "ti,j721e-sdhci-4bit"; 672 reg = <0x00 0x04fb0000 0x00 0x1000>, 673 <0x00 0x04fb8000 0x00 0x400>; 674 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 675 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 676 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 677 clock-names = "clk_ahb", "clk_xin"; 678 assigned-clocks = <&k3_clks 99 1>; 679 assigned-clock-parents = <&k3_clks 99 2>; 680 bus-width = <4>; 681 ti,otap-del-sel-legacy = <0x0>; 682 ti,otap-del-sel-sd-hs = <0x0>; 683 ti,otap-del-sel-sdr12 = <0xf>; 684 ti,otap-del-sel-sdr25 = <0xf>; 685 ti,otap-del-sel-sdr50 = <0xc>; 686 ti,otap-del-sel-sdr104 = <0x5>; 687 ti,otap-del-sel-ddr50 = <0xc>; 688 ti,itap-del-sel-legacy = <0x0>; 689 ti,itap-del-sel-sd-hs = <0x0>; 690 ti,itap-del-sel-sdr12 = <0x0>; 691 ti,itap-del-sel-sdr25 = <0x0>; 692 ti,clkbuf-sel = <0x7>; 693 ti,trm-icp = <0x8>; 694 dma-coherent; 695 /* Masking support for SDR104 capability */ 696 sdhci-caps-mask = <0x00000003 0x00000000>; 697 }; 698 699 main_navss: bus@30000000 { 700 compatible = "simple-mfd"; 701 #address-cells = <2>; 702 #size-cells = <2>; 703 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 704 ti,sci-dev-id = <224>; 705 dma-coherent; 706 dma-ranges; 707 708 main_navss_intr: interrupt-controller@310e0000 { 709 compatible = "ti,sci-intr"; 710 reg = <0x00 0x310e0000 0x00 0x4000>; 711 ti,intr-trigger-type = <4>; 712 interrupt-controller; 713 interrupt-parent = <&gic500>; 714 #interrupt-cells = <1>; 715 ti,sci = <&sms>; 716 ti,sci-dev-id = <227>; 717 ti,interrupt-ranges = <0 64 64>, 718 <64 448 64>, 719 <128 672 64>; 720 }; 721 722 main_udmass_inta: msi-controller@33d00000 { 723 compatible = "ti,sci-inta"; 724 reg = <0x00 0x33d00000 0x00 0x100000>; 725 interrupt-controller; 726 #interrupt-cells = <0>; 727 interrupt-parent = <&main_navss_intr>; 728 msi-controller; 729 ti,sci = <&sms>; 730 ti,sci-dev-id = <265>; 731 ti,interrupt-ranges = <0 0 256>; 732 }; 733 734 secure_proxy_main: mailbox@32c00000 { 735 compatible = "ti,am654-secure-proxy"; 736 #mbox-cells = <1>; 737 reg-names = "target_data", "rt", "scfg"; 738 reg = <0x00 0x32c00000 0x00 0x100000>, 739 <0x00 0x32400000 0x00 0x100000>, 740 <0x00 0x32800000 0x00 0x100000>; 741 interrupt-names = "rx_011"; 742 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 743 }; 744 745 hwspinlock: spinlock@30e00000 { 746 compatible = "ti,am654-hwspinlock"; 747 reg = <0x00 0x30e00000 0x00 0x1000>; 748 #hwlock-cells = <1>; 749 }; 750 751 mailbox0_cluster0: mailbox@31f80000 { 752 compatible = "ti,am654-mailbox"; 753 reg = <0x00 0x31f80000 0x00 0x200>; 754 #mbox-cells = <1>; 755 ti,mbox-num-users = <4>; 756 ti,mbox-num-fifos = <16>; 757 interrupt-parent = <&main_navss_intr>; 758 status = "disabled"; 759 }; 760 761 mailbox0_cluster1: mailbox@31f81000 { 762 compatible = "ti,am654-mailbox"; 763 reg = <0x00 0x31f81000 0x00 0x200>; 764 #mbox-cells = <1>; 765 ti,mbox-num-users = <4>; 766 ti,mbox-num-fifos = <16>; 767 interrupt-parent = <&main_navss_intr>; 768 status = "disabled"; 769 }; 770 771 mailbox0_cluster2: mailbox@31f82000 { 772 compatible = "ti,am654-mailbox"; 773 reg = <0x00 0x31f82000 0x00 0x200>; 774 #mbox-cells = <1>; 775 ti,mbox-num-users = <4>; 776 ti,mbox-num-fifos = <16>; 777 interrupt-parent = <&main_navss_intr>; 778 status = "disabled"; 779 }; 780 781 mailbox0_cluster3: mailbox@31f83000 { 782 compatible = "ti,am654-mailbox"; 783 reg = <0x00 0x31f83000 0x00 0x200>; 784 #mbox-cells = <1>; 785 ti,mbox-num-users = <4>; 786 ti,mbox-num-fifos = <16>; 787 interrupt-parent = <&main_navss_intr>; 788 status = "disabled"; 789 }; 790 791 mailbox0_cluster4: mailbox@31f84000 { 792 compatible = "ti,am654-mailbox"; 793 reg = <0x00 0x31f84000 0x00 0x200>; 794 #mbox-cells = <1>; 795 ti,mbox-num-users = <4>; 796 ti,mbox-num-fifos = <16>; 797 interrupt-parent = <&main_navss_intr>; 798 status = "disabled"; 799 }; 800 801 mailbox0_cluster5: mailbox@31f85000 { 802 compatible = "ti,am654-mailbox"; 803 reg = <0x00 0x31f85000 0x00 0x200>; 804 #mbox-cells = <1>; 805 ti,mbox-num-users = <4>; 806 ti,mbox-num-fifos = <16>; 807 interrupt-parent = <&main_navss_intr>; 808 status = "disabled"; 809 }; 810 811 mailbox0_cluster6: mailbox@31f86000 { 812 compatible = "ti,am654-mailbox"; 813 reg = <0x00 0x31f86000 0x00 0x200>; 814 #mbox-cells = <1>; 815 ti,mbox-num-users = <4>; 816 ti,mbox-num-fifos = <16>; 817 interrupt-parent = <&main_navss_intr>; 818 status = "disabled"; 819 }; 820 821 mailbox0_cluster7: mailbox@31f87000 { 822 compatible = "ti,am654-mailbox"; 823 reg = <0x00 0x31f87000 0x00 0x200>; 824 #mbox-cells = <1>; 825 ti,mbox-num-users = <4>; 826 ti,mbox-num-fifos = <16>; 827 interrupt-parent = <&main_navss_intr>; 828 status = "disabled"; 829 }; 830 831 mailbox0_cluster8: mailbox@31f88000 { 832 compatible = "ti,am654-mailbox"; 833 reg = <0x00 0x31f88000 0x00 0x200>; 834 #mbox-cells = <1>; 835 ti,mbox-num-users = <4>; 836 ti,mbox-num-fifos = <16>; 837 interrupt-parent = <&main_navss_intr>; 838 status = "disabled"; 839 }; 840 841 mailbox0_cluster9: mailbox@31f89000 { 842 compatible = "ti,am654-mailbox"; 843 reg = <0x00 0x31f89000 0x00 0x200>; 844 #mbox-cells = <1>; 845 ti,mbox-num-users = <4>; 846 ti,mbox-num-fifos = <16>; 847 interrupt-parent = <&main_navss_intr>; 848 status = "disabled"; 849 }; 850 851 mailbox0_cluster10: mailbox@31f8a000 { 852 compatible = "ti,am654-mailbox"; 853 reg = <0x00 0x31f8a000 0x00 0x200>; 854 #mbox-cells = <1>; 855 ti,mbox-num-users = <4>; 856 ti,mbox-num-fifos = <16>; 857 interrupt-parent = <&main_navss_intr>; 858 status = "disabled"; 859 }; 860 861 mailbox0_cluster11: mailbox@31f8b000 { 862 compatible = "ti,am654-mailbox"; 863 reg = <0x00 0x31f8b000 0x00 0x200>; 864 #mbox-cells = <1>; 865 ti,mbox-num-users = <4>; 866 ti,mbox-num-fifos = <16>; 867 interrupt-parent = <&main_navss_intr>; 868 status = "disabled"; 869 }; 870 871 mailbox1_cluster0: mailbox@31f90000 { 872 compatible = "ti,am654-mailbox"; 873 reg = <0x00 0x31f90000 0x00 0x200>; 874 #mbox-cells = <1>; 875 ti,mbox-num-users = <4>; 876 ti,mbox-num-fifos = <16>; 877 interrupt-parent = <&main_navss_intr>; 878 status = "disabled"; 879 }; 880 881 mailbox1_cluster1: mailbox@31f91000 { 882 compatible = "ti,am654-mailbox"; 883 reg = <0x00 0x31f91000 0x00 0x200>; 884 #mbox-cells = <1>; 885 ti,mbox-num-users = <4>; 886 ti,mbox-num-fifos = <16>; 887 interrupt-parent = <&main_navss_intr>; 888 status = "disabled"; 889 }; 890 891 mailbox1_cluster2: mailbox@31f92000 { 892 compatible = "ti,am654-mailbox"; 893 reg = <0x00 0x31f92000 0x00 0x200>; 894 #mbox-cells = <1>; 895 ti,mbox-num-users = <4>; 896 ti,mbox-num-fifos = <16>; 897 interrupt-parent = <&main_navss_intr>; 898 status = "disabled"; 899 }; 900 901 mailbox1_cluster3: mailbox@31f93000 { 902 compatible = "ti,am654-mailbox"; 903 reg = <0x00 0x31f93000 0x00 0x200>; 904 #mbox-cells = <1>; 905 ti,mbox-num-users = <4>; 906 ti,mbox-num-fifos = <16>; 907 interrupt-parent = <&main_navss_intr>; 908 status = "disabled"; 909 }; 910 911 mailbox1_cluster4: mailbox@31f94000 { 912 compatible = "ti,am654-mailbox"; 913 reg = <0x00 0x31f94000 0x00 0x200>; 914 #mbox-cells = <1>; 915 ti,mbox-num-users = <4>; 916 ti,mbox-num-fifos = <16>; 917 interrupt-parent = <&main_navss_intr>; 918 status = "disabled"; 919 }; 920 921 mailbox1_cluster5: mailbox@31f95000 { 922 compatible = "ti,am654-mailbox"; 923 reg = <0x00 0x31f95000 0x00 0x200>; 924 #mbox-cells = <1>; 925 ti,mbox-num-users = <4>; 926 ti,mbox-num-fifos = <16>; 927 interrupt-parent = <&main_navss_intr>; 928 status = "disabled"; 929 }; 930 931 mailbox1_cluster6: mailbox@31f96000 { 932 compatible = "ti,am654-mailbox"; 933 reg = <0x00 0x31f96000 0x00 0x200>; 934 #mbox-cells = <1>; 935 ti,mbox-num-users = <4>; 936 ti,mbox-num-fifos = <16>; 937 interrupt-parent = <&main_navss_intr>; 938 status = "disabled"; 939 }; 940 941 mailbox1_cluster7: mailbox@31f97000 { 942 compatible = "ti,am654-mailbox"; 943 reg = <0x00 0x31f97000 0x00 0x200>; 944 #mbox-cells = <1>; 945 ti,mbox-num-users = <4>; 946 ti,mbox-num-fifos = <16>; 947 interrupt-parent = <&main_navss_intr>; 948 status = "disabled"; 949 }; 950 951 mailbox1_cluster8: mailbox@31f98000 { 952 compatible = "ti,am654-mailbox"; 953 reg = <0x00 0x31f98000 0x00 0x200>; 954 #mbox-cells = <1>; 955 ti,mbox-num-users = <4>; 956 ti,mbox-num-fifos = <16>; 957 interrupt-parent = <&main_navss_intr>; 958 status = "disabled"; 959 }; 960 961 mailbox1_cluster9: mailbox@31f99000 { 962 compatible = "ti,am654-mailbox"; 963 reg = <0x00 0x31f99000 0x00 0x200>; 964 #mbox-cells = <1>; 965 ti,mbox-num-users = <4>; 966 ti,mbox-num-fifos = <16>; 967 interrupt-parent = <&main_navss_intr>; 968 status = "disabled"; 969 }; 970 971 mailbox1_cluster10: mailbox@31f9a000 { 972 compatible = "ti,am654-mailbox"; 973 reg = <0x00 0x31f9a000 0x00 0x200>; 974 #mbox-cells = <1>; 975 ti,mbox-num-users = <4>; 976 ti,mbox-num-fifos = <16>; 977 interrupt-parent = <&main_navss_intr>; 978 status = "disabled"; 979 }; 980 981 mailbox1_cluster11: mailbox@31f9b000 { 982 compatible = "ti,am654-mailbox"; 983 reg = <0x00 0x31f9b000 0x00 0x200>; 984 #mbox-cells = <1>; 985 ti,mbox-num-users = <4>; 986 ti,mbox-num-fifos = <16>; 987 interrupt-parent = <&main_navss_intr>; 988 status = "disabled"; 989 }; 990 991 main_ringacc: ringacc@3c000000 { 992 compatible = "ti,am654-navss-ringacc"; 993 reg = <0x0 0x3c000000 0x0 0x400000>, 994 <0x0 0x38000000 0x0 0x400000>, 995 <0x0 0x31120000 0x0 0x100>, 996 <0x0 0x33000000 0x0 0x40000>; 997 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 998 ti,num-rings = <1024>; 999 ti,sci-rm-range-gp-rings = <0x1>; 1000 ti,sci = <&sms>; 1001 ti,sci-dev-id = <259>; 1002 msi-parent = <&main_udmass_inta>; 1003 }; 1004 1005 main_udmap: dma-controller@31150000 { 1006 compatible = "ti,j721e-navss-main-udmap"; 1007 reg = <0x0 0x31150000 0x0 0x100>, 1008 <0x0 0x34000000 0x0 0x80000>, 1009 <0x0 0x35000000 0x0 0x200000>; 1010 reg-names = "gcfg", "rchanrt", "tchanrt"; 1011 msi-parent = <&main_udmass_inta>; 1012 #dma-cells = <1>; 1013 1014 ti,sci = <&sms>; 1015 ti,sci-dev-id = <263>; 1016 ti,ringacc = <&main_ringacc>; 1017 1018 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1019 <0x0f>, /* TX_HCHAN */ 1020 <0x10>; /* TX_UHCHAN */ 1021 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1022 <0x0b>, /* RX_HCHAN */ 1023 <0x0c>; /* RX_UHCHAN */ 1024 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1025 }; 1026 1027 cpts@310d0000 { 1028 compatible = "ti,j721e-cpts"; 1029 reg = <0x0 0x310d0000 0x0 0x400>; 1030 reg-names = "cpts"; 1031 clocks = <&k3_clks 226 5>; 1032 clock-names = "cpts"; 1033 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ 1034 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ 1035 interrupts-extended = <&main_navss_intr 391>; 1036 interrupt-names = "cpts"; 1037 ti,cpts-periodic-outputs = <6>; 1038 ti,cpts-ext-ts-inputs = <8>; 1039 }; 1040 }; 1041 1042 usbss0: cdns-usb@4104000 { 1043 compatible = "ti,j721e-usb"; 1044 reg = <0x00 0x04104000 0x00 0x100>; 1045 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 1046 clock-names = "ref", "lpm"; 1047 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 1048 assigned-clock-parents = <&k3_clks 360 17>; 1049 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1050 #address-cells = <2>; 1051 #size-cells = <2>; 1052 ranges; 1053 dma-coherent; 1054 1055 status = "disabled"; /* Needs pinmux */ 1056 1057 usb0: usb@6000000 { 1058 compatible = "cdns,usb3"; 1059 reg = <0x00 0x06000000 0x00 0x10000>, 1060 <0x00 0x06010000 0x00 0x10000>, 1061 <0x00 0x06020000 0x00 0x10000>; 1062 reg-names = "otg", "xhci", "dev"; 1063 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1066 interrupt-names = "host", "peripheral", "otg"; 1067 maximum-speed = "super-speed"; 1068 dr_mode = "otg"; 1069 }; 1070 }; 1071 1072 serdes_wiz0: wiz@5060000 { 1073 compatible = "ti,j721s2-wiz-10g"; 1074 #address-cells = <1>; 1075 #size-cells = <1>; 1076 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1077 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1078 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1079 num-lanes = <4>; 1080 #reset-cells = <1>; 1081 #clock-cells = <1>; 1082 ranges = <0x5060000 0x0 0x5060000 0x10000>; 1083 1084 assigned-clocks = <&k3_clks 365 3>; 1085 assigned-clock-parents = <&k3_clks 365 7>; 1086 1087 serdes0: serdes@5060000 { 1088 compatible = "ti,j721e-serdes-10g"; 1089 reg = <0x05060000 0x00010000>; 1090 reg-names = "torrent_phy"; 1091 resets = <&serdes_wiz0 0>; 1092 reset-names = "torrent_reset"; 1093 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1094 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1095 clock-names = "refclk", "phy_en_refclk"; 1096 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1097 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1098 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1099 assigned-clock-parents = <&k3_clks 365 3>, 1100 <&k3_clks 365 3>, 1101 <&k3_clks 365 3>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 #clock-cells = <1>; 1105 1106 status = "disabled"; /* Needs lane config */ 1107 }; 1108 }; 1109 1110 pcie1_rc: pcie@2910000 { 1111 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1112 reg = <0x00 0x02910000 0x00 0x1000>, 1113 <0x00 0x02917000 0x00 0x400>, 1114 <0x00 0x0d800000 0x00 0x800000>, 1115 <0x00 0x18000000 0x00 0x1000>; 1116 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1117 interrupt-names = "link_state"; 1118 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1119 device_type = "pci"; 1120 ti,syscon-pcie-ctrl = <&scm_conf 0x074>; 1121 max-link-speed = <3>; 1122 num-lanes = <4>; 1123 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1124 clocks = <&k3_clks 276 41>; 1125 clock-names = "fck"; 1126 #address-cells = <3>; 1127 #size-cells = <2>; 1128 bus-range = <0x0 0xff>; 1129 vendor-id = <0x104c>; 1130 device-id = <0xb013>; 1131 msi-map = <0x0 &gic_its 0x0 0x10000>; 1132 dma-coherent; 1133 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1134 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1135 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1136 #interrupt-cells = <1>; 1137 interrupt-map-mask = <0 0 0 7>; 1138 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1139 <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1140 <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1141 <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1142 1143 status = "disabled"; /* Needs gpio and serdes info */ 1144 1145 pcie1_intc: interrupt-controller { 1146 interrupt-controller; 1147 #interrupt-cells = <1>; 1148 interrupt-parent = <&gic500>; 1149 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1150 }; 1151 }; 1152 1153 main_mcan0: can@2701000 { 1154 compatible = "bosch,m_can"; 1155 reg = <0x00 0x02701000 0x00 0x200>, 1156 <0x00 0x02708000 0x00 0x8000>; 1157 reg-names = "m_can", "message_ram"; 1158 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1159 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1160 clock-names = "hclk", "cclk"; 1161 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1163 interrupt-names = "int0", "int1"; 1164 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1165 status = "disabled"; 1166 }; 1167 1168 main_mcan1: can@2711000 { 1169 compatible = "bosch,m_can"; 1170 reg = <0x00 0x02711000 0x00 0x200>, 1171 <0x00 0x02718000 0x00 0x8000>; 1172 reg-names = "m_can", "message_ram"; 1173 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1174 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1175 clock-names = "hclk", "cclk"; 1176 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1178 interrupt-names = "int0", "int1"; 1179 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1180 status = "disabled"; 1181 }; 1182 1183 main_mcan2: can@2721000 { 1184 compatible = "bosch,m_can"; 1185 reg = <0x00 0x02721000 0x00 0x200>, 1186 <0x00 0x02728000 0x00 0x8000>; 1187 reg-names = "m_can", "message_ram"; 1188 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1189 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1190 clock-names = "hclk", "cclk"; 1191 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1193 interrupt-names = "int0", "int1"; 1194 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1195 status = "disabled"; 1196 }; 1197 1198 main_mcan3: can@2731000 { 1199 compatible = "bosch,m_can"; 1200 reg = <0x00 0x02731000 0x00 0x200>, 1201 <0x00 0x02738000 0x00 0x8000>; 1202 reg-names = "m_can", "message_ram"; 1203 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1204 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1205 clock-names = "hclk", "cclk"; 1206 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1208 interrupt-names = "int0", "int1"; 1209 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1210 status = "disabled"; 1211 }; 1212 1213 main_mcan4: can@2741000 { 1214 compatible = "bosch,m_can"; 1215 reg = <0x00 0x02741000 0x00 0x200>, 1216 <0x00 0x02748000 0x00 0x8000>; 1217 reg-names = "m_can", "message_ram"; 1218 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1219 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1220 clock-names = "hclk", "cclk"; 1221 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1223 interrupt-names = "int0", "int1"; 1224 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1225 status = "disabled"; 1226 }; 1227 1228 main_mcan5: can@2751000 { 1229 compatible = "bosch,m_can"; 1230 reg = <0x00 0x02751000 0x00 0x200>, 1231 <0x00 0x02758000 0x00 0x8000>; 1232 reg-names = "m_can", "message_ram"; 1233 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1234 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1235 clock-names = "hclk", "cclk"; 1236 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1238 interrupt-names = "int0", "int1"; 1239 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1240 status = "disabled"; 1241 }; 1242 1243 main_mcan6: can@2761000 { 1244 compatible = "bosch,m_can"; 1245 reg = <0x00 0x02761000 0x00 0x200>, 1246 <0x00 0x02768000 0x00 0x8000>; 1247 reg-names = "m_can", "message_ram"; 1248 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1249 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1250 clock-names = "hclk", "cclk"; 1251 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1253 interrupt-names = "int0", "int1"; 1254 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1255 status = "disabled"; 1256 }; 1257 1258 main_mcan7: can@2771000 { 1259 compatible = "bosch,m_can"; 1260 reg = <0x00 0x02771000 0x00 0x200>, 1261 <0x00 0x02778000 0x00 0x8000>; 1262 reg-names = "m_can", "message_ram"; 1263 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1264 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1265 clock-names = "hclk", "cclk"; 1266 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1268 interrupt-names = "int0", "int1"; 1269 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1270 status = "disabled"; 1271 }; 1272 1273 main_mcan8: can@2781000 { 1274 compatible = "bosch,m_can"; 1275 reg = <0x00 0x02781000 0x00 0x200>, 1276 <0x00 0x02788000 0x00 0x8000>; 1277 reg-names = "m_can", "message_ram"; 1278 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1279 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1280 clock-names = "hclk", "cclk"; 1281 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1283 interrupt-names = "int0", "int1"; 1284 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1285 status = "disabled"; 1286 }; 1287 1288 main_mcan9: can@2791000 { 1289 compatible = "bosch,m_can"; 1290 reg = <0x00 0x02791000 0x00 0x200>, 1291 <0x00 0x02798000 0x00 0x8000>; 1292 reg-names = "m_can", "message_ram"; 1293 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1294 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1295 clock-names = "hclk", "cclk"; 1296 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1298 interrupt-names = "int0", "int1"; 1299 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1300 status = "disabled"; 1301 }; 1302 1303 main_mcan10: can@27a1000 { 1304 compatible = "bosch,m_can"; 1305 reg = <0x00 0x027a1000 0x00 0x200>, 1306 <0x00 0x027a8000 0x00 0x8000>; 1307 reg-names = "m_can", "message_ram"; 1308 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1309 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1310 clock-names = "hclk", "cclk"; 1311 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1313 interrupt-names = "int0", "int1"; 1314 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1315 status = "disabled"; 1316 }; 1317 1318 main_mcan11: can@27b1000 { 1319 compatible = "bosch,m_can"; 1320 reg = <0x00 0x027b1000 0x00 0x200>, 1321 <0x00 0x027b8000 0x00 0x8000>; 1322 reg-names = "m_can", "message_ram"; 1323 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1324 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1325 clock-names = "hclk", "cclk"; 1326 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1328 interrupt-names = "int0", "int1"; 1329 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1330 status = "disabled"; 1331 }; 1332 1333 main_mcan12: can@27c1000 { 1334 compatible = "bosch,m_can"; 1335 reg = <0x00 0x027c1000 0x00 0x200>, 1336 <0x00 0x027c8000 0x00 0x8000>; 1337 reg-names = "m_can", "message_ram"; 1338 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1339 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1340 clock-names = "hclk", "cclk"; 1341 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1343 interrupt-names = "int0", "int1"; 1344 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1345 status = "disabled"; 1346 }; 1347 1348 main_mcan13: can@27d1000 { 1349 compatible = "bosch,m_can"; 1350 reg = <0x00 0x027d1000 0x00 0x200>, 1351 <0x00 0x027d8000 0x00 0x8000>; 1352 reg-names = "m_can", "message_ram"; 1353 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1354 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1355 clock-names = "hclk", "cclk"; 1356 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1358 interrupt-names = "int0", "int1"; 1359 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1360 status = "disabled"; 1361 }; 1362 1363 main_mcan14: can@2681000 { 1364 compatible = "bosch,m_can"; 1365 reg = <0x00 0x02681000 0x00 0x200>, 1366 <0x00 0x02688000 0x00 0x8000>; 1367 reg-names = "m_can", "message_ram"; 1368 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1369 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1370 clock-names = "hclk", "cclk"; 1371 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1373 interrupt-names = "int0", "int1"; 1374 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1375 status = "disabled"; 1376 }; 1377 1378 main_mcan15: can@2691000 { 1379 compatible = "bosch,m_can"; 1380 reg = <0x00 0x02691000 0x00 0x200>, 1381 <0x00 0x02698000 0x00 0x8000>; 1382 reg-names = "m_can", "message_ram"; 1383 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1384 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1385 clock-names = "hclk", "cclk"; 1386 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "int0", "int1"; 1389 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1390 status = "disabled"; 1391 }; 1392 1393 main_mcan16: can@26a1000 { 1394 compatible = "bosch,m_can"; 1395 reg = <0x00 0x026a1000 0x00 0x200>, 1396 <0x00 0x026a8000 0x00 0x8000>; 1397 reg-names = "m_can", "message_ram"; 1398 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1399 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1400 clock-names = "hclk", "cclk"; 1401 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupt-names = "int0", "int1"; 1404 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1405 status = "disabled"; 1406 }; 1407 1408 main_mcan17: can@26b1000 { 1409 compatible = "bosch,m_can"; 1410 reg = <0x00 0x026b1000 0x00 0x200>, 1411 <0x00 0x026b8000 0x00 0x8000>; 1412 reg-names = "m_can", "message_ram"; 1413 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1414 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1415 clock-names = "hclk", "cclk"; 1416 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1418 interrupt-names = "int0", "int1"; 1419 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1420 status = "disabled"; 1421 }; 1422 1423 main_spi0: spi@2100000 { 1424 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1425 reg = <0x00 0x02100000 0x00 0x400>; 1426 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 1430 clocks = <&k3_clks 339 1>; 1431 status = "disabled"; 1432 }; 1433 1434 main_spi1: spi@2110000 { 1435 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1436 reg = <0x00 0x02110000 0x00 0x400>; 1437 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 1441 clocks = <&k3_clks 340 1>; 1442 status = "disabled"; 1443 }; 1444 1445 main_spi2: spi@2120000 { 1446 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1447 reg = <0x00 0x02120000 0x00 0x400>; 1448 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 1452 clocks = <&k3_clks 341 1>; 1453 status = "disabled"; 1454 }; 1455 1456 main_spi3: spi@2130000 { 1457 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1458 reg = <0x00 0x02130000 0x00 0x400>; 1459 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 1463 clocks = <&k3_clks 342 1>; 1464 status = "disabled"; 1465 }; 1466 1467 main_spi4: spi@2140000 { 1468 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1469 reg = <0x00 0x02140000 0x00 0x400>; 1470 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 1474 clocks = <&k3_clks 343 1>; 1475 status = "disabled"; 1476 }; 1477 1478 main_spi5: spi@2150000 { 1479 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1480 reg = <0x00 0x02150000 0x00 0x400>; 1481 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 1485 clocks = <&k3_clks 344 1>; 1486 status = "disabled"; 1487 }; 1488 1489 main_spi6: spi@2160000 { 1490 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1491 reg = <0x00 0x02160000 0x00 0x400>; 1492 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 1496 clocks = <&k3_clks 345 1>; 1497 status = "disabled"; 1498 }; 1499 1500 main_spi7: spi@2170000 { 1501 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1502 reg = <0x00 0x02170000 0x00 0x400>; 1503 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1507 clocks = <&k3_clks 346 1>; 1508 status = "disabled"; 1509 }; 1510}; 1511