1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_main {
9	msmc_ram: sram@70000000 {
10		compatible = "mmio-sram";
11		reg = <0x0 0x70000000 0x0 0x400000>;
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges = <0x0 0x0 0x70000000 0x400000>;
15
16		atf-sram@0 {
17			reg = <0x0 0x20000>;
18		};
19
20		tifs-sram@1f0000 {
21			reg = <0x1f0000 0x10000>;
22		};
23
24		l3cache-sram@200000 {
25			reg = <0x200000 0x200000>;
26		};
27	};
28
29	gic500: interrupt-controller@1800000 {
30		compatible = "arm,gic-v3";
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34		#interrupt-cells = <3>;
35		interrupt-controller;
36		reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
37		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
38		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
39		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
40		      <0x00 0x6f020000 0x00 0x2000>;   /* GICV */
41
42		/* vcpumntirq: virtual CPU interface maintenance interrupt */
43		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
44
45		gic_its: msi-controller@1820000 {
46			compatible = "arm,gic-v3-its";
47			reg = <0x00 0x01820000 0x00 0x10000>;
48			socionext,synquacer-pre-its = <0x1000000 0x400000>;
49			msi-controller;
50			#msi-cells = <1>;
51		};
52	};
53
54	main_gpio_intr: interrupt-controller@a00000 {
55		compatible = "ti,sci-intr";
56		reg = <0x00 0x00a00000 0x00 0x800>;
57		ti,intr-trigger-type = <1>;
58		interrupt-controller;
59		interrupt-parent = <&gic500>;
60		#interrupt-cells = <1>;
61		ti,sci = <&sms>;
62		ti,sci-dev-id = <148>;
63		ti,interrupt-ranges = <8 392 56>;
64	};
65
66	main_pmx0: pinctrl@11c000 {
67		compatible = "pinctrl-single";
68		/* Proxy 0 addressing */
69		reg = <0x0 0x11c000 0x0 0x120>;
70		#pinctrl-cells = <1>;
71		pinctrl-single,register-width = <32>;
72		pinctrl-single,function-mask = <0xffffffff>;
73	};
74
75	main_crypto: crypto@4e00000 {
76		compatible = "ti,j721e-sa2ul";
77		reg = <0x00 0x04e00000 0x00 0x1200>;
78		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
79		#address-cells = <2>;
80		#size-cells = <2>;
81		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
82
83		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
84		       <&main_udmap 0x4a41>;
85		dma-names = "tx", "rx1", "rx2";
86
87		rng: rng@4e10000 {
88			compatible = "inside-secure,safexcel-eip76";
89			reg = <0x00 0x04e10000 0x00 0x7d>;
90			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
91		};
92	};
93
94	main_uart0: serial@2800000 {
95		compatible = "ti,j721e-uart", "ti,am654-uart";
96		reg = <0x00 0x02800000 0x00 0x200>;
97		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
98		current-speed = <115200>;
99		clocks = <&k3_clks 146 3>;
100		clock-names = "fclk";
101		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
102		status = "disabled";
103	};
104
105	main_uart1: serial@2810000 {
106		compatible = "ti,j721e-uart", "ti,am654-uart";
107		reg = <0x00 0x02810000 0x00 0x200>;
108		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
109		current-speed = <115200>;
110		clocks = <&k3_clks 350 3>;
111		clock-names = "fclk";
112		power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
113		status = "disabled";
114	};
115
116	main_uart2: serial@2820000 {
117		compatible = "ti,j721e-uart", "ti,am654-uart";
118		reg = <0x00 0x02820000 0x00 0x200>;
119		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
120		current-speed = <115200>;
121		clocks = <&k3_clks 351 3>;
122		clock-names = "fclk";
123		power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
124		status = "disabled";
125	};
126
127	main_uart3: serial@2830000 {
128		compatible = "ti,j721e-uart", "ti,am654-uart";
129		reg = <0x00 0x02830000 0x00 0x200>;
130		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
131		current-speed = <115200>;
132		clocks = <&k3_clks 352 3>;
133		clock-names = "fclk";
134		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
135		status = "disabled";
136	};
137
138	main_uart4: serial@2840000 {
139		compatible = "ti,j721e-uart", "ti,am654-uart";
140		reg = <0x00 0x02840000 0x00 0x200>;
141		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
142		current-speed = <115200>;
143		clocks = <&k3_clks 353 3>;
144		clock-names = "fclk";
145		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
146		status = "disabled";
147	};
148
149	main_uart5: serial@2850000 {
150		compatible = "ti,j721e-uart", "ti,am654-uart";
151		reg = <0x00 0x02850000 0x00 0x200>;
152		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
153		current-speed = <115200>;
154		clocks = <&k3_clks 354 3>;
155		clock-names = "fclk";
156		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
157		status = "disabled";
158	};
159
160	main_uart6: serial@2860000 {
161		compatible = "ti,j721e-uart", "ti,am654-uart";
162		reg = <0x00 0x02860000 0x00 0x200>;
163		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
164		current-speed = <115200>;
165		clocks = <&k3_clks 355 3>;
166		clock-names = "fclk";
167		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
168		status = "disabled";
169	};
170
171	main_uart7: serial@2870000 {
172		compatible = "ti,j721e-uart", "ti,am654-uart";
173		reg = <0x00 0x02870000 0x00 0x200>;
174		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
175		current-speed = <115200>;
176		clocks = <&k3_clks 356 3>;
177		clock-names = "fclk";
178		power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
179		status = "disabled";
180	};
181
182	main_uart8: serial@2880000 {
183		compatible = "ti,j721e-uart", "ti,am654-uart";
184		reg = <0x00 0x02880000 0x00 0x200>;
185		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
186		current-speed = <115200>;
187		clocks = <&k3_clks 357 3>;
188		clock-names = "fclk";
189		power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
190		status = "disabled";
191	};
192
193	main_uart9: serial@2890000 {
194		compatible = "ti,j721e-uart", "ti,am654-uart";
195		reg = <0x00 0x02890000 0x00 0x200>;
196		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
197		current-speed = <115200>;
198		clocks = <&k3_clks 358 3>;
199		clock-names = "fclk";
200		power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
201		status = "disabled";
202	};
203
204	main_gpio0: gpio@600000 {
205		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
206		reg = <0x00 0x00600000 0x00 0x100>;
207		gpio-controller;
208		#gpio-cells = <2>;
209		interrupt-parent = <&main_gpio_intr>;
210		interrupts = <145>, <146>, <147>, <148>, <149>;
211		interrupt-controller;
212		#interrupt-cells = <2>;
213		ti,ngpio = <66>;
214		ti,davinci-gpio-unbanked = <0>;
215		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
216		clocks = <&k3_clks 111 0>;
217		clock-names = "gpio";
218	};
219
220	main_gpio2: gpio@610000 {
221		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
222		reg = <0x00 0x00610000 0x00 0x100>;
223		gpio-controller;
224		#gpio-cells = <2>;
225		interrupt-parent = <&main_gpio_intr>;
226		interrupts = <154>, <155>, <156>, <157>, <158>;
227		interrupt-controller;
228		#interrupt-cells = <2>;
229		ti,ngpio = <66>;
230		ti,davinci-gpio-unbanked = <0>;
231		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
232		clocks = <&k3_clks 112 0>;
233		clock-names = "gpio";
234	};
235
236	main_gpio4: gpio@620000 {
237		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
238		reg = <0x00 0x00620000 0x00 0x100>;
239		gpio-controller;
240		#gpio-cells = <2>;
241		interrupt-parent = <&main_gpio_intr>;
242		interrupts = <163>, <164>, <165>, <166>, <167>;
243		interrupt-controller;
244		#interrupt-cells = <2>;
245		ti,ngpio = <66>;
246		ti,davinci-gpio-unbanked = <0>;
247		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
248		clocks = <&k3_clks 113 0>;
249		clock-names = "gpio";
250	};
251
252	main_gpio6: gpio@630000 {
253		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
254		reg = <0x00 0x00630000 0x00 0x100>;
255		gpio-controller;
256		#gpio-cells = <2>;
257		interrupt-parent = <&main_gpio_intr>;
258		interrupts = <172>, <173>, <174>, <175>, <176>;
259		interrupt-controller;
260		#interrupt-cells = <2>;
261		ti,ngpio = <66>;
262		ti,davinci-gpio-unbanked = <0>;
263		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
264		clocks = <&k3_clks 114 0>;
265		clock-names = "gpio";
266	};
267
268	main_i2c0: i2c@2000000 {
269		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
270		reg = <0x00 0x02000000 0x00 0x100>;
271		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
272		#address-cells = <1>;
273		#size-cells = <0>;
274		clocks = <&k3_clks 214 1>;
275		clock-names = "fck";
276		power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
277	};
278
279	main_i2c1: i2c@2010000 {
280		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
281		reg = <0x00 0x02010000 0x00 0x100>;
282		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
283		#address-cells = <1>;
284		#size-cells = <0>;
285		clocks = <&k3_clks 215 1>;
286		clock-names = "fck";
287		power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
288		status = "disabled";
289	};
290
291	main_i2c2: i2c@2020000 {
292		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
293		reg = <0x00 0x02020000 0x00 0x100>;
294		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
295		#address-cells = <1>;
296		#size-cells = <0>;
297		clocks = <&k3_clks 216 1>;
298		clock-names = "fck";
299		power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
300		status = "disabled";
301	};
302
303	main_i2c3: i2c@2030000 {
304		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
305		reg = <0x00 0x02030000 0x00 0x100>;
306		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
307		#address-cells = <1>;
308		#size-cells = <0>;
309		clocks = <&k3_clks 217 1>;
310		clock-names = "fck";
311		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
312		status = "disabled";
313	};
314
315	main_i2c4: i2c@2040000 {
316		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
317		reg = <0x00 0x02040000 0x00 0x100>;
318		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
319		#address-cells = <1>;
320		#size-cells = <0>;
321		clocks = <&k3_clks 218 1>;
322		clock-names = "fck";
323		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
324		status = "disabled";
325	};
326
327	main_i2c5: i2c@2050000 {
328		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
329		reg = <0x00 0x02050000 0x00 0x100>;
330		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
331		#address-cells = <1>;
332		#size-cells = <0>;
333		clocks = <&k3_clks 219 1>;
334		clock-names = "fck";
335		power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
336		status = "disabled";
337	};
338
339	main_i2c6: i2c@2060000 {
340		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
341		reg = <0x00 0x02060000 0x00 0x100>;
342		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
343		#address-cells = <1>;
344		#size-cells = <0>;
345		clocks = <&k3_clks 220 1>;
346		clock-names = "fck";
347		power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
348		status = "disabled";
349	};
350
351	main_sdhci0: mmc@4f80000 {
352		compatible = "ti,j721e-sdhci-8bit";
353		reg = <0x00 0x04f80000 0x00 0x1000>,
354		      <0x00 0x04f88000 0x00 0x400>;
355		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
356		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
357		clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
358		clock-names = "clk_ahb", "clk_xin";
359		assigned-clocks = <&k3_clks 98 1>;
360		assigned-clock-parents = <&k3_clks 98 2>;
361		bus-width = <8>;
362		ti,otap-del-sel-legacy = <0x0>;
363		ti,otap-del-sel-mmc-hs = <0x0>;
364		ti,otap-del-sel-ddr52 = <0x6>;
365		ti,otap-del-sel-hs200 = <0x8>;
366		ti,otap-del-sel-hs400 = <0x5>;
367		ti,itap-del-sel-legacy = <0x10>;
368		ti,itap-del-sel-mmc-hs = <0xa>;
369		ti,strobe-sel = <0x77>;
370		ti,clkbuf-sel = <0x7>;
371		ti,trm-icp = <0x8>;
372		mmc-ddr-1_8v;
373		mmc-hs200-1_8v;
374		mmc-hs400-1_8v;
375		dma-coherent;
376	};
377
378	main_sdhci1: mmc@4fb0000 {
379		compatible = "ti,j721e-sdhci-4bit";
380		reg = <0x00 0x04fb0000 0x00 0x1000>,
381		      <0x00 0x04fb8000 0x00 0x400>;
382		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
383		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
384		clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
385		clock-names = "clk_ahb", "clk_xin";
386		assigned-clocks = <&k3_clks 99 1>;
387		assigned-clock-parents = <&k3_clks 99 2>;
388		bus-width = <4>;
389		ti,otap-del-sel-legacy = <0x0>;
390		ti,otap-del-sel-sd-hs = <0x0>;
391		ti,otap-del-sel-sdr12 = <0xf>;
392		ti,otap-del-sel-sdr25 = <0xf>;
393		ti,otap-del-sel-sdr50 = <0xc>;
394		ti,otap-del-sel-sdr104 = <0x5>;
395		ti,otap-del-sel-ddr50 = <0xc>;
396		ti,itap-del-sel-legacy = <0x0>;
397		ti,itap-del-sel-sd-hs = <0x0>;
398		ti,itap-del-sel-sdr12 = <0x0>;
399		ti,itap-del-sel-sdr25 = <0x0>;
400		ti,clkbuf-sel = <0x7>;
401		ti,trm-icp = <0x8>;
402		dma-coherent;
403		/* Masking support for SDR104 capability */
404		sdhci-caps-mask = <0x00000003 0x00000000>;
405	};
406
407	main_navss: bus@30000000 {
408		compatible = "simple-mfd";
409		#address-cells = <2>;
410		#size-cells = <2>;
411		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
412		ti,sci-dev-id = <224>;
413		dma-coherent;
414		dma-ranges;
415
416		main_navss_intr: interrupt-controller@310e0000 {
417			compatible = "ti,sci-intr";
418			reg = <0x00 0x310e0000 0x00 0x4000>;
419			ti,intr-trigger-type = <4>;
420			interrupt-controller;
421			interrupt-parent = <&gic500>;
422			#interrupt-cells = <1>;
423			ti,sci = <&sms>;
424			ti,sci-dev-id = <227>;
425			ti,interrupt-ranges = <0 64 64>,
426					      <64 448 64>,
427					      <128 672 64>;
428		};
429
430		main_udmass_inta: msi-controller@33d00000 {
431			compatible = "ti,sci-inta";
432			reg = <0x00 0x33d00000 0x00 0x100000>;
433			interrupt-controller;
434			#interrupt-cells = <0>;
435			interrupt-parent = <&main_navss_intr>;
436			msi-controller;
437			ti,sci = <&sms>;
438			ti,sci-dev-id = <265>;
439			ti,interrupt-ranges = <0 0 256>;
440		};
441
442		secure_proxy_main: mailbox@32c00000 {
443			compatible = "ti,am654-secure-proxy";
444			#mbox-cells = <1>;
445			reg-names = "target_data", "rt", "scfg";
446			reg = <0x00 0x32c00000 0x00 0x100000>,
447			      <0x00 0x32400000 0x00 0x100000>,
448			      <0x00 0x32800000 0x00 0x100000>;
449			interrupt-names = "rx_011";
450			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
451		};
452
453		hwspinlock: spinlock@30e00000 {
454			compatible = "ti,am654-hwspinlock";
455			reg = <0x00 0x30e00000 0x00 0x1000>;
456			#hwlock-cells = <1>;
457		};
458
459		mailbox0_cluster0: mailbox@31f80000 {
460			compatible = "ti,am654-mailbox";
461			reg = <0x00 0x31f80000 0x00 0x200>;
462			#mbox-cells = <1>;
463			ti,mbox-num-users = <4>;
464			ti,mbox-num-fifos = <16>;
465			interrupt-parent = <&main_navss_intr>;
466			status = "disabled";
467		};
468
469		mailbox0_cluster1: mailbox@31f81000 {
470			compatible = "ti,am654-mailbox";
471			reg = <0x00 0x31f81000 0x00 0x200>;
472			#mbox-cells = <1>;
473			ti,mbox-num-users = <4>;
474			ti,mbox-num-fifos = <16>;
475			interrupt-parent = <&main_navss_intr>;
476			status = "disabled";
477		};
478
479		mailbox0_cluster2: mailbox@31f82000 {
480			compatible = "ti,am654-mailbox";
481			reg = <0x00 0x31f82000 0x00 0x200>;
482			#mbox-cells = <1>;
483			ti,mbox-num-users = <4>;
484			ti,mbox-num-fifos = <16>;
485			interrupt-parent = <&main_navss_intr>;
486			status = "disabled";
487		};
488
489		mailbox0_cluster3: mailbox@31f83000 {
490			compatible = "ti,am654-mailbox";
491			reg = <0x00 0x31f83000 0x00 0x200>;
492			#mbox-cells = <1>;
493			ti,mbox-num-users = <4>;
494			ti,mbox-num-fifos = <16>;
495			interrupt-parent = <&main_navss_intr>;
496			status = "disabled";
497		};
498
499		mailbox0_cluster4: mailbox@31f84000 {
500			compatible = "ti,am654-mailbox";
501			reg = <0x00 0x31f84000 0x00 0x200>;
502			#mbox-cells = <1>;
503			ti,mbox-num-users = <4>;
504			ti,mbox-num-fifos = <16>;
505			interrupt-parent = <&main_navss_intr>;
506			status = "disabled";
507		};
508
509		mailbox0_cluster5: mailbox@31f85000 {
510			compatible = "ti,am654-mailbox";
511			reg = <0x00 0x31f85000 0x00 0x200>;
512			#mbox-cells = <1>;
513			ti,mbox-num-users = <4>;
514			ti,mbox-num-fifos = <16>;
515			interrupt-parent = <&main_navss_intr>;
516			status = "disabled";
517		};
518
519		mailbox0_cluster6: mailbox@31f86000 {
520			compatible = "ti,am654-mailbox";
521			reg = <0x00 0x31f86000 0x00 0x200>;
522			#mbox-cells = <1>;
523			ti,mbox-num-users = <4>;
524			ti,mbox-num-fifos = <16>;
525			interrupt-parent = <&main_navss_intr>;
526			status = "disabled";
527		};
528
529		mailbox0_cluster7: mailbox@31f87000 {
530			compatible = "ti,am654-mailbox";
531			reg = <0x00 0x31f87000 0x00 0x200>;
532			#mbox-cells = <1>;
533			ti,mbox-num-users = <4>;
534			ti,mbox-num-fifos = <16>;
535			interrupt-parent = <&main_navss_intr>;
536			status = "disabled";
537		};
538
539		mailbox0_cluster8: mailbox@31f88000 {
540			compatible = "ti,am654-mailbox";
541			reg = <0x00 0x31f88000 0x00 0x200>;
542			#mbox-cells = <1>;
543			ti,mbox-num-users = <4>;
544			ti,mbox-num-fifos = <16>;
545			interrupt-parent = <&main_navss_intr>;
546			status = "disabled";
547		};
548
549		mailbox0_cluster9: mailbox@31f89000 {
550			compatible = "ti,am654-mailbox";
551			reg = <0x00 0x31f89000 0x00 0x200>;
552			#mbox-cells = <1>;
553			ti,mbox-num-users = <4>;
554			ti,mbox-num-fifos = <16>;
555			interrupt-parent = <&main_navss_intr>;
556			status = "disabled";
557		};
558
559		mailbox0_cluster10: mailbox@31f8a000 {
560			compatible = "ti,am654-mailbox";
561			reg = <0x00 0x31f8a000 0x00 0x200>;
562			#mbox-cells = <1>;
563			ti,mbox-num-users = <4>;
564			ti,mbox-num-fifos = <16>;
565			interrupt-parent = <&main_navss_intr>;
566			status = "disabled";
567		};
568
569		mailbox0_cluster11: mailbox@31f8b000 {
570			compatible = "ti,am654-mailbox";
571			reg = <0x00 0x31f8b000 0x00 0x200>;
572			#mbox-cells = <1>;
573			ti,mbox-num-users = <4>;
574			ti,mbox-num-fifos = <16>;
575			interrupt-parent = <&main_navss_intr>;
576			status = "disabled";
577		};
578
579		mailbox1_cluster0: mailbox@31f90000 {
580			compatible = "ti,am654-mailbox";
581			reg = <0x00 0x31f90000 0x00 0x200>;
582			#mbox-cells = <1>;
583			ti,mbox-num-users = <4>;
584			ti,mbox-num-fifos = <16>;
585			interrupt-parent = <&main_navss_intr>;
586			status = "disabled";
587		};
588
589		mailbox1_cluster1: mailbox@31f91000 {
590			compatible = "ti,am654-mailbox";
591			reg = <0x00 0x31f91000 0x00 0x200>;
592			#mbox-cells = <1>;
593			ti,mbox-num-users = <4>;
594			ti,mbox-num-fifos = <16>;
595			interrupt-parent = <&main_navss_intr>;
596			status = "disabled";
597		};
598
599		mailbox1_cluster2: mailbox@31f92000 {
600			compatible = "ti,am654-mailbox";
601			reg = <0x00 0x31f92000 0x00 0x200>;
602			#mbox-cells = <1>;
603			ti,mbox-num-users = <4>;
604			ti,mbox-num-fifos = <16>;
605			interrupt-parent = <&main_navss_intr>;
606			status = "disabled";
607		};
608
609		mailbox1_cluster3: mailbox@31f93000 {
610			compatible = "ti,am654-mailbox";
611			reg = <0x00 0x31f93000 0x00 0x200>;
612			#mbox-cells = <1>;
613			ti,mbox-num-users = <4>;
614			ti,mbox-num-fifos = <16>;
615			interrupt-parent = <&main_navss_intr>;
616			status = "disabled";
617		};
618
619		mailbox1_cluster4: mailbox@31f94000 {
620			compatible = "ti,am654-mailbox";
621			reg = <0x00 0x31f94000 0x00 0x200>;
622			#mbox-cells = <1>;
623			ti,mbox-num-users = <4>;
624			ti,mbox-num-fifos = <16>;
625			interrupt-parent = <&main_navss_intr>;
626			status = "disabled";
627		};
628
629		mailbox1_cluster5: mailbox@31f95000 {
630			compatible = "ti,am654-mailbox";
631			reg = <0x00 0x31f95000 0x00 0x200>;
632			#mbox-cells = <1>;
633			ti,mbox-num-users = <4>;
634			ti,mbox-num-fifos = <16>;
635			interrupt-parent = <&main_navss_intr>;
636			status = "disabled";
637		};
638
639		mailbox1_cluster6: mailbox@31f96000 {
640			compatible = "ti,am654-mailbox";
641			reg = <0x00 0x31f96000 0x00 0x200>;
642			#mbox-cells = <1>;
643			ti,mbox-num-users = <4>;
644			ti,mbox-num-fifos = <16>;
645			interrupt-parent = <&main_navss_intr>;
646			status = "disabled";
647		};
648
649		mailbox1_cluster7: mailbox@31f97000 {
650			compatible = "ti,am654-mailbox";
651			reg = <0x00 0x31f97000 0x00 0x200>;
652			#mbox-cells = <1>;
653			ti,mbox-num-users = <4>;
654			ti,mbox-num-fifos = <16>;
655			interrupt-parent = <&main_navss_intr>;
656			status = "disabled";
657		};
658
659		mailbox1_cluster8: mailbox@31f98000 {
660			compatible = "ti,am654-mailbox";
661			reg = <0x00 0x31f98000 0x00 0x200>;
662			#mbox-cells = <1>;
663			ti,mbox-num-users = <4>;
664			ti,mbox-num-fifos = <16>;
665			interrupt-parent = <&main_navss_intr>;
666			status = "disabled";
667		};
668
669		mailbox1_cluster9: mailbox@31f99000 {
670			compatible = "ti,am654-mailbox";
671			reg = <0x00 0x31f99000 0x00 0x200>;
672			#mbox-cells = <1>;
673			ti,mbox-num-users = <4>;
674			ti,mbox-num-fifos = <16>;
675			interrupt-parent = <&main_navss_intr>;
676			status = "disabled";
677		};
678
679		mailbox1_cluster10: mailbox@31f9a000 {
680			compatible = "ti,am654-mailbox";
681			reg = <0x00 0x31f9a000 0x00 0x200>;
682			#mbox-cells = <1>;
683			ti,mbox-num-users = <4>;
684			ti,mbox-num-fifos = <16>;
685			interrupt-parent = <&main_navss_intr>;
686			status = "disabled";
687		};
688
689		mailbox1_cluster11: mailbox@31f9b000 {
690			compatible = "ti,am654-mailbox";
691			reg = <0x00 0x31f9b000 0x00 0x200>;
692			#mbox-cells = <1>;
693			ti,mbox-num-users = <4>;
694			ti,mbox-num-fifos = <16>;
695			interrupt-parent = <&main_navss_intr>;
696			status = "disabled";
697		};
698
699		main_ringacc: ringacc@3c000000 {
700			compatible = "ti,am654-navss-ringacc";
701			reg = <0x0 0x3c000000 0x0 0x400000>,
702			      <0x0 0x38000000 0x0 0x400000>,
703			      <0x0 0x31120000 0x0 0x100>,
704			      <0x0 0x33000000 0x0 0x40000>;
705			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
706			ti,num-rings = <1024>;
707			ti,sci-rm-range-gp-rings = <0x1>;
708			ti,sci = <&sms>;
709			ti,sci-dev-id = <259>;
710			msi-parent = <&main_udmass_inta>;
711		};
712
713		main_udmap: dma-controller@31150000 {
714			compatible = "ti,j721e-navss-main-udmap";
715			reg = <0x0 0x31150000 0x0 0x100>,
716			      <0x0 0x34000000 0x0 0x80000>,
717			      <0x0 0x35000000 0x0 0x200000>;
718			reg-names = "gcfg", "rchanrt", "tchanrt";
719			msi-parent = <&main_udmass_inta>;
720			#dma-cells = <1>;
721
722			ti,sci = <&sms>;
723			ti,sci-dev-id = <263>;
724			ti,ringacc = <&main_ringacc>;
725
726			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
727						<0x0f>, /* TX_HCHAN */
728						<0x10>; /* TX_UHCHAN */
729			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
730						<0x0b>, /* RX_HCHAN */
731						<0x0c>; /* RX_UHCHAN */
732			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
733		};
734
735		cpts@310d0000 {
736			compatible = "ti,j721e-cpts";
737			reg = <0x0 0x310d0000 0x0 0x400>;
738			reg-names = "cpts";
739			clocks = <&k3_clks 226 5>;
740			clock-names = "cpts";
741			interrupts-extended = <&main_navss_intr 391>;
742			interrupt-names = "cpts";
743			ti,cpts-periodic-outputs = <6>;
744			ti,cpts-ext-ts-inputs = <8>;
745		};
746	};
747
748	main_mcan0: can@2701000 {
749		compatible = "bosch,m_can";
750		reg = <0x00 0x02701000 0x00 0x200>,
751		      <0x00 0x02708000 0x00 0x8000>;
752		reg-names = "m_can", "message_ram";
753		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
754		clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
755		clock-names = "hclk", "cclk";
756		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
757			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
758		interrupt-names = "int0", "int1";
759		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
760		status = "disabled";
761	};
762
763	main_mcan1: can@2711000 {
764		compatible = "bosch,m_can";
765		reg = <0x00 0x02711000 0x00 0x200>,
766		      <0x00 0x02718000 0x00 0x8000>;
767		reg-names = "m_can", "message_ram";
768		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
769		clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
770		clock-names = "hclk", "cclk";
771		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
772			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
773		interrupt-names = "int0", "int1";
774		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
775		status = "disabled";
776	};
777
778	main_mcan2: can@2721000 {
779		compatible = "bosch,m_can";
780		reg = <0x00 0x02721000 0x00 0x200>,
781		      <0x00 0x02728000 0x00 0x8000>;
782		reg-names = "m_can", "message_ram";
783		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
784		clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
785		clock-names = "hclk", "cclk";
786		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
787			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
788		interrupt-names = "int0", "int1";
789		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
790		status = "disabled";
791	};
792
793	main_mcan3: can@2731000 {
794		compatible = "bosch,m_can";
795		reg = <0x00 0x02731000 0x00 0x200>,
796		      <0x00 0x02738000 0x00 0x8000>;
797		reg-names = "m_can", "message_ram";
798		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
799		clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
800		clock-names = "hclk", "cclk";
801		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
802			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
803		interrupt-names = "int0", "int1";
804		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
805		status = "disabled";
806	};
807
808	main_mcan4: can@2741000 {
809		compatible = "bosch,m_can";
810		reg = <0x00 0x02741000 0x00 0x200>,
811		      <0x00 0x02748000 0x00 0x8000>;
812		reg-names = "m_can", "message_ram";
813		power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
814		clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
815		clock-names = "hclk", "cclk";
816		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
817			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
818		interrupt-names = "int0", "int1";
819		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
820		status = "disabled";
821	};
822
823	main_mcan5: can@2751000 {
824		compatible = "bosch,m_can";
825		reg = <0x00 0x02751000 0x00 0x200>,
826		      <0x00 0x02758000 0x00 0x8000>;
827		reg-names = "m_can", "message_ram";
828		power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
829		clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
830		clock-names = "hclk", "cclk";
831		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
832			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
833		interrupt-names = "int0", "int1";
834		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
835		status = "disabled";
836	};
837
838	main_mcan6: can@2761000 {
839		compatible = "bosch,m_can";
840		reg = <0x00 0x02761000 0x00 0x200>,
841		      <0x00 0x02768000 0x00 0x8000>;
842		reg-names = "m_can", "message_ram";
843		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
844		clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
845		clock-names = "hclk", "cclk";
846		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
847			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
848		interrupt-names = "int0", "int1";
849		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
850		status = "disabled";
851	};
852
853	main_mcan7: can@2771000 {
854		compatible = "bosch,m_can";
855		reg = <0x00 0x02771000 0x00 0x200>,
856		      <0x00 0x02778000 0x00 0x8000>;
857		reg-names = "m_can", "message_ram";
858		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
859		clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
860		clock-names = "hclk", "cclk";
861		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
862			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
863		interrupt-names = "int0", "int1";
864		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
865		status = "disabled";
866	};
867
868	main_mcan8: can@2781000 {
869		compatible = "bosch,m_can";
870		reg = <0x00 0x02781000 0x00 0x200>,
871		      <0x00 0x02788000 0x00 0x8000>;
872		reg-names = "m_can", "message_ram";
873		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
874		clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
875		clock-names = "hclk", "cclk";
876		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
877			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
878		interrupt-names = "int0", "int1";
879		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
880		status = "disabled";
881	};
882
883	main_mcan9: can@2791000 {
884		compatible = "bosch,m_can";
885		reg = <0x00 0x02791000 0x00 0x200>,
886		      <0x00 0x02798000 0x00 0x8000>;
887		reg-names = "m_can", "message_ram";
888		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
889		clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
890		clock-names = "hclk", "cclk";
891		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
892			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
893		interrupt-names = "int0", "int1";
894		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
895		status = "disabled";
896	};
897
898	main_mcan10: can@27a1000 {
899		compatible = "bosch,m_can";
900		reg = <0x00 0x027a1000 0x00 0x200>,
901		      <0x00 0x027a8000 0x00 0x8000>;
902		reg-names = "m_can", "message_ram";
903		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
904		clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
905		clock-names = "hclk", "cclk";
906		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
907			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
908		interrupt-names = "int0", "int1";
909		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
910		status = "disabled";
911	};
912
913	main_mcan11: can@27b1000 {
914		compatible = "bosch,m_can";
915		reg = <0x00 0x027b1000 0x00 0x200>,
916		      <0x00 0x027b8000 0x00 0x8000>;
917		reg-names = "m_can", "message_ram";
918		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
919		clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
920		clock-names = "hclk", "cclk";
921		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
922			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
923		interrupt-names = "int0", "int1";
924		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
925		status = "disabled";
926	};
927
928	main_mcan12: can@27c1000 {
929		compatible = "bosch,m_can";
930		reg = <0x00 0x027c1000 0x00 0x200>,
931		      <0x00 0x027c8000 0x00 0x8000>;
932		reg-names = "m_can", "message_ram";
933		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
934		clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
935		clock-names = "hclk", "cclk";
936		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
937			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
938		interrupt-names = "int0", "int1";
939		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
940		status = "disabled";
941	};
942
943	main_mcan13: can@27d1000 {
944		compatible = "bosch,m_can";
945		reg = <0x00 0x027d1000 0x00 0x200>,
946		      <0x00 0x027d8000 0x00 0x8000>;
947		reg-names = "m_can", "message_ram";
948		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
949		clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
950		clock-names = "hclk", "cclk";
951		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
952			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
953		interrupt-names = "int0", "int1";
954		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
955		status = "disabled";
956	};
957
958	main_mcan14: can@2681000 {
959		compatible = "bosch,m_can";
960		reg = <0x00 0x02681000 0x00 0x200>,
961		      <0x00 0x02688000 0x00 0x8000>;
962		reg-names = "m_can", "message_ram";
963		power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
964		clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
965		clock-names = "hclk", "cclk";
966		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
967			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
968		interrupt-names = "int0", "int1";
969		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
970		status = "disabled";
971	};
972
973	main_mcan15: can@2691000 {
974		compatible = "bosch,m_can";
975		reg = <0x00 0x02691000 0x00 0x200>,
976		      <0x00 0x02698000 0x00 0x8000>;
977		reg-names = "m_can", "message_ram";
978		power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
979		clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
980		clock-names = "hclk", "cclk";
981		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
982			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
983		interrupt-names = "int0", "int1";
984		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
985		status = "disabled";
986	};
987
988	main_mcan16: can@26a1000 {
989		compatible = "bosch,m_can";
990		reg = <0x00 0x026a1000 0x00 0x200>,
991		      <0x00 0x026a8000 0x00 0x8000>;
992		reg-names = "m_can", "message_ram";
993		power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
994		clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
995		clock-names = "hclk", "cclk";
996		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
997			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
998		interrupt-names = "int0", "int1";
999		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1000		status = "disabled";
1001	};
1002
1003	main_mcan17: can@26b1000 {
1004		compatible = "bosch,m_can";
1005		reg = <0x00 0x026b1000 0x00 0x200>,
1006		      <0x00 0x026b8000 0x00 0x8000>;
1007		reg-names = "m_can", "message_ram";
1008		power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1009		clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1010		clock-names = "hclk", "cclk";
1011		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1012			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1013		interrupt-names = "int0", "int1";
1014		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1015		status = "disabled";
1016	};
1017};
1018