1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 msmc_ram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x0 0x70000000 0x0 0x400000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x0 0x70000000 0x400000>; 26 27 atf-sram@0 { 28 reg = <0x0 0x20000>; 29 }; 30 31 tifs-sram@1f0000 { 32 reg = <0x1f0000 0x10000>; 33 }; 34 35 l3cache-sram@200000 { 36 reg = <0x200000 0x200000>; 37 }; 38 }; 39 40 scm_conf: syscon@104000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x00 0x00104000 0x00 0x18000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x00 0x00 0x00104000 0x18000>; 46 47 usb_serdes_mux: mux-controller@0 { 48 compatible = "mmio-mux"; 49 reg = <0x0 0x4>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 52 }; 53 54 phy_gmii_sel_cpsw: phy@34 { 55 compatible = "ti,am654-phy-gmii-sel"; 56 reg = <0x34 0x4>; 57 #phy-cells = <1>; 58 }; 59 60 serdes_ln_ctrl: mux-controller@80 { 61 compatible = "mmio-mux"; 62 reg = <0x80 0x10>; 63 #mux-control-cells = <1>; 64 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ 65 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ 66 }; 67 68 ehrpwm_tbclk: clock-controller@140 { 69 compatible = "ti,am654-ehrpwm-tbclk"; 70 reg = <0x140 0x18>; 71 #clock-cells = <1>; 72 }; 73 }; 74 75 main_ehrpwm0: pwm@3000000 { 76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 77 #pwm-cells = <3>; 78 reg = <0x00 0x3000000 0x00 0x100>; 79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; 81 clock-names = "tbclk", "fck"; 82 status = "disabled"; 83 }; 84 85 main_ehrpwm1: pwm@3010000 { 86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 87 #pwm-cells = <3>; 88 reg = <0x00 0x3010000 0x00 0x100>; 89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; 91 clock-names = "tbclk", "fck"; 92 status = "disabled"; 93 }; 94 95 main_ehrpwm2: pwm@3020000 { 96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 97 #pwm-cells = <3>; 98 reg = <0x00 0x3020000 0x00 0x100>; 99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; 101 clock-names = "tbclk", "fck"; 102 status = "disabled"; 103 }; 104 105 main_ehrpwm3: pwm@3030000 { 106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 107 #pwm-cells = <3>; 108 reg = <0x00 0x3030000 0x00 0x100>; 109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; 111 clock-names = "tbclk", "fck"; 112 status = "disabled"; 113 }; 114 115 main_ehrpwm4: pwm@3040000 { 116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 117 #pwm-cells = <3>; 118 reg = <0x00 0x3040000 0x00 0x100>; 119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; 121 clock-names = "tbclk", "fck"; 122 status = "disabled"; 123 }; 124 125 main_ehrpwm5: pwm@3050000 { 126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 127 #pwm-cells = <3>; 128 reg = <0x00 0x3050000 0x00 0x100>; 129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; 131 clock-names = "tbclk", "fck"; 132 status = "disabled"; 133 }; 134 135 gic500: interrupt-controller@1800000 { 136 compatible = "arm,gic-v3"; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 ranges; 140 #interrupt-cells = <3>; 141 interrupt-controller; 142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 143 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 147 148 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 150 151 gic_its: msi-controller@1820000 { 152 compatible = "arm,gic-v3-its"; 153 reg = <0x00 0x01820000 0x00 0x10000>; 154 socionext,synquacer-pre-its = <0x1000000 0x400000>; 155 msi-controller; 156 #msi-cells = <1>; 157 }; 158 }; 159 160 main_gpio_intr: interrupt-controller@a00000 { 161 compatible = "ti,sci-intr"; 162 reg = <0x00 0x00a00000 0x00 0x800>; 163 ti,intr-trigger-type = <1>; 164 interrupt-controller; 165 interrupt-parent = <&gic500>; 166 #interrupt-cells = <1>; 167 ti,sci = <&sms>; 168 ti,sci-dev-id = <148>; 169 ti,interrupt-ranges = <8 392 56>; 170 }; 171 172 main_pmx0: pinctrl@11c000 { 173 compatible = "pinctrl-single"; 174 /* Proxy 0 addressing */ 175 reg = <0x0 0x11c000 0x0 0x120>; 176 #pinctrl-cells = <1>; 177 pinctrl-single,register-width = <32>; 178 pinctrl-single,function-mask = <0xffffffff>; 179 }; 180 181 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 182 main_timerio_input: pinctrl@104200 { 183 compatible = "pinctrl-single"; 184 reg = <0x00 0x104200 0x00 0x50>; 185 #pinctrl-cells = <1>; 186 pinctrl-single,register-width = <32>; 187 pinctrl-single,function-mask = <0x00000007>; 188 }; 189 190 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 191 main_timerio_output: pinctrl@104280 { 192 compatible = "pinctrl-single"; 193 reg = <0x00 0x104280 0x00 0x20>; 194 #pinctrl-cells = <1>; 195 pinctrl-single,register-width = <32>; 196 pinctrl-single,function-mask = <0x0000001f>; 197 }; 198 199 main_crypto: crypto@4e00000 { 200 compatible = "ti,j721e-sa2ul"; 201 reg = <0x00 0x04e00000 0x00 0x1200>; 202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 206 207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 208 <&main_udmap 0x4a41>; 209 dma-names = "tx", "rx1", "rx2"; 210 211 rng: rng@4e10000 { 212 compatible = "inside-secure,safexcel-eip76"; 213 reg = <0x00 0x04e10000 0x00 0x7d>; 214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 215 }; 216 }; 217 218 main_timer0: timer@2400000 { 219 compatible = "ti,am654-timer"; 220 reg = <0x00 0x2400000 0x00 0x400>; 221 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&k3_clks 63 1>; 223 clock-names = "fck"; 224 assigned-clocks = <&k3_clks 63 1>; 225 assigned-clock-parents = <&k3_clks 63 2>; 226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 227 ti,timer-pwm; 228 }; 229 230 main_timer1: timer@2410000 { 231 compatible = "ti,am654-timer"; 232 reg = <0x00 0x2410000 0x00 0x400>; 233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&k3_clks 64 1>; 235 clock-names = "fck"; 236 assigned-clocks = <&k3_clks 64 1>; 237 assigned-clock-parents = <&k3_clks 64 2>; 238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 239 ti,timer-pwm; 240 }; 241 242 main_timer2: timer@2420000 { 243 compatible = "ti,am654-timer"; 244 reg = <0x00 0x2420000 0x00 0x400>; 245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&k3_clks 65 1>; 247 clock-names = "fck"; 248 assigned-clocks = <&k3_clks 65 1>; 249 assigned-clock-parents = <&k3_clks 65 2>; 250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 251 ti,timer-pwm; 252 }; 253 254 main_timer3: timer@2430000 { 255 compatible = "ti,am654-timer"; 256 reg = <0x00 0x2430000 0x00 0x400>; 257 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&k3_clks 66 1>; 259 clock-names = "fck"; 260 assigned-clocks = <&k3_clks 66 1>; 261 assigned-clock-parents = <&k3_clks 66 2>; 262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 263 ti,timer-pwm; 264 }; 265 266 main_timer4: timer@2440000 { 267 compatible = "ti,am654-timer"; 268 reg = <0x00 0x2440000 0x00 0x400>; 269 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&k3_clks 67 1>; 271 clock-names = "fck"; 272 assigned-clocks = <&k3_clks 67 1>; 273 assigned-clock-parents = <&k3_clks 67 2>; 274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 275 ti,timer-pwm; 276 }; 277 278 main_timer5: timer@2450000 { 279 compatible = "ti,am654-timer"; 280 reg = <0x00 0x2450000 0x00 0x400>; 281 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&k3_clks 68 1>; 283 clock-names = "fck"; 284 assigned-clocks = <&k3_clks 68 1>; 285 assigned-clock-parents = <&k3_clks 68 2>; 286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 287 ti,timer-pwm; 288 }; 289 290 main_timer6: timer@2460000 { 291 compatible = "ti,am654-timer"; 292 reg = <0x00 0x2460000 0x00 0x400>; 293 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&k3_clks 69 1>; 295 clock-names = "fck"; 296 assigned-clocks = <&k3_clks 69 1>; 297 assigned-clock-parents = <&k3_clks 69 2>; 298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 299 ti,timer-pwm; 300 }; 301 302 main_timer7: timer@2470000 { 303 compatible = "ti,am654-timer"; 304 reg = <0x00 0x2470000 0x00 0x400>; 305 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&k3_clks 70 1>; 307 clock-names = "fck"; 308 assigned-clocks = <&k3_clks 70 1>; 309 assigned-clock-parents = <&k3_clks 70 2>; 310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 311 ti,timer-pwm; 312 }; 313 314 main_timer8: timer@2480000 { 315 compatible = "ti,am654-timer"; 316 reg = <0x00 0x2480000 0x00 0x400>; 317 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&k3_clks 71 1>; 319 clock-names = "fck"; 320 assigned-clocks = <&k3_clks 71 1>; 321 assigned-clock-parents = <&k3_clks 71 2>; 322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 323 ti,timer-pwm; 324 }; 325 326 main_timer9: timer@2490000 { 327 compatible = "ti,am654-timer"; 328 reg = <0x00 0x2490000 0x00 0x400>; 329 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&k3_clks 72 1>; 331 clock-names = "fck"; 332 assigned-clocks = <&k3_clks 72 1>; 333 assigned-clock-parents = <&k3_clks 72 2>; 334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 335 ti,timer-pwm; 336 }; 337 338 main_timer10: timer@24a0000 { 339 compatible = "ti,am654-timer"; 340 reg = <0x00 0x24a0000 0x00 0x400>; 341 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&k3_clks 73 1>; 343 clock-names = "fck"; 344 assigned-clocks = <&k3_clks 73 1>; 345 assigned-clock-parents = <&k3_clks 73 2>; 346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 347 ti,timer-pwm; 348 }; 349 350 main_timer11: timer@24b0000 { 351 compatible = "ti,am654-timer"; 352 reg = <0x00 0x24b0000 0x00 0x400>; 353 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&k3_clks 74 1>; 355 clock-names = "fck"; 356 assigned-clocks = <&k3_clks 74 1>; 357 assigned-clock-parents = <&k3_clks 74 2>; 358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 359 ti,timer-pwm; 360 }; 361 362 main_timer12: timer@24c0000 { 363 compatible = "ti,am654-timer"; 364 reg = <0x00 0x24c0000 0x00 0x400>; 365 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&k3_clks 75 1>; 367 clock-names = "fck"; 368 assigned-clocks = <&k3_clks 75 1>; 369 assigned-clock-parents = <&k3_clks 75 2>; 370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 371 ti,timer-pwm; 372 }; 373 374 main_timer13: timer@24d0000 { 375 compatible = "ti,am654-timer"; 376 reg = <0x00 0x24d0000 0x00 0x400>; 377 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&k3_clks 76 1>; 379 clock-names = "fck"; 380 assigned-clocks = <&k3_clks 76 1>; 381 assigned-clock-parents = <&k3_clks 76 2>; 382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 383 ti,timer-pwm; 384 }; 385 386 main_timer14: timer@24e0000 { 387 compatible = "ti,am654-timer"; 388 reg = <0x00 0x24e0000 0x00 0x400>; 389 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&k3_clks 77 1>; 391 clock-names = "fck"; 392 assigned-clocks = <&k3_clks 77 1>; 393 assigned-clock-parents = <&k3_clks 77 2>; 394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 395 ti,timer-pwm; 396 }; 397 398 main_timer15: timer@24f0000 { 399 compatible = "ti,am654-timer"; 400 reg = <0x00 0x24f0000 0x00 0x400>; 401 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&k3_clks 78 1>; 403 clock-names = "fck"; 404 assigned-clocks = <&k3_clks 78 1>; 405 assigned-clock-parents = <&k3_clks 78 2>; 406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 407 ti,timer-pwm; 408 }; 409 410 main_timer16: timer@2500000 { 411 compatible = "ti,am654-timer"; 412 reg = <0x00 0x2500000 0x00 0x400>; 413 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&k3_clks 79 1>; 415 clock-names = "fck"; 416 assigned-clocks = <&k3_clks 79 1>; 417 assigned-clock-parents = <&k3_clks 79 2>; 418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 419 ti,timer-pwm; 420 }; 421 422 main_timer17: timer@2510000 { 423 compatible = "ti,am654-timer"; 424 reg = <0x00 0x2510000 0x00 0x400>; 425 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&k3_clks 80 1>; 427 clock-names = "fck"; 428 assigned-clocks = <&k3_clks 80 1>; 429 assigned-clock-parents = <&k3_clks 80 2>; 430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 431 ti,timer-pwm; 432 }; 433 434 main_timer18: timer@2520000 { 435 compatible = "ti,am654-timer"; 436 reg = <0x00 0x2520000 0x00 0x400>; 437 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&k3_clks 81 1>; 439 clock-names = "fck"; 440 assigned-clocks = <&k3_clks 81 1>; 441 assigned-clock-parents = <&k3_clks 81 2>; 442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 443 ti,timer-pwm; 444 }; 445 446 main_timer19: timer@2530000 { 447 compatible = "ti,am654-timer"; 448 reg = <0x00 0x2530000 0x00 0x400>; 449 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&k3_clks 82 1>; 451 clock-names = "fck"; 452 assigned-clocks = <&k3_clks 82 1>; 453 assigned-clock-parents = <&k3_clks 82 2>; 454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 455 ti,timer-pwm; 456 }; 457 458 main_uart0: serial@2800000 { 459 compatible = "ti,j721e-uart", "ti,am654-uart"; 460 reg = <0x00 0x02800000 0x00 0x200>; 461 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 462 current-speed = <115200>; 463 clocks = <&k3_clks 146 3>; 464 clock-names = "fclk"; 465 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 466 status = "disabled"; 467 }; 468 469 main_uart1: serial@2810000 { 470 compatible = "ti,j721e-uart", "ti,am654-uart"; 471 reg = <0x00 0x02810000 0x00 0x200>; 472 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 473 current-speed = <115200>; 474 clocks = <&k3_clks 350 3>; 475 clock-names = "fclk"; 476 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 477 status = "disabled"; 478 }; 479 480 main_uart2: serial@2820000 { 481 compatible = "ti,j721e-uart", "ti,am654-uart"; 482 reg = <0x00 0x02820000 0x00 0x200>; 483 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 484 current-speed = <115200>; 485 clocks = <&k3_clks 351 3>; 486 clock-names = "fclk"; 487 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 488 status = "disabled"; 489 }; 490 491 main_uart3: serial@2830000 { 492 compatible = "ti,j721e-uart", "ti,am654-uart"; 493 reg = <0x00 0x02830000 0x00 0x200>; 494 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 495 current-speed = <115200>; 496 clocks = <&k3_clks 352 3>; 497 clock-names = "fclk"; 498 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 499 status = "disabled"; 500 }; 501 502 main_uart4: serial@2840000 { 503 compatible = "ti,j721e-uart", "ti,am654-uart"; 504 reg = <0x00 0x02840000 0x00 0x200>; 505 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 506 current-speed = <115200>; 507 clocks = <&k3_clks 353 3>; 508 clock-names = "fclk"; 509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 510 status = "disabled"; 511 }; 512 513 main_uart5: serial@2850000 { 514 compatible = "ti,j721e-uart", "ti,am654-uart"; 515 reg = <0x00 0x02850000 0x00 0x200>; 516 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 517 current-speed = <115200>; 518 clocks = <&k3_clks 354 3>; 519 clock-names = "fclk"; 520 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 521 status = "disabled"; 522 }; 523 524 main_uart6: serial@2860000 { 525 compatible = "ti,j721e-uart", "ti,am654-uart"; 526 reg = <0x00 0x02860000 0x00 0x200>; 527 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 528 current-speed = <115200>; 529 clocks = <&k3_clks 355 3>; 530 clock-names = "fclk"; 531 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 532 status = "disabled"; 533 }; 534 535 main_uart7: serial@2870000 { 536 compatible = "ti,j721e-uart", "ti,am654-uart"; 537 reg = <0x00 0x02870000 0x00 0x200>; 538 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 539 current-speed = <115200>; 540 clocks = <&k3_clks 356 3>; 541 clock-names = "fclk"; 542 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 543 status = "disabled"; 544 }; 545 546 main_uart8: serial@2880000 { 547 compatible = "ti,j721e-uart", "ti,am654-uart"; 548 reg = <0x00 0x02880000 0x00 0x200>; 549 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 550 current-speed = <115200>; 551 clocks = <&k3_clks 357 3>; 552 clock-names = "fclk"; 553 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 554 status = "disabled"; 555 }; 556 557 main_uart9: serial@2890000 { 558 compatible = "ti,j721e-uart", "ti,am654-uart"; 559 reg = <0x00 0x02890000 0x00 0x200>; 560 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 561 current-speed = <115200>; 562 clocks = <&k3_clks 358 3>; 563 clock-names = "fclk"; 564 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 565 status = "disabled"; 566 }; 567 568 main_gpio0: gpio@600000 { 569 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 570 reg = <0x00 0x00600000 0x00 0x100>; 571 gpio-controller; 572 #gpio-cells = <2>; 573 interrupt-parent = <&main_gpio_intr>; 574 interrupts = <145>, <146>, <147>, <148>, <149>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 ti,ngpio = <66>; 578 ti,davinci-gpio-unbanked = <0>; 579 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 580 clocks = <&k3_clks 111 0>; 581 clock-names = "gpio"; 582 }; 583 584 main_gpio2: gpio@610000 { 585 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 586 reg = <0x00 0x00610000 0x00 0x100>; 587 gpio-controller; 588 #gpio-cells = <2>; 589 interrupt-parent = <&main_gpio_intr>; 590 interrupts = <154>, <155>, <156>, <157>, <158>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 ti,ngpio = <66>; 594 ti,davinci-gpio-unbanked = <0>; 595 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 596 clocks = <&k3_clks 112 0>; 597 clock-names = "gpio"; 598 }; 599 600 main_gpio4: gpio@620000 { 601 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 602 reg = <0x00 0x00620000 0x00 0x100>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 interrupt-parent = <&main_gpio_intr>; 606 interrupts = <163>, <164>, <165>, <166>, <167>; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 ti,ngpio = <66>; 610 ti,davinci-gpio-unbanked = <0>; 611 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 612 clocks = <&k3_clks 113 0>; 613 clock-names = "gpio"; 614 }; 615 616 main_gpio6: gpio@630000 { 617 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 618 reg = <0x00 0x00630000 0x00 0x100>; 619 gpio-controller; 620 #gpio-cells = <2>; 621 interrupt-parent = <&main_gpio_intr>; 622 interrupts = <172>, <173>, <174>, <175>, <176>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 ti,ngpio = <66>; 626 ti,davinci-gpio-unbanked = <0>; 627 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 628 clocks = <&k3_clks 114 0>; 629 clock-names = "gpio"; 630 }; 631 632 main_i2c0: i2c@2000000 { 633 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 634 reg = <0x00 0x02000000 0x00 0x100>; 635 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&k3_clks 214 1>; 639 clock-names = "fck"; 640 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 641 }; 642 643 main_i2c1: i2c@2010000 { 644 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 645 reg = <0x00 0x02010000 0x00 0x100>; 646 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 clocks = <&k3_clks 215 1>; 650 clock-names = "fck"; 651 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 652 status = "disabled"; 653 }; 654 655 main_i2c2: i2c@2020000 { 656 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 657 reg = <0x00 0x02020000 0x00 0x100>; 658 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 clocks = <&k3_clks 216 1>; 662 clock-names = "fck"; 663 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 664 status = "disabled"; 665 }; 666 667 main_i2c3: i2c@2030000 { 668 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 669 reg = <0x00 0x02030000 0x00 0x100>; 670 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&k3_clks 217 1>; 674 clock-names = "fck"; 675 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 676 status = "disabled"; 677 }; 678 679 main_i2c4: i2c@2040000 { 680 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 681 reg = <0x00 0x02040000 0x00 0x100>; 682 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 clocks = <&k3_clks 218 1>; 686 clock-names = "fck"; 687 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 688 status = "disabled"; 689 }; 690 691 main_i2c5: i2c@2050000 { 692 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 693 reg = <0x00 0x02050000 0x00 0x100>; 694 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 clocks = <&k3_clks 219 1>; 698 clock-names = "fck"; 699 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 700 status = "disabled"; 701 }; 702 703 main_i2c6: i2c@2060000 { 704 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 705 reg = <0x00 0x02060000 0x00 0x100>; 706 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&k3_clks 220 1>; 710 clock-names = "fck"; 711 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 712 status = "disabled"; 713 }; 714 715 main_sdhci0: mmc@4f80000 { 716 compatible = "ti,j721e-sdhci-8bit"; 717 reg = <0x00 0x04f80000 0x00 0x1000>, 718 <0x00 0x04f88000 0x00 0x400>; 719 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 720 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 721 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 722 clock-names = "clk_ahb", "clk_xin"; 723 assigned-clocks = <&k3_clks 98 1>; 724 assigned-clock-parents = <&k3_clks 98 2>; 725 bus-width = <8>; 726 ti,otap-del-sel-legacy = <0x0>; 727 ti,otap-del-sel-mmc-hs = <0x0>; 728 ti,otap-del-sel-ddr52 = <0x6>; 729 ti,otap-del-sel-hs200 = <0x8>; 730 ti,otap-del-sel-hs400 = <0x5>; 731 ti,itap-del-sel-legacy = <0x10>; 732 ti,itap-del-sel-mmc-hs = <0xa>; 733 ti,strobe-sel = <0x77>; 734 ti,clkbuf-sel = <0x7>; 735 ti,trm-icp = <0x8>; 736 mmc-ddr-1_8v; 737 mmc-hs200-1_8v; 738 mmc-hs400-1_8v; 739 dma-coherent; 740 }; 741 742 main_sdhci1: mmc@4fb0000 { 743 compatible = "ti,j721e-sdhci-4bit"; 744 reg = <0x00 0x04fb0000 0x00 0x1000>, 745 <0x00 0x04fb8000 0x00 0x400>; 746 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 747 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 748 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 749 clock-names = "clk_ahb", "clk_xin"; 750 assigned-clocks = <&k3_clks 99 1>; 751 assigned-clock-parents = <&k3_clks 99 2>; 752 bus-width = <4>; 753 ti,otap-del-sel-legacy = <0x0>; 754 ti,otap-del-sel-sd-hs = <0x0>; 755 ti,otap-del-sel-sdr12 = <0xf>; 756 ti,otap-del-sel-sdr25 = <0xf>; 757 ti,otap-del-sel-sdr50 = <0xc>; 758 ti,otap-del-sel-sdr104 = <0x5>; 759 ti,otap-del-sel-ddr50 = <0xc>; 760 ti,itap-del-sel-legacy = <0x0>; 761 ti,itap-del-sel-sd-hs = <0x0>; 762 ti,itap-del-sel-sdr12 = <0x0>; 763 ti,itap-del-sel-sdr25 = <0x0>; 764 ti,clkbuf-sel = <0x7>; 765 ti,trm-icp = <0x8>; 766 dma-coherent; 767 /* Masking support for SDR104 capability */ 768 sdhci-caps-mask = <0x00000003 0x00000000>; 769 }; 770 771 main_navss: bus@30000000 { 772 compatible = "simple-mfd"; 773 #address-cells = <2>; 774 #size-cells = <2>; 775 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 776 ti,sci-dev-id = <224>; 777 dma-coherent; 778 dma-ranges; 779 780 main_navss_intr: interrupt-controller@310e0000 { 781 compatible = "ti,sci-intr"; 782 reg = <0x00 0x310e0000 0x00 0x4000>; 783 ti,intr-trigger-type = <4>; 784 interrupt-controller; 785 interrupt-parent = <&gic500>; 786 #interrupt-cells = <1>; 787 ti,sci = <&sms>; 788 ti,sci-dev-id = <227>; 789 ti,interrupt-ranges = <0 64 64>, 790 <64 448 64>, 791 <128 672 64>; 792 }; 793 794 main_udmass_inta: msi-controller@33d00000 { 795 compatible = "ti,sci-inta"; 796 reg = <0x00 0x33d00000 0x00 0x100000>; 797 interrupt-controller; 798 #interrupt-cells = <0>; 799 interrupt-parent = <&main_navss_intr>; 800 msi-controller; 801 ti,sci = <&sms>; 802 ti,sci-dev-id = <265>; 803 ti,interrupt-ranges = <0 0 256>; 804 }; 805 806 secure_proxy_main: mailbox@32c00000 { 807 compatible = "ti,am654-secure-proxy"; 808 #mbox-cells = <1>; 809 reg-names = "target_data", "rt", "scfg"; 810 reg = <0x00 0x32c00000 0x00 0x100000>, 811 <0x00 0x32400000 0x00 0x100000>, 812 <0x00 0x32800000 0x00 0x100000>; 813 interrupt-names = "rx_011"; 814 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 815 }; 816 817 hwspinlock: spinlock@30e00000 { 818 compatible = "ti,am654-hwspinlock"; 819 reg = <0x00 0x30e00000 0x00 0x1000>; 820 #hwlock-cells = <1>; 821 }; 822 823 mailbox0_cluster0: mailbox@31f80000 { 824 compatible = "ti,am654-mailbox"; 825 reg = <0x00 0x31f80000 0x00 0x200>; 826 #mbox-cells = <1>; 827 ti,mbox-num-users = <4>; 828 ti,mbox-num-fifos = <16>; 829 interrupt-parent = <&main_navss_intr>; 830 status = "disabled"; 831 }; 832 833 mailbox0_cluster1: mailbox@31f81000 { 834 compatible = "ti,am654-mailbox"; 835 reg = <0x00 0x31f81000 0x00 0x200>; 836 #mbox-cells = <1>; 837 ti,mbox-num-users = <4>; 838 ti,mbox-num-fifos = <16>; 839 interrupt-parent = <&main_navss_intr>; 840 status = "disabled"; 841 }; 842 843 mailbox0_cluster2: mailbox@31f82000 { 844 compatible = "ti,am654-mailbox"; 845 reg = <0x00 0x31f82000 0x00 0x200>; 846 #mbox-cells = <1>; 847 ti,mbox-num-users = <4>; 848 ti,mbox-num-fifos = <16>; 849 interrupt-parent = <&main_navss_intr>; 850 status = "disabled"; 851 }; 852 853 mailbox0_cluster3: mailbox@31f83000 { 854 compatible = "ti,am654-mailbox"; 855 reg = <0x00 0x31f83000 0x00 0x200>; 856 #mbox-cells = <1>; 857 ti,mbox-num-users = <4>; 858 ti,mbox-num-fifos = <16>; 859 interrupt-parent = <&main_navss_intr>; 860 status = "disabled"; 861 }; 862 863 mailbox0_cluster4: mailbox@31f84000 { 864 compatible = "ti,am654-mailbox"; 865 reg = <0x00 0x31f84000 0x00 0x200>; 866 #mbox-cells = <1>; 867 ti,mbox-num-users = <4>; 868 ti,mbox-num-fifos = <16>; 869 interrupt-parent = <&main_navss_intr>; 870 status = "disabled"; 871 }; 872 873 mailbox0_cluster5: mailbox@31f85000 { 874 compatible = "ti,am654-mailbox"; 875 reg = <0x00 0x31f85000 0x00 0x200>; 876 #mbox-cells = <1>; 877 ti,mbox-num-users = <4>; 878 ti,mbox-num-fifos = <16>; 879 interrupt-parent = <&main_navss_intr>; 880 status = "disabled"; 881 }; 882 883 mailbox0_cluster6: mailbox@31f86000 { 884 compatible = "ti,am654-mailbox"; 885 reg = <0x00 0x31f86000 0x00 0x200>; 886 #mbox-cells = <1>; 887 ti,mbox-num-users = <4>; 888 ti,mbox-num-fifos = <16>; 889 interrupt-parent = <&main_navss_intr>; 890 status = "disabled"; 891 }; 892 893 mailbox0_cluster7: mailbox@31f87000 { 894 compatible = "ti,am654-mailbox"; 895 reg = <0x00 0x31f87000 0x00 0x200>; 896 #mbox-cells = <1>; 897 ti,mbox-num-users = <4>; 898 ti,mbox-num-fifos = <16>; 899 interrupt-parent = <&main_navss_intr>; 900 status = "disabled"; 901 }; 902 903 mailbox0_cluster8: mailbox@31f88000 { 904 compatible = "ti,am654-mailbox"; 905 reg = <0x00 0x31f88000 0x00 0x200>; 906 #mbox-cells = <1>; 907 ti,mbox-num-users = <4>; 908 ti,mbox-num-fifos = <16>; 909 interrupt-parent = <&main_navss_intr>; 910 status = "disabled"; 911 }; 912 913 mailbox0_cluster9: mailbox@31f89000 { 914 compatible = "ti,am654-mailbox"; 915 reg = <0x00 0x31f89000 0x00 0x200>; 916 #mbox-cells = <1>; 917 ti,mbox-num-users = <4>; 918 ti,mbox-num-fifos = <16>; 919 interrupt-parent = <&main_navss_intr>; 920 status = "disabled"; 921 }; 922 923 mailbox0_cluster10: mailbox@31f8a000 { 924 compatible = "ti,am654-mailbox"; 925 reg = <0x00 0x31f8a000 0x00 0x200>; 926 #mbox-cells = <1>; 927 ti,mbox-num-users = <4>; 928 ti,mbox-num-fifos = <16>; 929 interrupt-parent = <&main_navss_intr>; 930 status = "disabled"; 931 }; 932 933 mailbox0_cluster11: mailbox@31f8b000 { 934 compatible = "ti,am654-mailbox"; 935 reg = <0x00 0x31f8b000 0x00 0x200>; 936 #mbox-cells = <1>; 937 ti,mbox-num-users = <4>; 938 ti,mbox-num-fifos = <16>; 939 interrupt-parent = <&main_navss_intr>; 940 status = "disabled"; 941 }; 942 943 mailbox1_cluster0: mailbox@31f90000 { 944 compatible = "ti,am654-mailbox"; 945 reg = <0x00 0x31f90000 0x00 0x200>; 946 #mbox-cells = <1>; 947 ti,mbox-num-users = <4>; 948 ti,mbox-num-fifos = <16>; 949 interrupt-parent = <&main_navss_intr>; 950 status = "disabled"; 951 }; 952 953 mailbox1_cluster1: mailbox@31f91000 { 954 compatible = "ti,am654-mailbox"; 955 reg = <0x00 0x31f91000 0x00 0x200>; 956 #mbox-cells = <1>; 957 ti,mbox-num-users = <4>; 958 ti,mbox-num-fifos = <16>; 959 interrupt-parent = <&main_navss_intr>; 960 status = "disabled"; 961 }; 962 963 mailbox1_cluster2: mailbox@31f92000 { 964 compatible = "ti,am654-mailbox"; 965 reg = <0x00 0x31f92000 0x00 0x200>; 966 #mbox-cells = <1>; 967 ti,mbox-num-users = <4>; 968 ti,mbox-num-fifos = <16>; 969 interrupt-parent = <&main_navss_intr>; 970 status = "disabled"; 971 }; 972 973 mailbox1_cluster3: mailbox@31f93000 { 974 compatible = "ti,am654-mailbox"; 975 reg = <0x00 0x31f93000 0x00 0x200>; 976 #mbox-cells = <1>; 977 ti,mbox-num-users = <4>; 978 ti,mbox-num-fifos = <16>; 979 interrupt-parent = <&main_navss_intr>; 980 status = "disabled"; 981 }; 982 983 mailbox1_cluster4: mailbox@31f94000 { 984 compatible = "ti,am654-mailbox"; 985 reg = <0x00 0x31f94000 0x00 0x200>; 986 #mbox-cells = <1>; 987 ti,mbox-num-users = <4>; 988 ti,mbox-num-fifos = <16>; 989 interrupt-parent = <&main_navss_intr>; 990 status = "disabled"; 991 }; 992 993 mailbox1_cluster5: mailbox@31f95000 { 994 compatible = "ti,am654-mailbox"; 995 reg = <0x00 0x31f95000 0x00 0x200>; 996 #mbox-cells = <1>; 997 ti,mbox-num-users = <4>; 998 ti,mbox-num-fifos = <16>; 999 interrupt-parent = <&main_navss_intr>; 1000 status = "disabled"; 1001 }; 1002 1003 mailbox1_cluster6: mailbox@31f96000 { 1004 compatible = "ti,am654-mailbox"; 1005 reg = <0x00 0x31f96000 0x00 0x200>; 1006 #mbox-cells = <1>; 1007 ti,mbox-num-users = <4>; 1008 ti,mbox-num-fifos = <16>; 1009 interrupt-parent = <&main_navss_intr>; 1010 status = "disabled"; 1011 }; 1012 1013 mailbox1_cluster7: mailbox@31f97000 { 1014 compatible = "ti,am654-mailbox"; 1015 reg = <0x00 0x31f97000 0x00 0x200>; 1016 #mbox-cells = <1>; 1017 ti,mbox-num-users = <4>; 1018 ti,mbox-num-fifos = <16>; 1019 interrupt-parent = <&main_navss_intr>; 1020 status = "disabled"; 1021 }; 1022 1023 mailbox1_cluster8: mailbox@31f98000 { 1024 compatible = "ti,am654-mailbox"; 1025 reg = <0x00 0x31f98000 0x00 0x200>; 1026 #mbox-cells = <1>; 1027 ti,mbox-num-users = <4>; 1028 ti,mbox-num-fifos = <16>; 1029 interrupt-parent = <&main_navss_intr>; 1030 status = "disabled"; 1031 }; 1032 1033 mailbox1_cluster9: mailbox@31f99000 { 1034 compatible = "ti,am654-mailbox"; 1035 reg = <0x00 0x31f99000 0x00 0x200>; 1036 #mbox-cells = <1>; 1037 ti,mbox-num-users = <4>; 1038 ti,mbox-num-fifos = <16>; 1039 interrupt-parent = <&main_navss_intr>; 1040 status = "disabled"; 1041 }; 1042 1043 mailbox1_cluster10: mailbox@31f9a000 { 1044 compatible = "ti,am654-mailbox"; 1045 reg = <0x00 0x31f9a000 0x00 0x200>; 1046 #mbox-cells = <1>; 1047 ti,mbox-num-users = <4>; 1048 ti,mbox-num-fifos = <16>; 1049 interrupt-parent = <&main_navss_intr>; 1050 status = "disabled"; 1051 }; 1052 1053 mailbox1_cluster11: mailbox@31f9b000 { 1054 compatible = "ti,am654-mailbox"; 1055 reg = <0x00 0x31f9b000 0x00 0x200>; 1056 #mbox-cells = <1>; 1057 ti,mbox-num-users = <4>; 1058 ti,mbox-num-fifos = <16>; 1059 interrupt-parent = <&main_navss_intr>; 1060 status = "disabled"; 1061 }; 1062 1063 main_ringacc: ringacc@3c000000 { 1064 compatible = "ti,am654-navss-ringacc"; 1065 reg = <0x0 0x3c000000 0x0 0x400000>, 1066 <0x0 0x38000000 0x0 0x400000>, 1067 <0x0 0x31120000 0x0 0x100>, 1068 <0x0 0x33000000 0x0 0x40000>; 1069 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 1070 ti,num-rings = <1024>; 1071 ti,sci-rm-range-gp-rings = <0x1>; 1072 ti,sci = <&sms>; 1073 ti,sci-dev-id = <259>; 1074 msi-parent = <&main_udmass_inta>; 1075 }; 1076 1077 main_udmap: dma-controller@31150000 { 1078 compatible = "ti,j721e-navss-main-udmap"; 1079 reg = <0x0 0x31150000 0x0 0x100>, 1080 <0x0 0x34000000 0x0 0x80000>, 1081 <0x0 0x35000000 0x0 0x200000>; 1082 reg-names = "gcfg", "rchanrt", "tchanrt"; 1083 msi-parent = <&main_udmass_inta>; 1084 #dma-cells = <1>; 1085 1086 ti,sci = <&sms>; 1087 ti,sci-dev-id = <263>; 1088 ti,ringacc = <&main_ringacc>; 1089 1090 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1091 <0x0f>, /* TX_HCHAN */ 1092 <0x10>; /* TX_UHCHAN */ 1093 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1094 <0x0b>, /* RX_HCHAN */ 1095 <0x0c>; /* RX_UHCHAN */ 1096 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1097 }; 1098 1099 cpts@310d0000 { 1100 compatible = "ti,j721e-cpts"; 1101 reg = <0x0 0x310d0000 0x0 0x400>; 1102 reg-names = "cpts"; 1103 clocks = <&k3_clks 226 5>; 1104 clock-names = "cpts"; 1105 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ 1106 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ 1107 interrupts-extended = <&main_navss_intr 391>; 1108 interrupt-names = "cpts"; 1109 ti,cpts-periodic-outputs = <6>; 1110 ti,cpts-ext-ts-inputs = <8>; 1111 }; 1112 }; 1113 1114 main_cpsw: ethernet@c200000 { 1115 compatible = "ti,j721e-cpsw-nuss"; 1116 reg = <0x00 0xc200000 0x00 0x200000>; 1117 reg-names = "cpsw_nuss"; 1118 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; 1119 #address-cells = <2>; 1120 #size-cells = <2>; 1121 dma-coherent; 1122 clocks = <&k3_clks 28 28>; 1123 clock-names = "fck"; 1124 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 1125 1126 dmas = <&main_udmap 0xc640>, 1127 <&main_udmap 0xc641>, 1128 <&main_udmap 0xc642>, 1129 <&main_udmap 0xc643>, 1130 <&main_udmap 0xc644>, 1131 <&main_udmap 0xc645>, 1132 <&main_udmap 0xc646>, 1133 <&main_udmap 0xc647>, 1134 <&main_udmap 0x4640>; 1135 dma-names = "tx0", "tx1", "tx2", "tx3", 1136 "tx4", "tx5", "tx6", "tx7", 1137 "rx"; 1138 1139 status = "disabled"; 1140 1141 ethernet-ports { 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 1145 main_cpsw_port1: port@1 { 1146 reg = <1>; 1147 ti,mac-only; 1148 label = "port1"; 1149 phys = <&phy_gmii_sel_cpsw 1>; 1150 status = "disabled"; 1151 }; 1152 }; 1153 1154 main_cpsw_mdio: mdio@f00 { 1155 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1156 reg = <0x00 0xf00 0x00 0x100>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 clocks = <&k3_clks 28 28>; 1160 clock-names = "fck"; 1161 bus_freq = <1000000>; 1162 status = "disabled"; 1163 }; 1164 1165 cpts@3d000 { 1166 compatible = "ti,am65-cpts"; 1167 reg = <0x00 0x3d000 0x00 0x400>; 1168 clocks = <&k3_clks 28 3>; 1169 clock-names = "cpts"; 1170 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "cpts"; 1172 ti,cpts-ext-ts-inputs = <4>; 1173 ti,cpts-periodic-outputs = <2>; 1174 }; 1175 }; 1176 1177 usbss0: cdns-usb@4104000 { 1178 compatible = "ti,j721e-usb"; 1179 reg = <0x00 0x04104000 0x00 0x100>; 1180 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 1181 clock-names = "ref", "lpm"; 1182 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 1183 assigned-clock-parents = <&k3_clks 360 17>; 1184 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1185 #address-cells = <2>; 1186 #size-cells = <2>; 1187 ranges; 1188 dma-coherent; 1189 1190 status = "disabled"; /* Needs pinmux */ 1191 1192 usb0: usb@6000000 { 1193 compatible = "cdns,usb3"; 1194 reg = <0x00 0x06000000 0x00 0x10000>, 1195 <0x00 0x06010000 0x00 0x10000>, 1196 <0x00 0x06020000 0x00 0x10000>; 1197 reg-names = "otg", "xhci", "dev"; 1198 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1201 interrupt-names = "host", "peripheral", "otg"; 1202 maximum-speed = "super-speed"; 1203 dr_mode = "otg"; 1204 }; 1205 }; 1206 1207 serdes_wiz0: wiz@5060000 { 1208 compatible = "ti,j721s2-wiz-10g"; 1209 #address-cells = <1>; 1210 #size-cells = <1>; 1211 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1212 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1213 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1214 num-lanes = <4>; 1215 #reset-cells = <1>; 1216 #clock-cells = <1>; 1217 ranges = <0x5060000 0x0 0x5060000 0x10000>; 1218 1219 assigned-clocks = <&k3_clks 365 3>; 1220 assigned-clock-parents = <&k3_clks 365 7>; 1221 1222 serdes0: serdes@5060000 { 1223 compatible = "ti,j721e-serdes-10g"; 1224 reg = <0x05060000 0x00010000>; 1225 reg-names = "torrent_phy"; 1226 resets = <&serdes_wiz0 0>; 1227 reset-names = "torrent_reset"; 1228 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1229 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1230 clock-names = "refclk", "phy_en_refclk"; 1231 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1232 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1233 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1234 assigned-clock-parents = <&k3_clks 365 3>, 1235 <&k3_clks 365 3>, 1236 <&k3_clks 365 3>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 #clock-cells = <1>; 1240 1241 status = "disabled"; /* Needs lane config */ 1242 }; 1243 }; 1244 1245 pcie1_rc: pcie@2910000 { 1246 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1247 reg = <0x00 0x02910000 0x00 0x1000>, 1248 <0x00 0x02917000 0x00 0x400>, 1249 <0x00 0x0d800000 0x00 0x800000>, 1250 <0x00 0x18000000 0x00 0x1000>; 1251 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1252 interrupt-names = "link_state"; 1253 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1254 device_type = "pci"; 1255 ti,syscon-pcie-ctrl = <&scm_conf 0x074>; 1256 max-link-speed = <3>; 1257 num-lanes = <4>; 1258 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1259 clocks = <&k3_clks 276 41>; 1260 clock-names = "fck"; 1261 #address-cells = <3>; 1262 #size-cells = <2>; 1263 bus-range = <0x0 0xff>; 1264 vendor-id = <0x104c>; 1265 device-id = <0xb013>; 1266 msi-map = <0x0 &gic_its 0x0 0x10000>; 1267 dma-coherent; 1268 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1269 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1270 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1271 #interrupt-cells = <1>; 1272 interrupt-map-mask = <0 0 0 7>; 1273 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1274 <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1275 <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1276 <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1277 1278 status = "disabled"; /* Needs gpio and serdes info */ 1279 1280 pcie1_intc: interrupt-controller { 1281 interrupt-controller; 1282 #interrupt-cells = <1>; 1283 interrupt-parent = <&gic500>; 1284 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1285 }; 1286 }; 1287 1288 main_mcan0: can@2701000 { 1289 compatible = "bosch,m_can"; 1290 reg = <0x00 0x02701000 0x00 0x200>, 1291 <0x00 0x02708000 0x00 0x8000>; 1292 reg-names = "m_can", "message_ram"; 1293 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1294 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1295 clock-names = "hclk", "cclk"; 1296 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1298 interrupt-names = "int0", "int1"; 1299 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1300 status = "disabled"; 1301 }; 1302 1303 main_mcan1: can@2711000 { 1304 compatible = "bosch,m_can"; 1305 reg = <0x00 0x02711000 0x00 0x200>, 1306 <0x00 0x02718000 0x00 0x8000>; 1307 reg-names = "m_can", "message_ram"; 1308 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1309 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1310 clock-names = "hclk", "cclk"; 1311 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1313 interrupt-names = "int0", "int1"; 1314 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1315 status = "disabled"; 1316 }; 1317 1318 main_mcan2: can@2721000 { 1319 compatible = "bosch,m_can"; 1320 reg = <0x00 0x02721000 0x00 0x200>, 1321 <0x00 0x02728000 0x00 0x8000>; 1322 reg-names = "m_can", "message_ram"; 1323 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1324 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1325 clock-names = "hclk", "cclk"; 1326 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1328 interrupt-names = "int0", "int1"; 1329 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1330 status = "disabled"; 1331 }; 1332 1333 main_mcan3: can@2731000 { 1334 compatible = "bosch,m_can"; 1335 reg = <0x00 0x02731000 0x00 0x200>, 1336 <0x00 0x02738000 0x00 0x8000>; 1337 reg-names = "m_can", "message_ram"; 1338 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1339 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1340 clock-names = "hclk", "cclk"; 1341 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1343 interrupt-names = "int0", "int1"; 1344 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1345 status = "disabled"; 1346 }; 1347 1348 main_mcan4: can@2741000 { 1349 compatible = "bosch,m_can"; 1350 reg = <0x00 0x02741000 0x00 0x200>, 1351 <0x00 0x02748000 0x00 0x8000>; 1352 reg-names = "m_can", "message_ram"; 1353 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1354 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1355 clock-names = "hclk", "cclk"; 1356 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1358 interrupt-names = "int0", "int1"; 1359 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1360 status = "disabled"; 1361 }; 1362 1363 main_mcan5: can@2751000 { 1364 compatible = "bosch,m_can"; 1365 reg = <0x00 0x02751000 0x00 0x200>, 1366 <0x00 0x02758000 0x00 0x8000>; 1367 reg-names = "m_can", "message_ram"; 1368 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1369 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1370 clock-names = "hclk", "cclk"; 1371 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1373 interrupt-names = "int0", "int1"; 1374 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1375 status = "disabled"; 1376 }; 1377 1378 main_mcan6: can@2761000 { 1379 compatible = "bosch,m_can"; 1380 reg = <0x00 0x02761000 0x00 0x200>, 1381 <0x00 0x02768000 0x00 0x8000>; 1382 reg-names = "m_can", "message_ram"; 1383 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1384 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1385 clock-names = "hclk", "cclk"; 1386 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "int0", "int1"; 1389 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1390 status = "disabled"; 1391 }; 1392 1393 main_mcan7: can@2771000 { 1394 compatible = "bosch,m_can"; 1395 reg = <0x00 0x02771000 0x00 0x200>, 1396 <0x00 0x02778000 0x00 0x8000>; 1397 reg-names = "m_can", "message_ram"; 1398 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1399 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1400 clock-names = "hclk", "cclk"; 1401 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupt-names = "int0", "int1"; 1404 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1405 status = "disabled"; 1406 }; 1407 1408 main_mcan8: can@2781000 { 1409 compatible = "bosch,m_can"; 1410 reg = <0x00 0x02781000 0x00 0x200>, 1411 <0x00 0x02788000 0x00 0x8000>; 1412 reg-names = "m_can", "message_ram"; 1413 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1414 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1415 clock-names = "hclk", "cclk"; 1416 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1418 interrupt-names = "int0", "int1"; 1419 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1420 status = "disabled"; 1421 }; 1422 1423 main_mcan9: can@2791000 { 1424 compatible = "bosch,m_can"; 1425 reg = <0x00 0x02791000 0x00 0x200>, 1426 <0x00 0x02798000 0x00 0x8000>; 1427 reg-names = "m_can", "message_ram"; 1428 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1429 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1430 clock-names = "hclk", "cclk"; 1431 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1433 interrupt-names = "int0", "int1"; 1434 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1435 status = "disabled"; 1436 }; 1437 1438 main_mcan10: can@27a1000 { 1439 compatible = "bosch,m_can"; 1440 reg = <0x00 0x027a1000 0x00 0x200>, 1441 <0x00 0x027a8000 0x00 0x8000>; 1442 reg-names = "m_can", "message_ram"; 1443 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1444 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1445 clock-names = "hclk", "cclk"; 1446 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1448 interrupt-names = "int0", "int1"; 1449 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1450 status = "disabled"; 1451 }; 1452 1453 main_mcan11: can@27b1000 { 1454 compatible = "bosch,m_can"; 1455 reg = <0x00 0x027b1000 0x00 0x200>, 1456 <0x00 0x027b8000 0x00 0x8000>; 1457 reg-names = "m_can", "message_ram"; 1458 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1459 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1460 clock-names = "hclk", "cclk"; 1461 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1463 interrupt-names = "int0", "int1"; 1464 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1465 status = "disabled"; 1466 }; 1467 1468 main_mcan12: can@27c1000 { 1469 compatible = "bosch,m_can"; 1470 reg = <0x00 0x027c1000 0x00 0x200>, 1471 <0x00 0x027c8000 0x00 0x8000>; 1472 reg-names = "m_can", "message_ram"; 1473 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1474 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1475 clock-names = "hclk", "cclk"; 1476 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1478 interrupt-names = "int0", "int1"; 1479 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1480 status = "disabled"; 1481 }; 1482 1483 main_mcan13: can@27d1000 { 1484 compatible = "bosch,m_can"; 1485 reg = <0x00 0x027d1000 0x00 0x200>, 1486 <0x00 0x027d8000 0x00 0x8000>; 1487 reg-names = "m_can", "message_ram"; 1488 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1489 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1490 clock-names = "hclk", "cclk"; 1491 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1493 interrupt-names = "int0", "int1"; 1494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1495 status = "disabled"; 1496 }; 1497 1498 main_mcan14: can@2681000 { 1499 compatible = "bosch,m_can"; 1500 reg = <0x00 0x02681000 0x00 0x200>, 1501 <0x00 0x02688000 0x00 0x8000>; 1502 reg-names = "m_can", "message_ram"; 1503 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1504 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1505 clock-names = "hclk", "cclk"; 1506 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-names = "int0", "int1"; 1509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1510 status = "disabled"; 1511 }; 1512 1513 main_mcan15: can@2691000 { 1514 compatible = "bosch,m_can"; 1515 reg = <0x00 0x02691000 0x00 0x200>, 1516 <0x00 0x02698000 0x00 0x8000>; 1517 reg-names = "m_can", "message_ram"; 1518 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1519 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1520 clock-names = "hclk", "cclk"; 1521 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1523 interrupt-names = "int0", "int1"; 1524 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1525 status = "disabled"; 1526 }; 1527 1528 main_mcan16: can@26a1000 { 1529 compatible = "bosch,m_can"; 1530 reg = <0x00 0x026a1000 0x00 0x200>, 1531 <0x00 0x026a8000 0x00 0x8000>; 1532 reg-names = "m_can", "message_ram"; 1533 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1534 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1535 clock-names = "hclk", "cclk"; 1536 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1538 interrupt-names = "int0", "int1"; 1539 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1540 status = "disabled"; 1541 }; 1542 1543 main_mcan17: can@26b1000 { 1544 compatible = "bosch,m_can"; 1545 reg = <0x00 0x026b1000 0x00 0x200>, 1546 <0x00 0x026b8000 0x00 0x8000>; 1547 reg-names = "m_can", "message_ram"; 1548 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1549 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1550 clock-names = "hclk", "cclk"; 1551 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1553 interrupt-names = "int0", "int1"; 1554 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1555 status = "disabled"; 1556 }; 1557 1558 main_spi0: spi@2100000 { 1559 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1560 reg = <0x00 0x02100000 0x00 0x400>; 1561 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 1565 clocks = <&k3_clks 339 1>; 1566 status = "disabled"; 1567 }; 1568 1569 main_spi1: spi@2110000 { 1570 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1571 reg = <0x00 0x02110000 0x00 0x400>; 1572 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 1576 clocks = <&k3_clks 340 1>; 1577 status = "disabled"; 1578 }; 1579 1580 main_spi2: spi@2120000 { 1581 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1582 reg = <0x00 0x02120000 0x00 0x400>; 1583 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 1587 clocks = <&k3_clks 341 1>; 1588 status = "disabled"; 1589 }; 1590 1591 main_spi3: spi@2130000 { 1592 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1593 reg = <0x00 0x02130000 0x00 0x400>; 1594 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 1598 clocks = <&k3_clks 342 1>; 1599 status = "disabled"; 1600 }; 1601 1602 main_spi4: spi@2140000 { 1603 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1604 reg = <0x00 0x02140000 0x00 0x400>; 1605 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 1609 clocks = <&k3_clks 343 1>; 1610 status = "disabled"; 1611 }; 1612 1613 main_spi5: spi@2150000 { 1614 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1615 reg = <0x00 0x02150000 0x00 0x400>; 1616 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 1620 clocks = <&k3_clks 344 1>; 1621 status = "disabled"; 1622 }; 1623 1624 main_spi6: spi@2160000 { 1625 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1626 reg = <0x00 0x02160000 0x00 0x400>; 1627 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 1631 clocks = <&k3_clks 345 1>; 1632 status = "disabled"; 1633 }; 1634 1635 main_spi7: spi@2170000 { 1636 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1637 reg = <0x00 0x02170000 0x00 0x400>; 1638 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1642 clocks = <&k3_clks 346 1>; 1643 status = "disabled"; 1644 }; 1645 1646 dss: dss@4a00000 { 1647 compatible = "ti,j721e-dss"; 1648 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1649 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1650 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1651 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1652 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1653 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1654 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1655 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1656 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1657 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1658 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1659 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1660 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1661 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1662 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1663 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1664 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1665 reg-names = "common_m", "common_s0", 1666 "common_s1", "common_s2", 1667 "vidl1", "vidl2","vid1","vid2", 1668 "ovr1", "ovr2", "ovr3", "ovr4", 1669 "vp1", "vp2", "vp3", "vp4", 1670 "wb"; 1671 clocks = <&k3_clks 158 0>, 1672 <&k3_clks 158 2>, 1673 <&k3_clks 158 5>, 1674 <&k3_clks 158 14>, 1675 <&k3_clks 158 18>; 1676 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1677 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 1678 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1682 interrupt-names = "common_m", 1683 "common_s0", 1684 "common_s1", 1685 "common_s2"; 1686 status = "disabled"; 1687 1688 dss_ports: ports { 1689 }; 1690 }; 1691}; 1692