1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/k3.h> 11 12/ { 13 model = "Texas Instruments K3 J721E SoC"; 14 compatible = "ti,j721e"; 15 interrupt-parent = <&gic500>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 serial4 = &main_uart2; 25 serial5 = &main_uart3; 26 serial6 = &main_uart4; 27 serial7 = &main_uart5; 28 serial8 = &main_uart6; 29 serial9 = &main_uart7; 30 serial10 = &main_uart8; 31 serial11 = &main_uart9; 32 }; 33 34 chosen { }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 cpu-map { 40 cluster0: cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 45 core1 { 46 cpu = <&cpu1>; 47 }; 48 }; 49 50 }; 51 52 cpu0: cpu@0 { 53 compatible = "arm,cortex-a72"; 54 reg = <0x000>; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 i-cache-size = <0xC000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&L2_0>; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a72"; 68 reg = <0x001>; 69 device_type = "cpu"; 70 enable-method = "psci"; 71 i-cache-size = <0xC000>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <256>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&L2_0>; 78 }; 79 }; 80 81 L2_0: l2-cache0 { 82 compatible = "cache"; 83 cache-level = <2>; 84 cache-size = <0x100000>; 85 cache-line-size = <64>; 86 cache-sets = <2048>; 87 next-level-cache = <&msmc_l3>; 88 }; 89 90 msmc_l3: l3-cache0 { 91 compatible = "cache"; 92 cache-level = <3>; 93 }; 94 95 firmware { 96 optee { 97 compatible = "linaro,optee-tz"; 98 method = "smc"; 99 }; 100 101 psci: psci { 102 compatible = "arm,psci-1.0"; 103 method = "smc"; 104 }; 105 }; 106 107 a72_timer0: timer-cl0-cpu0 { 108 compatible = "arm,armv8-timer"; 109 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 110 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 111 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 112 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 113 }; 114 115 pmu: pmu { 116 compatible = "arm,armv8-pmuv3"; 117 /* Recommendation from GIC500 TRM Table A.3 */ 118 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 cbass_main: interconnect@100000 { 122 compatible = "simple-bus"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 126 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 127 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 128 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ 129 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 130 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 131 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ 132 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 133 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ 134 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ 135 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ 136 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 137 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 138 139 /* MCUSS_WKUP Range */ 140 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 141 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 142 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 143 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 144 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 145 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 146 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 147 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 148 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 149 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 150 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 151 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 152 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 153 154 cbass_mcu_wakeup: interconnect@28380000 { 155 compatible = "simple-bus"; 156 #address-cells = <2>; 157 #size-cells = <2>; 158 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 159 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 160 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 161 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 162 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 163 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 164 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 165 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 166 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 167 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 168 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 169 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 170 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 171 }; 172 }; 173}; 174 175/* Now include the peripherals for each bus segments */ 176#include "k3-j721e-main.dtsi" 177#include "k3-j721e-mcu-wakeup.dtsi" 178