1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/k3.h> 11#include <dt-bindings/soc/ti,sci_pm_domain.h> 12 13/ { 14 model = "Texas Instruments K3 J721E SoC"; 15 compatible = "ti,j721e"; 16 interrupt-parent = <&gic500>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 serial5 = &main_uart3; 27 serial6 = &main_uart4; 28 serial7 = &main_uart5; 29 serial8 = &main_uart6; 30 serial9 = &main_uart7; 31 serial10 = &main_uart8; 32 serial11 = &main_uart9; 33 ethernet0 = &cpsw_port1; 34 mmc0 = &main_sdhci0; 35 mmc1 = &main_sdhci1; 36 mmc2 = &main_sdhci2; 37 }; 38 39 chosen { }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 cpu-map { 45 cluster0: cluster0 { 46 core0 { 47 cpu = <&cpu0>; 48 }; 49 50 core1 { 51 cpu = <&cpu1>; 52 }; 53 }; 54 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a72"; 59 reg = <0x000>; 60 device_type = "cpu"; 61 enable-method = "psci"; 62 i-cache-size = <0xC000>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <256>; 65 d-cache-size = <0x8000>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <256>; 68 next-level-cache = <&L2_0>; 69 }; 70 71 cpu1: cpu@1 { 72 compatible = "arm,cortex-a72"; 73 reg = <0x001>; 74 device_type = "cpu"; 75 enable-method = "psci"; 76 i-cache-size = <0xC000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 d-cache-size = <0x8000>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <256>; 82 next-level-cache = <&L2_0>; 83 }; 84 }; 85 86 L2_0: l2-cache0 { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-size = <0x100000>; 90 cache-line-size = <64>; 91 cache-sets = <1024>; 92 next-level-cache = <&msmc_l3>; 93 }; 94 95 msmc_l3: l3-cache0 { 96 compatible = "cache"; 97 cache-level = <3>; 98 }; 99 100 firmware { 101 optee { 102 compatible = "linaro,optee-tz"; 103 method = "smc"; 104 }; 105 106 psci: psci { 107 compatible = "arm,psci-1.0"; 108 method = "smc"; 109 }; 110 }; 111 112 a72_timer0: timer-cl0-cpu0 { 113 compatible = "arm,armv8-timer"; 114 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 115 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 116 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 117 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 118 }; 119 120 pmu: pmu { 121 compatible = "arm,cortex-a72-pmu"; 122 /* Recommendation from GIC500 TRM Table A.3 */ 123 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 124 }; 125 126 cbass_main: bus@100000 { 127 compatible = "simple-bus"; 128 #address-cells = <2>; 129 #size-cells = <2>; 130 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 131 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 132 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 133 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ 134 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ 135 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ 136 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 137 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 138 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ 139 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ 140 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 141 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ 142 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 143 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ 144 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ 145 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ 146 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ 147 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 148 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 149 150 /* MCUSS_WKUP Range */ 151 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 152 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 153 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 154 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 155 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 156 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 157 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 158 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 159 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 160 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 161 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 162 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 163 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 164 165 cbass_mcu_wakeup: bus@28380000 { 166 compatible = "simple-bus"; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 170 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 171 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 172 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 173 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 174 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 175 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 176 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 177 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 178 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 179 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 180 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 181 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 182 }; 183 }; 184}; 185 186/* Now include the peripherals for each bus segments */ 187#include "k3-j721e-main.dtsi" 188#include "k3-j721e-mcu-wakeup.dtsi" 189