1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/soc/ti,sci_pm_domain.h> 11 12#include "k3-pinctrl.h" 13 14/ { 15 model = "Texas Instruments K3 J721E SoC"; 16 compatible = "ti,j721e"; 17 interrupt-parent = <&gic500>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 serial0 = &wkup_uart0; 23 serial1 = &mcu_uart0; 24 serial2 = &main_uart0; 25 serial3 = &main_uart1; 26 serial4 = &main_uart2; 27 serial5 = &main_uart3; 28 serial6 = &main_uart4; 29 serial7 = &main_uart5; 30 serial8 = &main_uart6; 31 serial9 = &main_uart7; 32 serial10 = &main_uart8; 33 serial11 = &main_uart9; 34 ethernet0 = &cpsw_port1; 35 mmc0 = &main_sdhci0; 36 mmc1 = &main_sdhci1; 37 mmc2 = &main_sdhci2; 38 }; 39 40 chosen { }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 cpu-map { 46 cluster0: cluster0 { 47 core0 { 48 cpu = <&cpu0>; 49 }; 50 51 core1 { 52 cpu = <&cpu1>; 53 }; 54 }; 55 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a72"; 60 reg = <0x000>; 61 device_type = "cpu"; 62 enable-method = "psci"; 63 i-cache-size = <0xC000>; 64 i-cache-line-size = <64>; 65 i-cache-sets = <256>; 66 d-cache-size = <0x8000>; 67 d-cache-line-size = <64>; 68 d-cache-sets = <256>; 69 next-level-cache = <&L2_0>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a72"; 74 reg = <0x001>; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 i-cache-size = <0xC000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <256>; 83 next-level-cache = <&L2_0>; 84 }; 85 }; 86 87 L2_0: l2-cache0 { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 cache-size = <0x100000>; 92 cache-line-size = <64>; 93 cache-sets = <1024>; 94 next-level-cache = <&msmc_l3>; 95 }; 96 97 msmc_l3: l3-cache0 { 98 compatible = "cache"; 99 cache-level = <3>; 100 }; 101 102 firmware { 103 optee { 104 compatible = "linaro,optee-tz"; 105 method = "smc"; 106 }; 107 108 psci: psci { 109 compatible = "arm,psci-1.0"; 110 method = "smc"; 111 }; 112 }; 113 114 a72_timer0: timer-cl0-cpu0 { 115 compatible = "arm,armv8-timer"; 116 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 117 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 118 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 119 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 120 }; 121 122 pmu: pmu { 123 compatible = "arm,cortex-a72-pmu"; 124 /* Recommendation from GIC500 TRM Table A.3 */ 125 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 126 }; 127 128 cbass_main: bus@100000 { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 133 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 134 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 135 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ 136 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ 137 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ 138 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 139 <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ 140 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 141 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ 142 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ 143 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 144 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ 145 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 146 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ 147 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ 148 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ 149 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ 150 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 151 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 152 153 /* MCUSS_WKUP Range */ 154 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 155 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 156 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 157 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 158 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 159 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 160 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 161 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 162 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 163 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 164 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 165 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 166 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 167 168 cbass_mcu_wakeup: bus@28380000 { 169 compatible = "simple-bus"; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 173 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 174 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 175 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 176 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 177 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 178 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 179 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 180 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 181 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 182 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 183 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 184 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 185 }; 186 }; 187}; 188 189/* Now include the peripherals for each bus segments */ 190#include "k3-j721e-main.dtsi" 191#include "k3-j721e-mcu-wakeup.dtsi" 192