1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/k3.h> 11#include <dt-bindings/soc/ti,sci_pm_domain.h> 12 13/ { 14 model = "Texas Instruments K3 J721E SoC"; 15 compatible = "ti,j721e"; 16 interrupt-parent = <&gic500>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 serial5 = &main_uart3; 27 serial6 = &main_uart4; 28 serial7 = &main_uart5; 29 serial8 = &main_uart6; 30 serial9 = &main_uart7; 31 serial10 = &main_uart8; 32 serial11 = &main_uart9; 33 }; 34 35 chosen { }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 cpu-map { 41 cluster0: cluster0 { 42 core0 { 43 cpu = <&cpu0>; 44 }; 45 46 core1 { 47 cpu = <&cpu1>; 48 }; 49 }; 50 51 }; 52 53 cpu0: cpu@0 { 54 compatible = "arm,cortex-a72"; 55 reg = <0x000>; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 i-cache-size = <0xC000>; 59 i-cache-line-size = <64>; 60 i-cache-sets = <256>; 61 d-cache-size = <0x8000>; 62 d-cache-line-size = <64>; 63 d-cache-sets = <128>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 cpu1: cpu@1 { 68 compatible = "arm,cortex-a72"; 69 reg = <0x001>; 70 device_type = "cpu"; 71 enable-method = "psci"; 72 i-cache-size = <0xC000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <256>; 75 d-cache-size = <0x8000>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&L2_0>; 79 }; 80 }; 81 82 L2_0: l2-cache0 { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-size = <0x100000>; 86 cache-line-size = <64>; 87 cache-sets = <2048>; 88 next-level-cache = <&msmc_l3>; 89 }; 90 91 msmc_l3: l3-cache0 { 92 compatible = "cache"; 93 cache-level = <3>; 94 }; 95 96 firmware { 97 optee { 98 compatible = "linaro,optee-tz"; 99 method = "smc"; 100 }; 101 102 psci: psci { 103 compatible = "arm,psci-1.0"; 104 method = "smc"; 105 }; 106 }; 107 108 a72_timer0: timer-cl0-cpu0 { 109 compatible = "arm,armv8-timer"; 110 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 111 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 112 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 113 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 114 }; 115 116 pmu: pmu { 117 compatible = "arm,armv8-pmuv3"; 118 /* Recommendation from GIC500 TRM Table A.3 */ 119 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 cbass_main: interconnect@100000 { 123 compatible = "simple-bus"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 127 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 128 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 129 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ 130 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 131 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 132 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ 133 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 134 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ 135 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ 136 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ 137 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 138 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 139 140 /* MCUSS_WKUP Range */ 141 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 142 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 143 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 144 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 145 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 146 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 147 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 148 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 149 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 150 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 151 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 152 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 153 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 154 155 cbass_mcu_wakeup: interconnect@28380000 { 156 compatible = "simple-bus"; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 160 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 161 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 162 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 163 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 164 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 165 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 166 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 167 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 168 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 169 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 170 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 171 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 172 }; 173 }; 174}; 175 176/* Now include the peripherals for each bus segments */ 177#include "k3-j721e-main.dtsi" 178#include "k3-j721e-mcu-wakeup.dtsi" 179