1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Product Link: https://www.ti.com/tool/J721EXSOMXEVM
6 */
7
8/dts-v1/;
9
10#include "k3-j721e.dtsi"
11
12/ {
13	memory@80000000 {
14		device_type = "memory";
15		/* 4G RAM */
16		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17		      <0x00000008 0x80000000 0x00000000 0x80000000>;
18	};
19
20	reserved_memory: reserved-memory {
21		#address-cells = <2>;
22		#size-cells = <2>;
23		ranges;
24
25		secure_ddr: optee@9e800000 {
26			reg = <0x00 0x9e800000 0x00 0x01800000>;
27			alignment = <0x1000>;
28			no-map;
29		};
30
31		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
32			compatible = "shared-dma-pool";
33			reg = <0x00 0xa0000000 0x00 0x100000>;
34			no-map;
35		};
36
37		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
38			compatible = "shared-dma-pool";
39			reg = <0x00 0xa0100000 0x00 0xf00000>;
40			no-map;
41		};
42
43		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
44			compatible = "shared-dma-pool";
45			reg = <0x00 0xa1000000 0x00 0x100000>;
46			no-map;
47		};
48
49		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
50			compatible = "shared-dma-pool";
51			reg = <0x00 0xa1100000 0x00 0xf00000>;
52			no-map;
53		};
54
55		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
56			compatible = "shared-dma-pool";
57			reg = <0x00 0xa2000000 0x00 0x100000>;
58			no-map;
59		};
60
61		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
62			compatible = "shared-dma-pool";
63			reg = <0x00 0xa2100000 0x00 0xf00000>;
64			no-map;
65		};
66
67		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
68			compatible = "shared-dma-pool";
69			reg = <0x00 0xa3000000 0x00 0x100000>;
70			no-map;
71		};
72
73		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
74			compatible = "shared-dma-pool";
75			reg = <0x00 0xa3100000 0x00 0xf00000>;
76			no-map;
77		};
78
79		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
80			compatible = "shared-dma-pool";
81			reg = <0x00 0xa4000000 0x00 0x100000>;
82			no-map;
83		};
84
85		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
86			compatible = "shared-dma-pool";
87			reg = <0x00 0xa4100000 0x00 0xf00000>;
88			no-map;
89		};
90
91		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
92			compatible = "shared-dma-pool";
93			reg = <0x00 0xa5000000 0x00 0x100000>;
94			no-map;
95		};
96
97		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
98			compatible = "shared-dma-pool";
99			reg = <0x00 0xa5100000 0x00 0xf00000>;
100			no-map;
101		};
102
103		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
104			compatible = "shared-dma-pool";
105			reg = <0x00 0xa6000000 0x00 0x100000>;
106			no-map;
107		};
108
109		c66_0_memory_region: c66-memory@a6100000 {
110			compatible = "shared-dma-pool";
111			reg = <0x00 0xa6100000 0x00 0xf00000>;
112			no-map;
113		};
114
115		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
116			compatible = "shared-dma-pool";
117			reg = <0x00 0xa7000000 0x00 0x100000>;
118			no-map;
119		};
120
121		c66_1_memory_region: c66-memory@a7100000 {
122			compatible = "shared-dma-pool";
123			reg = <0x00 0xa7100000 0x00 0xf00000>;
124			no-map;
125		};
126
127		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
128			compatible = "shared-dma-pool";
129			reg = <0x00 0xa8000000 0x00 0x100000>;
130			no-map;
131		};
132
133		c71_0_memory_region: c71-memory@a8100000 {
134			compatible = "shared-dma-pool";
135			reg = <0x00 0xa8100000 0x00 0xf00000>;
136			no-map;
137		};
138
139		rtos_ipc_memory_region: ipc-memories@aa000000 {
140			reg = <0x00 0xaa000000 0x00 0x01c00000>;
141			alignment = <0x1000>;
142			no-map;
143		};
144	};
145};
146
147&wkup_pmx0 {
148	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
149		pinctrl-single,pins = <
150			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
151			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
152		>;
153	};
154
155	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
156		pinctrl-single,pins = <
157			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
158			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
159			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
160			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
161			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
162			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
163			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
164			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
165			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
166			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
167			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
168		>;
169	};
170
171	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
172		pinctrl-single,pins = <
173			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CK */
174			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CKn */
175			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
176			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
177			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
178			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1)   /* MCU_HYPERBUS0_RWDS */
179			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1)   /* MCU_HYPERBUS0_DQ0 */
180			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ1 */
181			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ2 */
182			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ3 */
183			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ4 */
184			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
185			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
186			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
187		>;
188	};
189};
190
191&wkup_i2c0 {
192	status = "okay";
193	pinctrl-names = "default";
194	pinctrl-0 = <&wkup_i2c0_pins_default>;
195	clock-frequency = <400000>;
196
197	eeprom@50 {
198		/* CAV24C256WE-GT3 */
199		compatible = "atmel,24c256";
200		reg = <0x50>;
201	};
202};
203
204&ospi0 {
205	status = "okay";
206	pinctrl-names = "default";
207	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
208
209	flash@0 {
210		compatible = "jedec,spi-nor";
211		reg = <0x0>;
212		spi-tx-bus-width = <8>;
213		spi-rx-bus-width = <8>;
214		spi-max-frequency = <25000000>;
215		cdns,tshsl-ns = <60>;
216		cdns,tsd2d-ns = <60>;
217		cdns,tchsh-ns = <60>;
218		cdns,tslch-ns = <60>;
219		cdns,read-delay = <0>;
220
221		partitions {
222			compatible = "fixed-partitions";
223			#address-cells = <1>;
224			#size-cells = <1>;
225
226			partition@0 {
227				label = "ospi.tiboot3";
228				reg = <0x0 0x80000>;
229			};
230
231			partition@80000 {
232				label = "ospi.tispl";
233				reg = <0x80000 0x200000>;
234			};
235
236			partition@280000 {
237				label = "ospi.u-boot";
238				reg = <0x280000 0x400000>;
239			};
240
241			partition@680000 {
242				label = "ospi.env";
243				reg = <0x680000 0x20000>;
244			};
245
246			partition@6a0000 {
247				label = "ospi.env.backup";
248				reg = <0x6a0000 0x20000>;
249			};
250
251			partition@6c0000 {
252				label = "ospi.sysfw";
253				reg = <0x6c0000 0x100000>;
254			};
255
256			partition@800000 {
257				label = "ospi.rootfs";
258				reg = <0x800000 0x37c0000>;
259			};
260
261			partition@3fe0000 {
262				label = "ospi.phypattern";
263				reg = <0x3fe0000 0x20000>;
264			};
265		};
266	};
267};
268
269&hbmc {
270	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
271	 * appropriate node based on board detection
272	 */
273	status = "disabled";
274	pinctrl-names = "default";
275	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
276	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
277		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
278
279	flash@0,0 {
280		compatible = "cypress,hyperflash", "cfi-flash";
281		reg = <0x00 0x00 0x4000000>;
282
283		partitions {
284			compatible = "fixed-partitions";
285			#address-cells = <1>;
286			#size-cells = <1>;
287
288			partition@0 {
289				label = "hbmc.tiboot3";
290				reg = <0x0 0x80000>;
291			};
292
293			partition@80000 {
294				label = "hbmc.tispl";
295				reg = <0x80000 0x200000>;
296			};
297
298			partition@280000 {
299				label = "hbmc.u-boot";
300				reg = <0x280000 0x400000>;
301			};
302
303			partition@680000 {
304				label = "hbmc.env";
305				reg = <0x680000 0x40000>;
306			};
307
308			partition@6c0000 {
309				label = "hbmc.sysfw";
310				reg = <0x6c0000 0x100000>;
311			};
312
313			partition@800000 {
314				label = "hbmc.rootfs";
315				reg = <0x800000 0x3800000>;
316			};
317		};
318	};
319};
320
321&mailbox0_cluster0 {
322	status = "okay";
323	interrupts = <436>;
324
325	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
326		ti,mbox-rx = <0 0 0>;
327		ti,mbox-tx = <1 0 0>;
328	};
329
330	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
331		ti,mbox-rx = <2 0 0>;
332		ti,mbox-tx = <3 0 0>;
333	};
334};
335
336&mailbox0_cluster1 {
337	status = "okay";
338	interrupts = <432>;
339
340	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
341		ti,mbox-rx = <0 0 0>;
342		ti,mbox-tx = <1 0 0>;
343	};
344
345	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
346		ti,mbox-rx = <2 0 0>;
347		ti,mbox-tx = <3 0 0>;
348	};
349};
350
351&mailbox0_cluster2 {
352	status = "okay";
353	interrupts = <428>;
354
355	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
356		ti,mbox-rx = <0 0 0>;
357		ti,mbox-tx = <1 0 0>;
358	};
359
360	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
361		ti,mbox-rx = <2 0 0>;
362		ti,mbox-tx = <3 0 0>;
363	};
364};
365
366&mailbox0_cluster3 {
367	status = "okay";
368	interrupts = <424>;
369
370	mbox_c66_0: mbox-c66-0 {
371		ti,mbox-rx = <0 0 0>;
372		ti,mbox-tx = <1 0 0>;
373	};
374
375	mbox_c66_1: mbox-c66-1 {
376		ti,mbox-rx = <2 0 0>;
377		ti,mbox-tx = <3 0 0>;
378	};
379};
380
381&mailbox0_cluster4 {
382	status = "okay";
383	interrupts = <420>;
384
385	mbox_c71_0: mbox-c71-0 {
386		ti,mbox-rx = <0 0 0>;
387		ti,mbox-tx = <1 0 0>;
388	};
389};
390
391&mcu_r5fss0_core0 {
392	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
393	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
394			<&mcu_r5fss0_core0_memory_region>;
395};
396
397&mcu_r5fss0_core1 {
398	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
399	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
400			<&mcu_r5fss0_core1_memory_region>;
401};
402
403&main_r5fss0_core0 {
404	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
405	memory-region = <&main_r5fss0_core0_dma_memory_region>,
406			<&main_r5fss0_core0_memory_region>;
407};
408
409&main_r5fss0_core1 {
410	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
411	memory-region = <&main_r5fss0_core1_dma_memory_region>,
412			<&main_r5fss0_core1_memory_region>;
413};
414
415&main_r5fss1_core0 {
416	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
417	memory-region = <&main_r5fss1_core0_dma_memory_region>,
418			<&main_r5fss1_core0_memory_region>;
419};
420
421&main_r5fss1_core1 {
422	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
423	memory-region = <&main_r5fss1_core1_dma_memory_region>,
424			<&main_r5fss1_core1_memory_region>;
425};
426
427&c66_0 {
428	status = "okay";
429	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
430	memory-region = <&c66_0_dma_memory_region>,
431			<&c66_0_memory_region>;
432};
433
434&c66_1 {
435	status = "okay";
436	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
437	memory-region = <&c66_1_dma_memory_region>,
438			<&c66_1_memory_region>;
439};
440
441&c71_0 {
442	status = "okay";
443	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
444	memory-region = <&c71_0_dma_memory_region>,
445			<&c71_0_memory_region>;
446};
447