1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 4G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 28 <0x00000008 0x80000000 0x00000000 0x80000000>; 29 }; 30 31 reserved_memory: reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa4000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa4100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa5000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa5100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0x00 0xa6000000 0x00 0x100000>; 117 no-map; 118 }; 119 120 c66_0_memory_region: c66-memory@a6100000 { 121 compatible = "shared-dma-pool"; 122 reg = <0x00 0xa6100000 0x00 0xf00000>; 123 no-map; 124 }; 125 126 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 127 compatible = "shared-dma-pool"; 128 reg = <0x00 0xa7000000 0x00 0x100000>; 129 no-map; 130 }; 131 132 c66_1_memory_region: c66-memory@a7100000 { 133 compatible = "shared-dma-pool"; 134 reg = <0x00 0xa7100000 0x00 0xf00000>; 135 no-map; 136 }; 137 138 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 139 compatible = "shared-dma-pool"; 140 reg = <0x00 0xa8000000 0x00 0x100000>; 141 no-map; 142 }; 143 144 c71_0_memory_region: c71-memory@a8100000 { 145 compatible = "shared-dma-pool"; 146 reg = <0x00 0xa8100000 0x00 0xf00000>; 147 no-map; 148 }; 149 150 rtos_ipc_memory_region: ipc-memories@aa000000 { 151 reg = <0x00 0xaa000000 0x00 0x01c00000>; 152 alignment = <0x1000>; 153 no-map; 154 }; 155 }; 156 157 vusb_main: fixedregulator-vusb-main5v0 { 158 /* USB MAIN INPUT 5V DC */ 159 compatible = "regulator-fixed"; 160 regulator-name = "vusb-main5v0"; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 regulator-always-on; 164 regulator-boot-on; 165 }; 166 167 vsys_3v3: fixedregulator-vsys3v3 { 168 /* Output of LM5141 */ 169 compatible = "regulator-fixed"; 170 regulator-name = "vsys_3v3"; 171 regulator-min-microvolt = <3300000>; 172 regulator-max-microvolt = <3300000>; 173 vin-supply = <&vusb_main>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vdd_mmc1: fixedregulator-sd { 179 compatible = "regulator-fixed"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 182 regulator-name = "vdd_mmc1"; 183 regulator-min-microvolt = <3300000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 enable-active-high; 187 vin-supply = <&vsys_3v3>; 188 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 189 }; 190 191 vdd_sd_dv_alt: gpio-regulator-tps659411 { 192 compatible = "regulator-gpio"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 195 regulator-name = "tps659411"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <3300000>; 198 regulator-boot-on; 199 vin-supply = <&vsys_3v3>; 200 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 201 states = <1800000 0x0>, 202 <3300000 0x1>; 203 }; 204 205 dp_pwr_3v3: fixedregulator-dp-prw { 206 compatible = "regulator-fixed"; 207 regulator-name = "dp-pwr"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&dp_pwr_en_pins_default>; 212 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 213 enable-active-high; 214 }; 215 216}; 217 218&main_pmx0 { 219 main_mmc1_pins_default: main-mmc1-pins-default { 220 pinctrl-single,pins = < 221 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 222 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 223 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 224 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 225 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 226 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 227 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 228 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 229 >; 230 }; 231 232 main_uart0_pins_default: main-uart0-pins-default { 233 pinctrl-single,pins = < 234 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 235 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 236 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 237 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 238 >; 239 }; 240 241 main_i2c0_pins_default: main-i2c0-pins-default { 242 pinctrl-single,pins = < 243 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 244 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 245 >; 246 }; 247 248 main_i2c1_pins_default: main-i2c1-pins-default { 249 pinctrl-single,pins = < 250 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 251 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 252 >; 253 }; 254 255 main_i2c3_pins_default: main-i2c3-pins-default { 256 pinctrl-single,pins = < 257 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 258 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 259 >; 260 }; 261 262 main_usbss0_pins_default: main-usbss0-pins-default { 263 pinctrl-single,pins = < 264 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 265 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 266 >; 267 }; 268 269 main_usbss1_pins_default: main-usbss1-pins-default { 270 pinctrl-single,pins = < 271 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 272 >; 273 }; 274 275 dp0_pins_default: dp0-pins-default { 276 pinctrl-single,pins = < 277 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 278 >; 279 }; 280 281 dp_pwr_en_pins_default: dp-pwr-en-pins-default { 282 pinctrl-single,pins = < 283 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 284 >; 285 }; 286 287 dss_vout0_pins_default: dss-vout0-pins-default { 288 pinctrl-single,pins = < 289 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 290 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 291 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 292 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 293 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 294 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 295 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 296 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 297 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 298 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 299 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 300 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 301 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 302 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 303 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 304 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 305 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 306 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 307 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 308 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 309 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 310 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 311 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 312 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 313 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 314 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 315 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 316 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 317 >; 318 }; 319 320 /* Reset for M.2 E Key slot on PCIe0 */ 321 ekey_reset_pins_default: ekey-reset-pns-pins-default { 322 pinctrl-single,pins = < 323 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 324 >; 325 }; 326}; 327 328&wkup_pmx0 { 329 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 330 pinctrl-single,pins = < 331 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 332 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 333 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 334 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 335 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 336 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 337 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 338 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 339 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 340 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 341 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 342 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 343 >; 344 }; 345 346 mcu_mdio_pins_default: mcu-mdio1-pins-default { 347 pinctrl-single,pins = < 348 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 349 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 350 >; 351 }; 352 353 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 354 pinctrl-single,pins = < 355 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 356 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 357 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 358 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 359 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 360 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 361 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 362 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 363 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 364 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 365 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 366 >; 367 }; 368 369 vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { 370 pinctrl-single,pins = < 371 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 372 >; 373 }; 374 375 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 376 pinctrl-single,pins = < 377 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 378 >; 379 }; 380 381 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 382 pinctrl-single,pins = < 383 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 384 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 385 >; 386 }; 387 388 /* Reset for M.2 M Key slot on PCIe1 */ 389 mkey_reset_pins_default: mkey-reset-pns-pins-default { 390 pinctrl-single,pins = < 391 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 392 >; 393 }; 394}; 395 396&wkup_uart0 { 397 /* Wakeup UART is used by System firmware */ 398 status = "reserved"; 399}; 400 401&main_uart0 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&main_uart0_pins_default>; 404 /* Shared with ATF on this platform */ 405 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 406}; 407 408&main_uart2 { 409 /* Brought out on RPi header */ 410 status = "disabled"; 411}; 412 413&main_uart3 { 414 /* UART not brought out */ 415 status = "disabled"; 416}; 417 418&main_uart5 { 419 /* UART not brought out */ 420 status = "disabled"; 421}; 422 423&main_uart6 { 424 /* UART not brought out */ 425 status = "disabled"; 426}; 427 428&main_uart7 { 429 /* UART not brought out */ 430 status = "disabled"; 431}; 432 433&main_uart8 { 434 /* UART not brought out */ 435 status = "disabled"; 436}; 437 438&main_uart9 { 439 /* Brought out on M.2 E Key */ 440 status = "disabled"; 441}; 442 443&main_sdhci0 { 444 /* Unused */ 445 status = "disabled"; 446}; 447 448&main_sdhci1 { 449 /* SD Card */ 450 vmmc-supply = <&vdd_mmc1>; 451 vqmmc-supply = <&vdd_sd_dv_alt>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&main_mmc1_pins_default>; 454 ti,driver-strength-ohm = <50>; 455 disable-wp; 456}; 457 458&main_sdhci2 { 459 /* Unused */ 460 status = "disabled"; 461}; 462 463&ospi0 { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 466 467 flash@0 { 468 compatible = "jedec,spi-nor"; 469 reg = <0x0>; 470 spi-tx-bus-width = <8>; 471 spi-rx-bus-width = <8>; 472 spi-max-frequency = <25000000>; 473 cdns,tshsl-ns = <60>; 474 cdns,tsd2d-ns = <60>; 475 cdns,tchsh-ns = <60>; 476 cdns,tslch-ns = <60>; 477 cdns,read-delay = <4>; 478 #address-cells = <1>; 479 #size-cells = <1>; 480 }; 481}; 482 483&ospi1 { 484 /* Unused */ 485 status = "disabled"; 486}; 487 488&main_i2c0 { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&main_i2c0_pins_default>; 491 clock-frequency = <400000>; 492 493 i2c-mux@71 { 494 compatible = "nxp,pca9543"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <0x71>; 498 499 /* PCIe1 M.2 M Key I2C */ 500 i2c@0 { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0>; 504 }; 505 506 /* PCIe0 M.2 E Key I2C */ 507 i2c@1 { 508 #address-cells = <1>; 509 #size-cells = <0>; 510 reg = <1>; 511 }; 512 }; 513}; 514 515&main_i2c1 { 516 pinctrl-names = "default"; 517 pinctrl-0 = <&main_i2c1_pins_default>; 518 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 519 clock-frequency = <100000>; 520}; 521 522&main_i2c2 { 523 /* Unused */ 524 status = "disabled"; 525}; 526 527&main_i2c3 { 528 pinctrl-names = "default"; 529 pinctrl-0 = <&main_i2c3_pins_default>; 530 clock-frequency = <400000>; 531 532 i2c-mux@70 { 533 compatible = "nxp,pca9543"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 reg = <0x70>; 537 538 /* CSI0 I2C */ 539 i2c@0 { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 reg = <0>; 543 }; 544 545 /* CSI1 I2C */ 546 i2c@1 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 reg = <1>; 550 }; 551 }; 552}; 553 554&main_i2c4 { 555 /* Unused */ 556 status = "disabled"; 557}; 558 559&main_i2c5 { 560 /* Brought out on RPi Header */ 561 status = "disabled"; 562}; 563 564&main_i2c6 { 565 /* Unused */ 566 status = "disabled"; 567}; 568 569&main_gpio2 { 570 status = "disabled"; 571}; 572 573&main_gpio3 { 574 status = "disabled"; 575}; 576 577&main_gpio4 { 578 status = "disabled"; 579}; 580 581&main_gpio5 { 582 status = "disabled"; 583}; 584 585&main_gpio6 { 586 status = "disabled"; 587}; 588 589&main_gpio7 { 590 status = "disabled"; 591}; 592 593&wkup_gpio1 { 594 status = "disabled"; 595}; 596 597&main_r5fss0_core0{ 598 firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; 599}; 600 601&usb_serdes_mux { 602 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 603}; 604 605&serdes_ln_ctrl { 606 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 607 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 608 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 609 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 610 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 611 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 612}; 613 614&serdes_wiz3 { 615 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 616 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 617}; 618 619&serdes3 { 620 serdes3_usb_link: phy@0 { 621 reg = <0>; 622 cdns,num-lanes = <2>; 623 #phy-cells = <0>; 624 cdns,phy-type = <PHY_TYPE_USB3>; 625 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 626 }; 627}; 628 629&usbss0 { 630 pinctrl-names = "default"; 631 pinctrl-0 = <&main_usbss0_pins_default>; 632 ti,vbus-divider; 633}; 634 635&usb0 { 636 dr_mode = "otg"; 637 maximum-speed = "super-speed"; 638 phys = <&serdes3_usb_link>; 639 phy-names = "cdns3,usb3-phy"; 640}; 641 642&serdes2 { 643 serdes2_usb_link: phy@1 { 644 reg = <1>; 645 cdns,num-lanes = <1>; 646 #phy-cells = <0>; 647 cdns,phy-type = <PHY_TYPE_USB3>; 648 resets = <&serdes_wiz2 2>; 649 }; 650}; 651 652&usbss1 { 653 pinctrl-names = "default"; 654 pinctrl-0 = <&main_usbss1_pins_default>; 655 ti,vbus-divider; 656}; 657 658&usb1 { 659 dr_mode = "host"; 660 maximum-speed = "super-speed"; 661 phys = <&serdes2_usb_link>; 662 phy-names = "cdns3,usb3-phy"; 663}; 664 665&tscadc0 { 666 /* Unused */ 667 status = "disabled"; 668}; 669 670&tscadc1 { 671 /* Unused */ 672 status = "disabled"; 673}; 674 675&mcu_cpsw { 676 pinctrl-names = "default"; 677 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 678}; 679 680&davinci_mdio { 681 phy0: ethernet-phy@0 { 682 reg = <0>; 683 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 684 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 685 }; 686}; 687 688&cpsw_port1 { 689 phy-mode = "rgmii-rxid"; 690 phy-handle = <&phy0>; 691}; 692 693&dss { 694 pinctrl-names = "default"; 695 pinctrl-0 = <&dss_vout0_pins_default>; 696 697 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 698 <&k3_clks 152 4>, /* VP 2 pixel clock */ 699 <&k3_clks 152 9>, /* VP 3 pixel clock */ 700 <&k3_clks 152 13>; /* VP 4 pixel clock */ 701 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 702 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 703 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 704 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 705}; 706 707&mcasp0 { 708 /* Unused */ 709 status = "disabled"; 710}; 711 712&mcasp1 { 713 /* Unused */ 714 status = "disabled"; 715}; 716 717&mcasp2 { 718 /* Unused */ 719 status = "disabled"; 720}; 721 722&mcasp3 { 723 /* Unused */ 724 status = "disabled"; 725}; 726 727&mcasp4 { 728 /* Unused */ 729 status = "disabled"; 730}; 731 732&mcasp5 { 733 /* Unused */ 734 status = "disabled"; 735}; 736 737&mcasp6 { 738 /* Brought out on RPi header */ 739 status = "disabled"; 740}; 741 742&mcasp7 { 743 /* Unused */ 744 status = "disabled"; 745}; 746 747&mcasp8 { 748 /* Unused */ 749 status = "disabled"; 750}; 751 752&mcasp9 { 753 /* Unused */ 754 status = "disabled"; 755}; 756 757&mcasp10 { 758 /* Unused */ 759 status = "disabled"; 760}; 761 762&mcasp11 { 763 /* Brought out on M.2 E Key */ 764 status = "disabled"; 765}; 766 767&serdes0 { 768 serdes0_pcie_link: phy@0 { 769 reg = <0>; 770 cdns,num-lanes = <1>; 771 #phy-cells = <0>; 772 cdns,phy-type = <PHY_TYPE_PCIE>; 773 resets = <&serdes_wiz0 1>; 774 }; 775}; 776 777&serdes1 { 778 serdes1_pcie_link: phy@0 { 779 reg = <0>; 780 cdns,num-lanes = <2>; 781 #phy-cells = <0>; 782 cdns,phy-type = <PHY_TYPE_PCIE>; 783 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 784 }; 785}; 786 787&pcie0_rc { 788 pinctrl-names = "default"; 789 pinctrl-0 = <&ekey_reset_pins_default>; 790 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 791 792 phys = <&serdes0_pcie_link>; 793 phy-names = "pcie-phy"; 794 num-lanes = <1>; 795}; 796 797&pcie1_rc { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&mkey_reset_pins_default>; 800 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 801 802 phys = <&serdes1_pcie_link>; 803 phy-names = "pcie-phy"; 804 num-lanes = <2>; 805}; 806 807&pcie2_rc { 808 /* Unused */ 809 status = "disabled"; 810}; 811 812&pcie0_ep { 813 status = "disabled"; 814 phys = <&serdes0_pcie_link>; 815 phy-names = "pcie-phy"; 816 num-lanes = <1>; 817}; 818 819&pcie1_ep { 820 status = "disabled"; 821 phys = <&serdes1_pcie_link>; 822 phy-names = "pcie-phy"; 823 num-lanes = <2>; 824}; 825 826&pcie2_ep { 827 /* Unused */ 828 status = "disabled"; 829}; 830 831&pcie3_rc { 832 /* Unused */ 833 status = "disabled"; 834}; 835 836&pcie3_ep { 837 /* Unused */ 838 status = "disabled"; 839}; 840 841&dss { 842 status = "disabled"; 843}; 844 845&icssg0_mdio { 846 status = "disabled"; 847}; 848 849&icssg1_mdio { 850 status = "disabled"; 851}; 852 853&ufs_wrapper { 854 status = "disabled"; 855}; 856 857&mailbox0_cluster0 { 858 interrupts = <436>; 859 860 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 861 ti,mbox-rx = <0 0 0>; 862 ti,mbox-tx = <1 0 0>; 863 }; 864 865 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 866 ti,mbox-rx = <2 0 0>; 867 ti,mbox-tx = <3 0 0>; 868 }; 869}; 870 871&mailbox0_cluster1 { 872 interrupts = <432>; 873 874 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 875 ti,mbox-rx = <0 0 0>; 876 ti,mbox-tx = <1 0 0>; 877 }; 878 879 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 880 ti,mbox-rx = <2 0 0>; 881 ti,mbox-tx = <3 0 0>; 882 }; 883}; 884 885&mailbox0_cluster2 { 886 interrupts = <428>; 887 888 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 889 ti,mbox-rx = <0 0 0>; 890 ti,mbox-tx = <1 0 0>; 891 }; 892 893 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 894 ti,mbox-rx = <2 0 0>; 895 ti,mbox-tx = <3 0 0>; 896 }; 897}; 898 899&mailbox0_cluster3 { 900 interrupts = <424>; 901 902 mbox_c66_0: mbox-c66-0 { 903 ti,mbox-rx = <0 0 0>; 904 ti,mbox-tx = <1 0 0>; 905 }; 906 907 mbox_c66_1: mbox-c66-1 { 908 ti,mbox-rx = <2 0 0>; 909 ti,mbox-tx = <3 0 0>; 910 }; 911}; 912 913&mailbox0_cluster4 { 914 interrupts = <420>; 915 916 mbox_c71_0: mbox-c71-0 { 917 ti,mbox-rx = <0 0 0>; 918 ti,mbox-tx = <1 0 0>; 919 }; 920}; 921 922&mailbox0_cluster5 { 923 status = "disabled"; 924}; 925 926&mailbox0_cluster6 { 927 status = "disabled"; 928}; 929 930&mailbox0_cluster7 { 931 status = "disabled"; 932}; 933 934&mailbox0_cluster8 { 935 status = "disabled"; 936}; 937 938&mailbox0_cluster9 { 939 status = "disabled"; 940}; 941 942&mailbox0_cluster10 { 943 status = "disabled"; 944}; 945 946&mailbox0_cluster11 { 947 status = "disabled"; 948}; 949 950&mcu_r5fss0_core0 { 951 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 952 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 953 <&mcu_r5fss0_core0_memory_region>; 954}; 955 956&mcu_r5fss0_core1 { 957 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 958 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 959 <&mcu_r5fss0_core1_memory_region>; 960}; 961 962&main_r5fss0_core0 { 963 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 964 memory-region = <&main_r5fss0_core0_dma_memory_region>, 965 <&main_r5fss0_core0_memory_region>; 966}; 967 968&main_r5fss0_core1 { 969 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 970 memory-region = <&main_r5fss0_core1_dma_memory_region>, 971 <&main_r5fss0_core1_memory_region>; 972}; 973 974&main_r5fss1_core0 { 975 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 976 memory-region = <&main_r5fss1_core0_dma_memory_region>, 977 <&main_r5fss1_core0_memory_region>; 978}; 979 980&main_r5fss1_core1 { 981 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 982 memory-region = <&main_r5fss1_core1_dma_memory_region>, 983 <&main_r5fss1_core1_memory_region>; 984}; 985 986&c66_0 { 987 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 988 memory-region = <&c66_0_dma_memory_region>, 989 <&c66_0_memory_region>; 990}; 991 992&c66_1 { 993 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 994 memory-region = <&c66_1_dma_memory_region>, 995 <&c66_1_memory_region>; 996}; 997 998&c71_0 { 999 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1000 memory-region = <&c71_0_dma_memory_region>, 1001 <&c71_0_memory_region>; 1002}; 1003