1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 4G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 28 <0x00000008 0x80000000 0x00000000 0x80000000>; 29 }; 30 31 reserved_memory: reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa4000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa4100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa5000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa5100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0x00 0xa6000000 0x00 0x100000>; 117 no-map; 118 }; 119 120 c66_0_memory_region: c66-memory@a6100000 { 121 compatible = "shared-dma-pool"; 122 reg = <0x00 0xa6100000 0x00 0xf00000>; 123 no-map; 124 }; 125 126 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 127 compatible = "shared-dma-pool"; 128 reg = <0x00 0xa7000000 0x00 0x100000>; 129 no-map; 130 }; 131 132 c66_1_memory_region: c66-memory@a7100000 { 133 compatible = "shared-dma-pool"; 134 reg = <0x00 0xa7100000 0x00 0xf00000>; 135 no-map; 136 }; 137 138 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 139 compatible = "shared-dma-pool"; 140 reg = <0x00 0xa8000000 0x00 0x100000>; 141 no-map; 142 }; 143 144 c71_0_memory_region: c71-memory@a8100000 { 145 compatible = "shared-dma-pool"; 146 reg = <0x00 0xa8100000 0x00 0xf00000>; 147 no-map; 148 }; 149 150 rtos_ipc_memory_region: ipc-memories@aa000000 { 151 reg = <0x00 0xaa000000 0x00 0x01c00000>; 152 alignment = <0x1000>; 153 no-map; 154 }; 155 }; 156 157 vusb_main: fixedregulator-vusb-main5v0 { 158 /* USB MAIN INPUT 5V DC */ 159 compatible = "regulator-fixed"; 160 regulator-name = "vusb-main5v0"; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 regulator-always-on; 164 regulator-boot-on; 165 }; 166 167 vsys_3v3: fixedregulator-vsys3v3 { 168 /* Output of LM5141 */ 169 compatible = "regulator-fixed"; 170 regulator-name = "vsys_3v3"; 171 regulator-min-microvolt = <3300000>; 172 regulator-max-microvolt = <3300000>; 173 vin-supply = <&vusb_main>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vdd_mmc1: fixedregulator-sd { 179 compatible = "regulator-fixed"; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 182 regulator-name = "vdd_mmc1"; 183 regulator-min-microvolt = <3300000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 enable-active-high; 187 vin-supply = <&vsys_3v3>; 188 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 189 }; 190 191 vdd_sd_dv_alt: gpio-regulator-tps659411 { 192 compatible = "regulator-gpio"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 195 regulator-name = "tps659411"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <3300000>; 198 regulator-boot-on; 199 vin-supply = <&vsys_3v3>; 200 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 201 states = <1800000 0x0>, 202 <3300000 0x1>; 203 }; 204 205 dp_pwr_3v3: fixedregulator-dp-prw { 206 compatible = "regulator-fixed"; 207 regulator-name = "dp-pwr"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&dp_pwr_en_pins_default>; 212 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 213 enable-active-high; 214 }; 215 216}; 217 218&main_pmx0 { 219 main_mmc1_pins_default: main-mmc1-pins-default { 220 pinctrl-single,pins = < 221 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 222 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 223 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 224 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 225 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 226 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 227 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 228 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 229 >; 230 }; 231 232 main_uart0_pins_default: main-uart0-pins-default { 233 pinctrl-single,pins = < 234 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 235 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 236 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 237 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 238 >; 239 }; 240 241 main_i2c0_pins_default: main-i2c0-pins-default { 242 pinctrl-single,pins = < 243 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 244 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 245 >; 246 }; 247 248 main_i2c1_pins_default: main-i2c1-pins-default { 249 pinctrl-single,pins = < 250 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 251 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 252 >; 253 }; 254 255 main_i2c3_pins_default: main-i2c3-pins-default { 256 pinctrl-single,pins = < 257 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 258 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 259 >; 260 }; 261 262 main_usbss0_pins_default: main-usbss0-pins-default { 263 pinctrl-single,pins = < 264 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 265 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 266 >; 267 }; 268 269 main_usbss1_pins_default: main-usbss1-pins-default { 270 pinctrl-single,pins = < 271 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 272 >; 273 }; 274 275 dp0_pins_default: dp0-pins-default { 276 pinctrl-single,pins = < 277 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 278 >; 279 }; 280 281 dp_pwr_en_pins_default: dp-pwr-en-pins-default { 282 pinctrl-single,pins = < 283 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 284 >; 285 }; 286 287 dss_vout0_pins_default: dss-vout0-pins-default { 288 pinctrl-single,pins = < 289 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 290 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 291 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 292 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 293 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 294 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 295 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 296 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 297 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 298 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 299 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 300 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 301 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 302 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 303 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 304 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 305 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 306 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 307 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 308 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 309 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 310 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 311 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 312 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 313 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 314 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 315 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 316 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 317 >; 318 }; 319 320 /* Reset for M.2 E Key slot on PCIe0 */ 321 ekey_reset_pins_default: ekey-reset-pns-pins-default { 322 pinctrl-single,pins = < 323 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 324 >; 325 }; 326}; 327 328&wkup_pmx0 { 329 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 330 pinctrl-single,pins = < 331 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 332 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 333 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 334 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 335 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 336 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 337 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 338 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 339 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 340 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 341 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 342 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 343 >; 344 }; 345 346 mcu_mdio_pins_default: mcu-mdio1-pins-default { 347 pinctrl-single,pins = < 348 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 349 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 350 >; 351 }; 352 353 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 354 pinctrl-single,pins = < 355 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 356 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 357 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 358 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 359 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 360 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 361 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 362 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 363 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 364 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 365 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 366 >; 367 }; 368 369 vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { 370 pinctrl-single,pins = < 371 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 372 >; 373 }; 374 375 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 376 pinctrl-single,pins = < 377 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 378 >; 379 }; 380 381 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 382 pinctrl-single,pins = < 383 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 384 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 385 >; 386 }; 387 388 /* Reset for M.2 M Key slot on PCIe1 */ 389 mkey_reset_pins_default: mkey-reset-pns-pins-default { 390 pinctrl-single,pins = < 391 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 392 >; 393 }; 394}; 395 396&wkup_uart0 { 397 /* Wakeup UART is used by System firmware */ 398 status = "reserved"; 399}; 400 401&main_uart0 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&main_uart0_pins_default>; 404 /* Shared with ATF on this platform */ 405 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 406}; 407 408&main_uart2 { 409 /* Brought out on RPi header */ 410 status = "disabled"; 411}; 412 413&main_uart3 { 414 /* UART not brought out */ 415 status = "disabled"; 416}; 417 418&main_uart5 { 419 /* UART not brought out */ 420 status = "disabled"; 421}; 422 423&main_uart6 { 424 /* UART not brought out */ 425 status = "disabled"; 426}; 427 428&main_uart7 { 429 /* UART not brought out */ 430 status = "disabled"; 431}; 432 433&main_uart8 { 434 /* UART not brought out */ 435 status = "disabled"; 436}; 437 438&main_uart9 { 439 /* Brought out on M.2 E Key */ 440 status = "disabled"; 441}; 442 443&main_sdhci0 { 444 /* Unused */ 445 status = "disabled"; 446}; 447 448&main_sdhci1 { 449 /* SD Card */ 450 vmmc-supply = <&vdd_mmc1>; 451 vqmmc-supply = <&vdd_sd_dv_alt>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&main_mmc1_pins_default>; 454 ti,driver-strength-ohm = <50>; 455 disable-wp; 456}; 457 458&main_sdhci2 { 459 /* Unused */ 460 status = "disabled"; 461}; 462 463&ospi0 { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 466 467 flash@0 { 468 compatible = "jedec,spi-nor"; 469 reg = <0x0>; 470 spi-tx-bus-width = <8>; 471 spi-rx-bus-width = <8>; 472 spi-max-frequency = <25000000>; 473 cdns,tshsl-ns = <60>; 474 cdns,tsd2d-ns = <60>; 475 cdns,tchsh-ns = <60>; 476 cdns,tslch-ns = <60>; 477 cdns,read-delay = <4>; 478 }; 479}; 480 481&ospi1 { 482 /* Unused */ 483 status = "disabled"; 484}; 485 486&main_i2c0 { 487 pinctrl-names = "default"; 488 pinctrl-0 = <&main_i2c0_pins_default>; 489 clock-frequency = <400000>; 490 491 i2c-mux@71 { 492 compatible = "nxp,pca9543"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <0x71>; 496 497 /* PCIe1 M.2 M Key I2C */ 498 i2c@0 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <0>; 502 }; 503 504 /* PCIe0 M.2 E Key I2C */ 505 i2c@1 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <1>; 509 }; 510 }; 511}; 512 513&main_i2c1 { 514 pinctrl-names = "default"; 515 pinctrl-0 = <&main_i2c1_pins_default>; 516 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 517 clock-frequency = <100000>; 518}; 519 520&main_i2c2 { 521 /* Unused */ 522 status = "disabled"; 523}; 524 525&main_i2c3 { 526 pinctrl-names = "default"; 527 pinctrl-0 = <&main_i2c3_pins_default>; 528 clock-frequency = <400000>; 529 530 i2c-mux@70 { 531 compatible = "nxp,pca9543"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 reg = <0x70>; 535 536 /* CSI0 I2C */ 537 i2c@0 { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 reg = <0>; 541 }; 542 543 /* CSI1 I2C */ 544 i2c@1 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <1>; 548 }; 549 }; 550}; 551 552&main_i2c4 { 553 /* Unused */ 554 status = "disabled"; 555}; 556 557&main_i2c5 { 558 /* Brought out on RPi Header */ 559 status = "disabled"; 560}; 561 562&main_i2c6 { 563 /* Unused */ 564 status = "disabled"; 565}; 566 567&main_gpio2 { 568 status = "disabled"; 569}; 570 571&main_gpio3 { 572 status = "disabled"; 573}; 574 575&main_gpio4 { 576 status = "disabled"; 577}; 578 579&main_gpio5 { 580 status = "disabled"; 581}; 582 583&main_gpio6 { 584 status = "disabled"; 585}; 586 587&main_gpio7 { 588 status = "disabled"; 589}; 590 591&wkup_gpio1 { 592 status = "disabled"; 593}; 594 595&main_r5fss0_core0{ 596 firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; 597}; 598 599&usb_serdes_mux { 600 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 601}; 602 603&serdes_ln_ctrl { 604 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 605 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 606 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 607 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 608 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 609 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 610}; 611 612&serdes_wiz3 { 613 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 614 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 615}; 616 617&serdes3 { 618 serdes3_usb_link: phy@0 { 619 reg = <0>; 620 cdns,num-lanes = <2>; 621 #phy-cells = <0>; 622 cdns,phy-type = <PHY_TYPE_USB3>; 623 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 624 }; 625}; 626 627&usbss0 { 628 pinctrl-names = "default"; 629 pinctrl-0 = <&main_usbss0_pins_default>; 630 ti,vbus-divider; 631}; 632 633&usb0 { 634 dr_mode = "otg"; 635 maximum-speed = "super-speed"; 636 phys = <&serdes3_usb_link>; 637 phy-names = "cdns3,usb3-phy"; 638}; 639 640&serdes2 { 641 serdes2_usb_link: phy@1 { 642 reg = <1>; 643 cdns,num-lanes = <1>; 644 #phy-cells = <0>; 645 cdns,phy-type = <PHY_TYPE_USB3>; 646 resets = <&serdes_wiz2 2>; 647 }; 648}; 649 650&usbss1 { 651 pinctrl-names = "default"; 652 pinctrl-0 = <&main_usbss1_pins_default>; 653 ti,vbus-divider; 654}; 655 656&usb1 { 657 dr_mode = "host"; 658 maximum-speed = "super-speed"; 659 phys = <&serdes2_usb_link>; 660 phy-names = "cdns3,usb3-phy"; 661}; 662 663&tscadc0 { 664 /* Unused */ 665 status = "disabled"; 666}; 667 668&tscadc1 { 669 /* Unused */ 670 status = "disabled"; 671}; 672 673&mcu_cpsw { 674 pinctrl-names = "default"; 675 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 676}; 677 678&davinci_mdio { 679 phy0: ethernet-phy@0 { 680 reg = <0>; 681 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 682 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 683 }; 684}; 685 686&cpsw_port1 { 687 phy-mode = "rgmii-rxid"; 688 phy-handle = <&phy0>; 689}; 690 691&dss { 692 pinctrl-names = "default"; 693 pinctrl-0 = <&dss_vout0_pins_default>; 694 695 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 696 <&k3_clks 152 4>, /* VP 2 pixel clock */ 697 <&k3_clks 152 9>, /* VP 3 pixel clock */ 698 <&k3_clks 152 13>; /* VP 4 pixel clock */ 699 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 700 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 701 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 702 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 703}; 704 705&mcasp0 { 706 /* Unused */ 707 status = "disabled"; 708}; 709 710&mcasp1 { 711 /* Unused */ 712 status = "disabled"; 713}; 714 715&mcasp2 { 716 /* Unused */ 717 status = "disabled"; 718}; 719 720&mcasp3 { 721 /* Unused */ 722 status = "disabled"; 723}; 724 725&mcasp4 { 726 /* Unused */ 727 status = "disabled"; 728}; 729 730&mcasp5 { 731 /* Unused */ 732 status = "disabled"; 733}; 734 735&mcasp6 { 736 /* Brought out on RPi header */ 737 status = "disabled"; 738}; 739 740&mcasp7 { 741 /* Unused */ 742 status = "disabled"; 743}; 744 745&mcasp8 { 746 /* Unused */ 747 status = "disabled"; 748}; 749 750&mcasp9 { 751 /* Unused */ 752 status = "disabled"; 753}; 754 755&mcasp10 { 756 /* Unused */ 757 status = "disabled"; 758}; 759 760&mcasp11 { 761 /* Brought out on M.2 E Key */ 762 status = "disabled"; 763}; 764 765&serdes0 { 766 serdes0_pcie_link: phy@0 { 767 reg = <0>; 768 cdns,num-lanes = <1>; 769 #phy-cells = <0>; 770 cdns,phy-type = <PHY_TYPE_PCIE>; 771 resets = <&serdes_wiz0 1>; 772 }; 773}; 774 775&serdes1 { 776 serdes1_pcie_link: phy@0 { 777 reg = <0>; 778 cdns,num-lanes = <2>; 779 #phy-cells = <0>; 780 cdns,phy-type = <PHY_TYPE_PCIE>; 781 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 782 }; 783}; 784 785&pcie0_rc { 786 pinctrl-names = "default"; 787 pinctrl-0 = <&ekey_reset_pins_default>; 788 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 789 790 phys = <&serdes0_pcie_link>; 791 phy-names = "pcie-phy"; 792 num-lanes = <1>; 793}; 794 795&pcie1_rc { 796 pinctrl-names = "default"; 797 pinctrl-0 = <&mkey_reset_pins_default>; 798 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 799 800 phys = <&serdes1_pcie_link>; 801 phy-names = "pcie-phy"; 802 num-lanes = <2>; 803}; 804 805&pcie2_rc { 806 /* Unused */ 807 status = "disabled"; 808}; 809 810&pcie0_ep { 811 status = "disabled"; 812 phys = <&serdes0_pcie_link>; 813 phy-names = "pcie-phy"; 814 num-lanes = <1>; 815}; 816 817&pcie1_ep { 818 status = "disabled"; 819 phys = <&serdes1_pcie_link>; 820 phy-names = "pcie-phy"; 821 num-lanes = <2>; 822}; 823 824&pcie2_ep { 825 /* Unused */ 826 status = "disabled"; 827}; 828 829&pcie3_rc { 830 /* Unused */ 831 status = "disabled"; 832}; 833 834&pcie3_ep { 835 /* Unused */ 836 status = "disabled"; 837}; 838 839&dss { 840 status = "disabled"; 841}; 842 843&icssg0_mdio { 844 status = "disabled"; 845}; 846 847&icssg1_mdio { 848 status = "disabled"; 849}; 850 851&ufs_wrapper { 852 status = "disabled"; 853}; 854 855&mailbox0_cluster0 { 856 interrupts = <436>; 857 858 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 859 ti,mbox-rx = <0 0 0>; 860 ti,mbox-tx = <1 0 0>; 861 }; 862 863 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 864 ti,mbox-rx = <2 0 0>; 865 ti,mbox-tx = <3 0 0>; 866 }; 867}; 868 869&mailbox0_cluster1 { 870 interrupts = <432>; 871 872 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 873 ti,mbox-rx = <0 0 0>; 874 ti,mbox-tx = <1 0 0>; 875 }; 876 877 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 878 ti,mbox-rx = <2 0 0>; 879 ti,mbox-tx = <3 0 0>; 880 }; 881}; 882 883&mailbox0_cluster2 { 884 interrupts = <428>; 885 886 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 887 ti,mbox-rx = <0 0 0>; 888 ti,mbox-tx = <1 0 0>; 889 }; 890 891 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 892 ti,mbox-rx = <2 0 0>; 893 ti,mbox-tx = <3 0 0>; 894 }; 895}; 896 897&mailbox0_cluster3 { 898 interrupts = <424>; 899 900 mbox_c66_0: mbox-c66-0 { 901 ti,mbox-rx = <0 0 0>; 902 ti,mbox-tx = <1 0 0>; 903 }; 904 905 mbox_c66_1: mbox-c66-1 { 906 ti,mbox-rx = <2 0 0>; 907 ti,mbox-tx = <3 0 0>; 908 }; 909}; 910 911&mailbox0_cluster4 { 912 interrupts = <420>; 913 914 mbox_c71_0: mbox-c71-0 { 915 ti,mbox-rx = <0 0 0>; 916 ti,mbox-tx = <1 0 0>; 917 }; 918}; 919 920&mailbox0_cluster5 { 921 status = "disabled"; 922}; 923 924&mailbox0_cluster6 { 925 status = "disabled"; 926}; 927 928&mailbox0_cluster7 { 929 status = "disabled"; 930}; 931 932&mailbox0_cluster8 { 933 status = "disabled"; 934}; 935 936&mailbox0_cluster9 { 937 status = "disabled"; 938}; 939 940&mailbox0_cluster10 { 941 status = "disabled"; 942}; 943 944&mailbox0_cluster11 { 945 status = "disabled"; 946}; 947 948&mcu_r5fss0_core0 { 949 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 950 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 951 <&mcu_r5fss0_core0_memory_region>; 952}; 953 954&mcu_r5fss0_core1 { 955 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 956 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 957 <&mcu_r5fss0_core1_memory_region>; 958}; 959 960&main_r5fss0_core0 { 961 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 962 memory-region = <&main_r5fss0_core0_dma_memory_region>, 963 <&main_r5fss0_core0_memory_region>; 964}; 965 966&main_r5fss0_core1 { 967 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 968 memory-region = <&main_r5fss0_core1_dma_memory_region>, 969 <&main_r5fss0_core1_memory_region>; 970}; 971 972&main_r5fss1_core0 { 973 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 974 memory-region = <&main_r5fss1_core0_dma_memory_region>, 975 <&main_r5fss1_core0_memory_region>; 976}; 977 978&main_r5fss1_core1 { 979 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 980 memory-region = <&main_r5fss1_core1_dma_memory_region>, 981 <&main_r5fss1_core1_memory_region>; 982}; 983 984&c66_0 { 985 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 986 memory-region = <&c66_0_dma_memory_region>, 987 <&c66_0_memory_region>; 988}; 989 990&c66_1 { 991 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 992 memory-region = <&c66_1_dma_memory_region>, 993 <&c66_1_memory_region>; 994}; 995 996&c71_0 { 997 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 998 memory-region = <&c71_0_dma_memory_region>, 999 <&c71_0_memory_region>; 1000}; 1001