1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: dmsc@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clocks { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x0 0x43000014 0x0 0x4>; 54 }; 55 56 wkup_pmx0: pinmux@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x178>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 mcu_ram: sram@41c00000 { 66 compatible = "mmio-sram"; 67 reg = <0x00 0x41c00000 0x00 0x100000>; 68 ranges = <0x0 0x00 0x41c00000 0x100000>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 }; 72 73 wkup_uart0: serial@42300000 { 74 compatible = "ti,j721e-uart", "ti,am654-uart"; 75 reg = <0x00 0x42300000 0x00 0x100>; 76 reg-shift = <2>; 77 reg-io-width = <4>; 78 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 79 clock-frequency = <48000000>; 80 current-speed = <115200>; 81 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 82 clocks = <&k3_clks 287 0>; 83 clock-names = "fclk"; 84 }; 85 86 mcu_uart0: serial@40a00000 { 87 compatible = "ti,j721e-uart", "ti,am654-uart"; 88 reg = <0x00 0x40a00000 0x00 0x100>; 89 reg-shift = <2>; 90 reg-io-width = <4>; 91 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 92 clock-frequency = <96000000>; 93 current-speed = <115200>; 94 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 95 clocks = <&k3_clks 149 0>; 96 clock-names = "fclk"; 97 }; 98 99 wkup_gpio_intr: interrupt-controller2 { 100 compatible = "ti,sci-intr"; 101 ti,intr-trigger-type = <1>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 #interrupt-cells = <2>; 105 ti,sci = <&dmsc>; 106 ti,sci-dst-id = <14>; 107 ti,sci-rm-range-girq = <0x5>; 108 }; 109 110 wkup_gpio0: gpio@42110000 { 111 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 112 reg = <0x0 0x42110000 0x0 0x100>; 113 gpio-controller; 114 #gpio-cells = <2>; 115 interrupt-parent = <&wkup_gpio_intr>; 116 interrupts = <113 0>, <113 1>, <113 2>, 117 <113 3>, <113 4>, <113 5>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 ti,ngpio = <84>; 121 ti,davinci-gpio-unbanked = <0>; 122 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 123 clocks = <&k3_clks 113 0>; 124 clock-names = "gpio"; 125 }; 126 127 wkup_gpio1: gpio@42100000 { 128 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 129 reg = <0x0 0x42100000 0x0 0x100>; 130 gpio-controller; 131 #gpio-cells = <2>; 132 interrupt-parent = <&wkup_gpio_intr>; 133 interrupts = <114 0>, <114 1>, <114 2>, 134 <114 3>, <114 4>, <114 5>; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 ti,ngpio = <84>; 138 ti,davinci-gpio-unbanked = <0>; 139 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 140 clocks = <&k3_clks 114 0>; 141 clock-names = "gpio"; 142 }; 143 144 mcu_i2c0: i2c@40b00000 { 145 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 146 reg = <0x0 0x40b00000 0x0 0x100>; 147 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 clock-names = "fck"; 151 clocks = <&k3_clks 194 0>; 152 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 153 }; 154 155 mcu_i2c1: i2c@40b10000 { 156 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 157 reg = <0x0 0x40b10000 0x0 0x100>; 158 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 clock-names = "fck"; 162 clocks = <&k3_clks 195 0>; 163 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 164 }; 165 166 wkup_i2c0: i2c@42120000 { 167 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 168 reg = <0x0 0x42120000 0x0 0x100>; 169 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 clock-names = "fck"; 173 clocks = <&k3_clks 197 0>; 174 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 175 }; 176 177 fss: fss@47000000 { 178 compatible = "simple-bus"; 179 reg = <0x0 0x47000000 0x0 0x100>; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 ospi0: spi@47040000 { 185 compatible = "ti,am654-ospi"; 186 reg = <0x0 0x47040000 0x0 0x100>, 187 <0x5 0x00000000 0x1 0x0000000>; 188 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 189 cdns,fifo-depth = <256>; 190 cdns,fifo-width = <4>; 191 cdns,trigger-address = <0x0>; 192 clocks = <&k3_clks 103 0>; 193 assigned-clocks = <&k3_clks 103 0>; 194 assigned-clock-parents = <&k3_clks 103 2>; 195 assigned-clock-rates = <166666666>; 196 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 }; 200 201 ospi1: spi@47050000 { 202 compatible = "ti,am654-ospi"; 203 reg = <0x0 0x47050000 0x0 0x100>, 204 <0x7 0x00000000 0x1 0x00000000>; 205 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 206 cdns,fifo-depth = <256>; 207 cdns,fifo-width = <4>; 208 cdns,trigger-address = <0x0>; 209 clocks = <&k3_clks 104 0>; 210 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 }; 214 }; 215 216 tscadc0: tscadc@40200000 { 217 compatible = "ti,am3359-tscadc"; 218 reg = <0x0 0x40200000 0x0 0x1000>; 219 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 220 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 221 clocks = <&k3_clks 0 1>; 222 assigned-clocks = <&k3_clks 0 3>; 223 assigned-clock-rates = <60000000>; 224 clock-names = "adc_tsc_fck"; 225 dmas = <&main_udmap 0x7400>, 226 <&main_udmap 0x7401>; 227 dma-names = "fifo0", "fifo1"; 228 229 adc { 230 #io-channel-cells = <1>; 231 compatible = "ti,am3359-adc"; 232 }; 233 }; 234 235 tscadc1: tscadc@40210000 { 236 compatible = "ti,am3359-tscadc"; 237 reg = <0x0 0x40210000 0x0 0x1000>; 238 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 239 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 240 clocks = <&k3_clks 1 1>; 241 assigned-clocks = <&k3_clks 1 3>; 242 assigned-clock-rates = <60000000>; 243 clock-names = "adc_tsc_fck"; 244 dmas = <&main_udmap 0x7402>, 245 <&main_udmap 0x7403>; 246 dma-names = "fifo0", "fifo1"; 247 248 adc { 249 #io-channel-cells = <1>; 250 compatible = "ti,am3359-adc"; 251 }; 252 }; 253 254 mcu_navss { 255 compatible = "simple-mfd"; 256 #address-cells = <2>; 257 #size-cells = <2>; 258 ranges; 259 dma-coherent; 260 dma-ranges; 261 262 ti,sci-dev-id = <232>; 263 264 mcu_ringacc: ringacc@2b800000 { 265 compatible = "ti,am654-navss-ringacc"; 266 reg = <0x0 0x2b800000 0x0 0x400000>, 267 <0x0 0x2b000000 0x0 0x400000>, 268 <0x0 0x28590000 0x0 0x100>, 269 <0x0 0x2a500000 0x0 0x40000>; 270 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 271 ti,num-rings = <286>; 272 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 273 ti,sci = <&dmsc>; 274 ti,sci-dev-id = <235>; 275 msi-parent = <&main_udmass_inta>; 276 }; 277 278 mcu_udmap: dma-controller@285c0000 { 279 compatible = "ti,j721e-navss-mcu-udmap"; 280 reg = <0x0 0x285c0000 0x0 0x100>, 281 <0x0 0x2a800000 0x0 0x40000>, 282 <0x0 0x2aa00000 0x0 0x40000>; 283 reg-names = "gcfg", "rchanrt", "tchanrt"; 284 msi-parent = <&main_udmass_inta>; 285 #dma-cells = <1>; 286 287 ti,sci = <&dmsc>; 288 ti,sci-dev-id = <236>; 289 ti,ringacc = <&mcu_ringacc>; 290 291 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 292 <0x0f>; /* TX_HCHAN */ 293 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 294 <0x0b>; /* RX_HCHAN */ 295 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 296 }; 297 }; 298 299 mcu_cpsw: ethernet@46000000 { 300 compatible = "ti,j721e-cpsw-nuss"; 301 #address-cells = <2>; 302 #size-cells = <2>; 303 reg = <0x0 0x46000000 0x0 0x200000>; 304 reg-names = "cpsw_nuss"; 305 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 306 dma-coherent; 307 clocks = <&k3_clks 18 22>; 308 clock-names = "fck"; 309 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 310 311 dmas = <&mcu_udmap 0xf000>, 312 <&mcu_udmap 0xf001>, 313 <&mcu_udmap 0xf002>, 314 <&mcu_udmap 0xf003>, 315 <&mcu_udmap 0xf004>, 316 <&mcu_udmap 0xf005>, 317 <&mcu_udmap 0xf006>, 318 <&mcu_udmap 0xf007>, 319 <&mcu_udmap 0x7000>; 320 dma-names = "tx0", "tx1", "tx2", "tx3", 321 "tx4", "tx5", "tx6", "tx7", 322 "rx"; 323 324 ethernet-ports { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 328 cpsw_port1: port@1 { 329 reg = <1>; 330 ti,mac-only; 331 label = "port1"; 332 ti,syscon-efuse = <&mcu_conf 0x200>; 333 phys = <&phy_gmii_sel 1>; 334 }; 335 }; 336 337 davinci_mdio: mdio@f00 { 338 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 339 reg = <0x0 0xf00 0x0 0x100>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clocks = <&k3_clks 18 22>; 343 clock-names = "fck"; 344 bus_freq = <1000000>; 345 }; 346 347 cpts@3d000 { 348 compatible = "ti,am65-cpts"; 349 reg = <0x0 0x3d000 0x0 0x400>; 350 clocks = <&k3_clks 18 2>; 351 clock-names = "cpts"; 352 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 353 interrupt-names = "cpts"; 354 ti,cpts-ext-ts-inputs = <4>; 355 ti,cpts-periodic-outputs = <2>; 356 }; 357 }; 358}; 359