1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9	dmsc: system-controller@44083000 {
10		compatible = "ti,k2g-sci";
11		ti,host-id = <12>;
12
13		mbox-names = "rx", "tx";
14
15		mboxes= <&secure_proxy_main 11>,
16			<&secure_proxy_main 13>;
17
18		reg-names = "debug_messages";
19		reg = <0x00 0x44083000 0x0 0x1000>;
20
21		k3_pds: power-controller {
22			compatible = "ti,sci-pm-domain";
23			#power-domain-cells = <2>;
24		};
25
26		k3_clks: clock-controller {
27			compatible = "ti,k2g-sci-clk";
28			#clock-cells = <2>;
29		};
30
31		k3_reset: reset-controller {
32			compatible = "ti,sci-reset";
33			#reset-cells = <2>;
34		};
35	};
36
37	mcu_conf: syscon@40f00000 {
38		compatible = "syscon", "simple-mfd";
39		reg = <0x0 0x40f00000 0x0 0x20000>;
40		#address-cells = <1>;
41		#size-cells = <1>;
42		ranges = <0x0 0x0 0x40f00000 0x20000>;
43
44		phy_gmii_sel: phy@4040 {
45			compatible = "ti,am654-phy-gmii-sel";
46			reg = <0x4040 0x4>;
47			#phy-cells = <1>;
48		};
49	};
50
51	chipid@43000014 {
52		compatible = "ti,am654-chipid";
53		reg = <0x0 0x43000014 0x0 0x4>;
54	};
55
56	wkup_pmx0: pinctrl@4301c000 {
57		compatible = "pinctrl-single";
58		/* Proxy 0 addressing */
59		reg = <0x00 0x4301c000 0x00 0x178>;
60		#pinctrl-cells = <1>;
61		pinctrl-single,register-width = <32>;
62		pinctrl-single,function-mask = <0xffffffff>;
63	};
64
65	mcu_ram: sram@41c00000 {
66		compatible = "mmio-sram";
67		reg = <0x00 0x41c00000 0x00 0x100000>;
68		ranges = <0x0 0x00 0x41c00000 0x100000>;
69		#address-cells = <1>;
70		#size-cells = <1>;
71	};
72
73	wkup_uart0: serial@42300000 {
74		compatible = "ti,j721e-uart", "ti,am654-uart";
75		reg = <0x00 0x42300000 0x00 0x100>;
76		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
77		clock-frequency = <48000000>;
78		current-speed = <115200>;
79		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
80		clocks = <&k3_clks 287 0>;
81		clock-names = "fclk";
82	};
83
84	mcu_uart0: serial@40a00000 {
85		compatible = "ti,j721e-uart", "ti,am654-uart";
86		reg = <0x00 0x40a00000 0x00 0x100>;
87		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
88		clock-frequency = <96000000>;
89		current-speed = <115200>;
90		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
91		clocks = <&k3_clks 149 0>;
92		clock-names = "fclk";
93	};
94
95	wkup_gpio_intr: interrupt-controller@42200000 {
96		compatible = "ti,sci-intr";
97		reg = <0x00 0x42200000 0x00 0x400>;
98		ti,intr-trigger-type = <1>;
99		interrupt-controller;
100		interrupt-parent = <&gic500>;
101		#interrupt-cells = <1>;
102		ti,sci = <&dmsc>;
103		ti,sci-dev-id = <137>;
104		ti,interrupt-ranges = <16 960 16>;
105	};
106
107	wkup_gpio0: gpio@42110000 {
108		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
109		reg = <0x0 0x42110000 0x0 0x100>;
110		gpio-controller;
111		#gpio-cells = <2>;
112		interrupt-parent = <&wkup_gpio_intr>;
113		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
114		interrupt-controller;
115		#interrupt-cells = <2>;
116		ti,ngpio = <84>;
117		ti,davinci-gpio-unbanked = <0>;
118		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
119		clocks = <&k3_clks 113 0>;
120		clock-names = "gpio";
121	};
122
123	wkup_gpio1: gpio@42100000 {
124		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
125		reg = <0x0 0x42100000 0x0 0x100>;
126		gpio-controller;
127		#gpio-cells = <2>;
128		interrupt-parent = <&wkup_gpio_intr>;
129		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
130		interrupt-controller;
131		#interrupt-cells = <2>;
132		ti,ngpio = <84>;
133		ti,davinci-gpio-unbanked = <0>;
134		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
135		clocks = <&k3_clks 114 0>;
136		clock-names = "gpio";
137	};
138
139	mcu_i2c0: i2c@40b00000 {
140		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
141		reg = <0x0 0x40b00000 0x0 0x100>;
142		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
143		#address-cells = <1>;
144		#size-cells = <0>;
145		clock-names = "fck";
146		clocks = <&k3_clks 194 0>;
147		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
148	};
149
150	mcu_i2c1: i2c@40b10000 {
151		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
152		reg = <0x0 0x40b10000 0x0 0x100>;
153		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
154		#address-cells = <1>;
155		#size-cells = <0>;
156		clock-names = "fck";
157		clocks = <&k3_clks 195 0>;
158		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
159	};
160
161	wkup_i2c0: i2c@42120000 {
162		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
163		reg = <0x0 0x42120000 0x0 0x100>;
164		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
165		#address-cells = <1>;
166		#size-cells = <0>;
167		clock-names = "fck";
168		clocks = <&k3_clks 197 0>;
169		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
170	};
171
172	fss: fss@47000000 {
173		compatible = "simple-bus";
174		reg = <0x0 0x47000000 0x0 0x100>;
175		#address-cells = <2>;
176		#size-cells = <2>;
177		ranges;
178
179		ospi0: spi@47040000 {
180			compatible = "ti,am654-ospi", "cdns,qspi-nor";
181			reg = <0x0 0x47040000 0x0 0x100>,
182				<0x5 0x00000000 0x1 0x0000000>;
183			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
184			cdns,fifo-depth = <256>;
185			cdns,fifo-width = <4>;
186			cdns,trigger-address = <0x0>;
187			clocks = <&k3_clks 103 0>;
188			assigned-clocks = <&k3_clks 103 0>;
189			assigned-clock-parents = <&k3_clks 103 2>;
190			assigned-clock-rates = <166666666>;
191			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
192			#address-cells = <1>;
193			#size-cells = <0>;
194		};
195
196		ospi1: spi@47050000 {
197			compatible = "ti,am654-ospi", "cdns,qspi-nor";
198			reg = <0x0 0x47050000 0x0 0x100>,
199				<0x7 0x00000000 0x1 0x00000000>;
200			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
201			cdns,fifo-depth = <256>;
202			cdns,fifo-width = <4>;
203			cdns,trigger-address = <0x0>;
204			clocks = <&k3_clks 104 0>;
205			power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
206			#address-cells = <1>;
207			#size-cells = <0>;
208		};
209	};
210
211	tscadc0: tscadc@40200000 {
212		compatible = "ti,am3359-tscadc";
213		reg = <0x0 0x40200000 0x0 0x1000>;
214		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
215		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
216		clocks = <&k3_clks 0 1>;
217		assigned-clocks = <&k3_clks 0 3>;
218		assigned-clock-rates = <60000000>;
219		clock-names = "adc_tsc_fck";
220		dmas = <&main_udmap 0x7400>,
221			<&main_udmap 0x7401>;
222		dma-names = "fifo0", "fifo1";
223
224		adc {
225			#io-channel-cells = <1>;
226			compatible = "ti,am3359-adc";
227		};
228	};
229
230	tscadc1: tscadc@40210000 {
231		compatible = "ti,am3359-tscadc";
232		reg = <0x0 0x40210000 0x0 0x1000>;
233		interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
234		power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
235		clocks = <&k3_clks 1 1>;
236		assigned-clocks = <&k3_clks 1 3>;
237		assigned-clock-rates = <60000000>;
238		clock-names = "adc_tsc_fck";
239		dmas = <&main_udmap 0x7402>,
240			<&main_udmap 0x7403>;
241		dma-names = "fifo0", "fifo1";
242
243		adc {
244			#io-channel-cells = <1>;
245			compatible = "ti,am3359-adc";
246		};
247	};
248
249	mcu_navss: bus@28380000 {
250		compatible = "simple-mfd";
251		#address-cells = <2>;
252		#size-cells = <2>;
253		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
254		dma-coherent;
255		dma-ranges;
256
257		ti,sci-dev-id = <232>;
258
259		mcu_ringacc: ringacc@2b800000 {
260			compatible = "ti,am654-navss-ringacc";
261			reg =	<0x0 0x2b800000 0x0 0x400000>,
262				<0x0 0x2b000000 0x0 0x400000>,
263				<0x0 0x28590000 0x0 0x100>,
264				<0x0 0x2a500000 0x0 0x40000>;
265			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
266			ti,num-rings = <286>;
267			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
268			ti,sci = <&dmsc>;
269			ti,sci-dev-id = <235>;
270			msi-parent = <&main_udmass_inta>;
271		};
272
273		mcu_udmap: dma-controller@285c0000 {
274			compatible = "ti,j721e-navss-mcu-udmap";
275			reg =	<0x0 0x285c0000 0x0 0x100>,
276				<0x0 0x2a800000 0x0 0x40000>,
277				<0x0 0x2aa00000 0x0 0x40000>;
278			reg-names = "gcfg", "rchanrt", "tchanrt";
279			msi-parent = <&main_udmass_inta>;
280			#dma-cells = <1>;
281
282			ti,sci = <&dmsc>;
283			ti,sci-dev-id = <236>;
284			ti,ringacc = <&mcu_ringacc>;
285
286			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
287						<0x0f>; /* TX_HCHAN */
288			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
289						<0x0b>; /* RX_HCHAN */
290			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
291		};
292	};
293
294	mcu_cpsw: ethernet@46000000 {
295		compatible = "ti,j721e-cpsw-nuss";
296		#address-cells = <2>;
297		#size-cells = <2>;
298		reg = <0x0 0x46000000 0x0 0x200000>;
299		reg-names = "cpsw_nuss";
300		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
301		dma-coherent;
302		clocks = <&k3_clks 18 22>;
303		clock-names = "fck";
304		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
305
306		dmas = <&mcu_udmap 0xf000>,
307		       <&mcu_udmap 0xf001>,
308		       <&mcu_udmap 0xf002>,
309		       <&mcu_udmap 0xf003>,
310		       <&mcu_udmap 0xf004>,
311		       <&mcu_udmap 0xf005>,
312		       <&mcu_udmap 0xf006>,
313		       <&mcu_udmap 0xf007>,
314		       <&mcu_udmap 0x7000>;
315		dma-names = "tx0", "tx1", "tx2", "tx3",
316			    "tx4", "tx5", "tx6", "tx7",
317			    "rx";
318
319		ethernet-ports {
320			#address-cells = <1>;
321			#size-cells = <0>;
322
323			cpsw_port1: port@1 {
324				reg = <1>;
325				ti,mac-only;
326				label = "port1";
327				ti,syscon-efuse = <&mcu_conf 0x200>;
328				phys = <&phy_gmii_sel 1>;
329			};
330		};
331
332		davinci_mdio: mdio@f00 {
333			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
334			reg = <0x0 0xf00 0x0 0x100>;
335			#address-cells = <1>;
336			#size-cells = <0>;
337			clocks = <&k3_clks 18 22>;
338			clock-names = "fck";
339			bus_freq = <1000000>;
340		};
341
342		cpts@3d000 {
343			compatible = "ti,am65-cpts";
344			reg = <0x0 0x3d000 0x0 0x400>;
345			clocks = <&k3_clks 18 2>;
346			clock-names = "cpts";
347			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
348			interrupt-names = "cpts";
349			ti,cpts-ext-ts-inputs = <4>;
350			ti,cpts-periodic-outputs = <2>;
351		};
352	};
353
354	mcu_r5fss0: r5fss@41000000 {
355		compatible = "ti,j721e-r5fss";
356		ti,cluster-mode = <1>;
357		#address-cells = <1>;
358		#size-cells = <1>;
359		ranges = <0x41000000 0x00 0x41000000 0x20000>,
360			 <0x41400000 0x00 0x41400000 0x20000>;
361		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
362
363		mcu_r5fss0_core0: r5f@41000000 {
364			compatible = "ti,j721e-r5f";
365			reg = <0x41000000 0x00008000>,
366			      <0x41010000 0x00008000>;
367			reg-names = "atcm", "btcm";
368			ti,sci = <&dmsc>;
369			ti,sci-dev-id = <250>;
370			ti,sci-proc-ids = <0x01 0xff>;
371			resets = <&k3_reset 250 1>;
372			firmware-name = "j7-mcu-r5f0_0-fw";
373			ti,atcm-enable = <1>;
374			ti,btcm-enable = <1>;
375			ti,loczrama = <1>;
376		};
377
378		mcu_r5fss0_core1: r5f@41400000 {
379			compatible = "ti,j721e-r5f";
380			reg = <0x41400000 0x00008000>,
381			      <0x41410000 0x00008000>;
382			reg-names = "atcm", "btcm";
383			ti,sci = <&dmsc>;
384			ti,sci-dev-id = <251>;
385			ti,sci-proc-ids = <0x02 0xff>;
386			resets = <&k3_reset 251 1>;
387			firmware-name = "j7-mcu-r5f0_1-fw";
388			ti,atcm-enable = <1>;
389			ti,btcm-enable = <1>;
390			ti,loczrama = <1>;
391		};
392	};
393};
394