1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x0 0x43000014 0x0 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x178>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 mcu_ram: sram@41c00000 { 66 compatible = "mmio-sram"; 67 reg = <0x00 0x41c00000 0x00 0x100000>; 68 ranges = <0x0 0x00 0x41c00000 0x100000>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 }; 72 73 wkup_uart0: serial@42300000 { 74 compatible = "ti,j721e-uart", "ti,am654-uart"; 75 reg = <0x00 0x42300000 0x00 0x100>; 76 reg-shift = <2>; 77 reg-io-width = <4>; 78 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 79 clock-frequency = <48000000>; 80 current-speed = <115200>; 81 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 82 clocks = <&k3_clks 287 0>; 83 clock-names = "fclk"; 84 }; 85 86 mcu_uart0: serial@40a00000 { 87 compatible = "ti,j721e-uart", "ti,am654-uart"; 88 reg = <0x00 0x40a00000 0x00 0x100>; 89 reg-shift = <2>; 90 reg-io-width = <4>; 91 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 92 clock-frequency = <96000000>; 93 current-speed = <115200>; 94 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 95 clocks = <&k3_clks 149 0>; 96 clock-names = "fclk"; 97 }; 98 99 wkup_gpio_intr: interrupt-controller@42200000 { 100 compatible = "ti,sci-intr"; 101 reg = <0x00 0x42200000 0x00 0x400>; 102 ti,intr-trigger-type = <1>; 103 interrupt-controller; 104 interrupt-parent = <&gic500>; 105 #interrupt-cells = <1>; 106 ti,sci = <&dmsc>; 107 ti,sci-dev-id = <137>; 108 ti,interrupt-ranges = <16 960 16>; 109 }; 110 111 wkup_gpio0: gpio@42110000 { 112 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 113 reg = <0x0 0x42110000 0x0 0x100>; 114 gpio-controller; 115 #gpio-cells = <2>; 116 interrupt-parent = <&wkup_gpio_intr>; 117 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 ti,ngpio = <84>; 121 ti,davinci-gpio-unbanked = <0>; 122 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 123 clocks = <&k3_clks 113 0>; 124 clock-names = "gpio"; 125 }; 126 127 wkup_gpio1: gpio@42100000 { 128 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 129 reg = <0x0 0x42100000 0x0 0x100>; 130 gpio-controller; 131 #gpio-cells = <2>; 132 interrupt-parent = <&wkup_gpio_intr>; 133 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 134 interrupt-controller; 135 #interrupt-cells = <2>; 136 ti,ngpio = <84>; 137 ti,davinci-gpio-unbanked = <0>; 138 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 139 clocks = <&k3_clks 114 0>; 140 clock-names = "gpio"; 141 }; 142 143 mcu_i2c0: i2c@40b00000 { 144 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 145 reg = <0x0 0x40b00000 0x0 0x100>; 146 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 clock-names = "fck"; 150 clocks = <&k3_clks 194 0>; 151 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 152 }; 153 154 mcu_i2c1: i2c@40b10000 { 155 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 156 reg = <0x0 0x40b10000 0x0 0x100>; 157 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 clock-names = "fck"; 161 clocks = <&k3_clks 195 0>; 162 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 163 }; 164 165 wkup_i2c0: i2c@42120000 { 166 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 167 reg = <0x0 0x42120000 0x0 0x100>; 168 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clock-names = "fck"; 172 clocks = <&k3_clks 197 0>; 173 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 174 }; 175 176 fss: fss@47000000 { 177 compatible = "simple-bus"; 178 reg = <0x0 0x47000000 0x0 0x100>; 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges; 182 183 ospi0: spi@47040000 { 184 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 185 reg = <0x0 0x47040000 0x0 0x100>, 186 <0x5 0x00000000 0x1 0x0000000>; 187 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 188 cdns,fifo-depth = <256>; 189 cdns,fifo-width = <4>; 190 cdns,trigger-address = <0x0>; 191 clocks = <&k3_clks 103 0>; 192 assigned-clocks = <&k3_clks 103 0>; 193 assigned-clock-parents = <&k3_clks 103 2>; 194 assigned-clock-rates = <166666666>; 195 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 }; 199 200 ospi1: spi@47050000 { 201 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 202 reg = <0x0 0x47050000 0x0 0x100>, 203 <0x7 0x00000000 0x1 0x00000000>; 204 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 205 cdns,fifo-depth = <256>; 206 cdns,fifo-width = <4>; 207 cdns,trigger-address = <0x0>; 208 clocks = <&k3_clks 104 0>; 209 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 }; 213 }; 214 215 tscadc0: tscadc@40200000 { 216 compatible = "ti,am3359-tscadc"; 217 reg = <0x0 0x40200000 0x0 0x1000>; 218 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 219 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 220 clocks = <&k3_clks 0 1>; 221 assigned-clocks = <&k3_clks 0 3>; 222 assigned-clock-rates = <60000000>; 223 clock-names = "adc_tsc_fck"; 224 dmas = <&main_udmap 0x7400>, 225 <&main_udmap 0x7401>; 226 dma-names = "fifo0", "fifo1"; 227 228 adc { 229 #io-channel-cells = <1>; 230 compatible = "ti,am3359-adc"; 231 }; 232 }; 233 234 tscadc1: tscadc@40210000 { 235 compatible = "ti,am3359-tscadc"; 236 reg = <0x0 0x40210000 0x0 0x1000>; 237 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 238 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 239 clocks = <&k3_clks 1 1>; 240 assigned-clocks = <&k3_clks 1 3>; 241 assigned-clock-rates = <60000000>; 242 clock-names = "adc_tsc_fck"; 243 dmas = <&main_udmap 0x7402>, 244 <&main_udmap 0x7403>; 245 dma-names = "fifo0", "fifo1"; 246 247 adc { 248 #io-channel-cells = <1>; 249 compatible = "ti,am3359-adc"; 250 }; 251 }; 252 253 mcu_navss: bus@28380000 { 254 compatible = "simple-mfd"; 255 #address-cells = <2>; 256 #size-cells = <2>; 257 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 258 dma-coherent; 259 dma-ranges; 260 261 ti,sci-dev-id = <232>; 262 263 mcu_ringacc: ringacc@2b800000 { 264 compatible = "ti,am654-navss-ringacc"; 265 reg = <0x0 0x2b800000 0x0 0x400000>, 266 <0x0 0x2b000000 0x0 0x400000>, 267 <0x0 0x28590000 0x0 0x100>, 268 <0x0 0x2a500000 0x0 0x40000>; 269 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 270 ti,num-rings = <286>; 271 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 272 ti,sci = <&dmsc>; 273 ti,sci-dev-id = <235>; 274 msi-parent = <&main_udmass_inta>; 275 }; 276 277 mcu_udmap: dma-controller@285c0000 { 278 compatible = "ti,j721e-navss-mcu-udmap"; 279 reg = <0x0 0x285c0000 0x0 0x100>, 280 <0x0 0x2a800000 0x0 0x40000>, 281 <0x0 0x2aa00000 0x0 0x40000>; 282 reg-names = "gcfg", "rchanrt", "tchanrt"; 283 msi-parent = <&main_udmass_inta>; 284 #dma-cells = <1>; 285 286 ti,sci = <&dmsc>; 287 ti,sci-dev-id = <236>; 288 ti,ringacc = <&mcu_ringacc>; 289 290 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 291 <0x0f>; /* TX_HCHAN */ 292 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 293 <0x0b>; /* RX_HCHAN */ 294 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 295 }; 296 }; 297 298 mcu_cpsw: ethernet@46000000 { 299 compatible = "ti,j721e-cpsw-nuss"; 300 #address-cells = <2>; 301 #size-cells = <2>; 302 reg = <0x0 0x46000000 0x0 0x200000>; 303 reg-names = "cpsw_nuss"; 304 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 305 dma-coherent; 306 clocks = <&k3_clks 18 22>; 307 clock-names = "fck"; 308 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 309 310 dmas = <&mcu_udmap 0xf000>, 311 <&mcu_udmap 0xf001>, 312 <&mcu_udmap 0xf002>, 313 <&mcu_udmap 0xf003>, 314 <&mcu_udmap 0xf004>, 315 <&mcu_udmap 0xf005>, 316 <&mcu_udmap 0xf006>, 317 <&mcu_udmap 0xf007>, 318 <&mcu_udmap 0x7000>; 319 dma-names = "tx0", "tx1", "tx2", "tx3", 320 "tx4", "tx5", "tx6", "tx7", 321 "rx"; 322 323 ethernet-ports { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 cpsw_port1: port@1 { 328 reg = <1>; 329 ti,mac-only; 330 label = "port1"; 331 ti,syscon-efuse = <&mcu_conf 0x200>; 332 phys = <&phy_gmii_sel 1>; 333 }; 334 }; 335 336 davinci_mdio: mdio@f00 { 337 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 338 reg = <0x0 0xf00 0x0 0x100>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clocks = <&k3_clks 18 22>; 342 clock-names = "fck"; 343 bus_freq = <1000000>; 344 }; 345 346 cpts@3d000 { 347 compatible = "ti,am65-cpts"; 348 reg = <0x0 0x3d000 0x0 0x400>; 349 clocks = <&k3_clks 18 2>; 350 clock-names = "cpts"; 351 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 352 interrupt-names = "cpts"; 353 ti,cpts-ext-ts-inputs = <4>; 354 ti,cpts-periodic-outputs = <2>; 355 }; 356 }; 357 358 mcu_r5fss0: r5fss@41000000 { 359 compatible = "ti,j721e-r5fss"; 360 ti,cluster-mode = <1>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 ranges = <0x41000000 0x00 0x41000000 0x20000>, 364 <0x41400000 0x00 0x41400000 0x20000>; 365 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 366 367 mcu_r5fss0_core0: r5f@41000000 { 368 compatible = "ti,j721e-r5f"; 369 reg = <0x41000000 0x00008000>, 370 <0x41010000 0x00008000>; 371 reg-names = "atcm", "btcm"; 372 ti,sci = <&dmsc>; 373 ti,sci-dev-id = <250>; 374 ti,sci-proc-ids = <0x01 0xff>; 375 resets = <&k3_reset 250 1>; 376 firmware-name = "j7-mcu-r5f0_0-fw"; 377 ti,atcm-enable = <1>; 378 ti,btcm-enable = <1>; 379 ti,loczrama = <1>; 380 }; 381 382 mcu_r5fss0_core1: r5f@41400000 { 383 compatible = "ti,j721e-r5f"; 384 reg = <0x41400000 0x00008000>, 385 <0x41410000 0x00008000>; 386 reg-names = "atcm", "btcm"; 387 ti,sci = <&dmsc>; 388 ti,sci-dev-id = <251>; 389 ti,sci-proc-ids = <0x02 0xff>; 390 resets = <&k3_reset 251 1>; 391 firmware-name = "j7-mcu-r5f0_1-fw"; 392 ti,atcm-enable = <1>; 393 ti,btcm-enable = <1>; 394 ti,loczrama = <1>; 395 }; 396 }; 397}; 398