1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10#include <dt-bindings/mux/ti-serdes.h> 11 12/ { 13 cmn_refclk: clock-cmnrefclk { 14 #clock-cells = <0>; 15 compatible = "fixed-clock"; 16 clock-frequency = <0>; 17 }; 18 19 cmn_refclk1: clock-cmnrefclk1 { 20 #clock-cells = <0>; 21 compatible = "fixed-clock"; 22 clock-frequency = <0>; 23 }; 24}; 25 26&cbass_main { 27 msmc_ram: sram@70000000 { 28 compatible = "mmio-sram"; 29 reg = <0x0 0x70000000 0x0 0x800000>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 ranges = <0x0 0x0 0x70000000 0x800000>; 33 34 atf-sram@0 { 35 reg = <0x0 0x20000>; 36 }; 37 }; 38 39 scm_conf: scm-conf@100000 { 40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x0 0x00100000 0x1c000>; 45 46 serdes_ln_ctrl: mux-controller@4080 { 47 compatible = "mmio-mux"; 48 reg = <0x00004080 0x50>; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 51 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 52 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 53 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 54 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 55 /* SERDES4 lane0/1/2/3 select */ 56 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 57 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 58 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 59 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 60 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 61 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 62 }; 63 64 cpsw0_phy_gmii_sel: phy@4044 { 65 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 66 ti,qsgmii-main-ports = <2>, <2>; 67 reg = <0x4044 0x20>; 68 #phy-cells = <1>; 69 }; 70 71 usb_serdes_mux: mux-controller@4000 { 72 compatible = "mmio-mux"; 73 #mux-control-cells = <1>; 74 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 75 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 76 }; 77 78 ehrpwm_tbclk: clock-controller@4140 { 79 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 80 reg = <0x4140 0x18>; 81 #clock-cells = <1>; 82 }; 83 }; 84 85 main_ehrpwm0: pwm@3000000 { 86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 87 #pwm-cells = <3>; 88 reg = <0x00 0x3000000 0x00 0x100>; 89 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 90 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 91 clock-names = "tbclk", "fck"; 92 status = "disabled"; 93 }; 94 95 main_ehrpwm1: pwm@3010000 { 96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 97 #pwm-cells = <3>; 98 reg = <0x00 0x3010000 0x00 0x100>; 99 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 100 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 101 clock-names = "tbclk", "fck"; 102 status = "disabled"; 103 }; 104 105 main_ehrpwm2: pwm@3020000 { 106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 107 #pwm-cells = <3>; 108 reg = <0x00 0x3020000 0x00 0x100>; 109 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 110 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 111 clock-names = "tbclk", "fck"; 112 status = "disabled"; 113 }; 114 115 main_ehrpwm3: pwm@3030000 { 116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 117 #pwm-cells = <3>; 118 reg = <0x00 0x3030000 0x00 0x100>; 119 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 120 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 121 clock-names = "tbclk", "fck"; 122 status = "disabled"; 123 }; 124 125 main_ehrpwm4: pwm@3040000 { 126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 127 #pwm-cells = <3>; 128 reg = <0x00 0x3040000 0x00 0x100>; 129 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 130 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 131 clock-names = "tbclk", "fck"; 132 status = "disabled"; 133 }; 134 135 main_ehrpwm5: pwm@3050000 { 136 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 137 #pwm-cells = <3>; 138 reg = <0x00 0x3050000 0x00 0x100>; 139 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 140 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 141 clock-names = "tbclk", "fck"; 142 status = "disabled"; 143 }; 144 145 gic500: interrupt-controller@1800000 { 146 compatible = "arm,gic-v3"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 153 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 154 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 155 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 156 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 157 158 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 160 161 gic_its: msi-controller@1820000 { 162 compatible = "arm,gic-v3-its"; 163 reg = <0x00 0x01820000 0x00 0x10000>; 164 socionext,synquacer-pre-its = <0x1000000 0x400000>; 165 msi-controller; 166 #msi-cells = <1>; 167 }; 168 }; 169 170 main_gpio_intr: interrupt-controller@a00000 { 171 compatible = "ti,sci-intr"; 172 reg = <0x00 0x00a00000 0x00 0x800>; 173 ti,intr-trigger-type = <1>; 174 interrupt-controller; 175 interrupt-parent = <&gic500>; 176 #interrupt-cells = <1>; 177 ti,sci = <&dmsc>; 178 ti,sci-dev-id = <131>; 179 ti,interrupt-ranges = <8 392 56>; 180 }; 181 182 main_navss: bus@30000000 { 183 compatible = "simple-mfd"; 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 187 dma-coherent; 188 dma-ranges; 189 190 ti,sci-dev-id = <199>; 191 192 main_navss_intr: interrupt-controller@310e0000 { 193 compatible = "ti,sci-intr"; 194 reg = <0x0 0x310e0000 0x0 0x4000>; 195 ti,intr-trigger-type = <4>; 196 interrupt-controller; 197 interrupt-parent = <&gic500>; 198 #interrupt-cells = <1>; 199 ti,sci = <&dmsc>; 200 ti,sci-dev-id = <213>; 201 ti,interrupt-ranges = <0 64 64>, 202 <64 448 64>, 203 <128 672 64>; 204 }; 205 206 main_udmass_inta: interrupt-controller@33d00000 { 207 compatible = "ti,sci-inta"; 208 reg = <0x0 0x33d00000 0x0 0x100000>; 209 interrupt-controller; 210 interrupt-parent = <&main_navss_intr>; 211 msi-controller; 212 #interrupt-cells = <0>; 213 ti,sci = <&dmsc>; 214 ti,sci-dev-id = <209>; 215 ti,interrupt-ranges = <0 0 256>; 216 }; 217 218 secure_proxy_main: mailbox@32c00000 { 219 compatible = "ti,am654-secure-proxy"; 220 #mbox-cells = <1>; 221 reg-names = "target_data", "rt", "scfg"; 222 reg = <0x00 0x32c00000 0x00 0x100000>, 223 <0x00 0x32400000 0x00 0x100000>, 224 <0x00 0x32800000 0x00 0x100000>; 225 interrupt-names = "rx_011"; 226 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 smmu0: iommu@36600000 { 230 compatible = "arm,smmu-v3"; 231 reg = <0x0 0x36600000 0x0 0x100000>; 232 interrupt-parent = <&gic500>; 233 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 235 interrupt-names = "eventq", "gerror"; 236 #iommu-cells = <1>; 237 }; 238 239 hwspinlock: spinlock@30e00000 { 240 compatible = "ti,am654-hwspinlock"; 241 reg = <0x00 0x30e00000 0x00 0x1000>; 242 #hwlock-cells = <1>; 243 }; 244 245 mailbox0_cluster0: mailbox@31f80000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f80000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster1: mailbox@31f81000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f81000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 mailbox0_cluster2: mailbox@31f82000 { 266 compatible = "ti,am654-mailbox"; 267 reg = <0x00 0x31f82000 0x00 0x200>; 268 #mbox-cells = <1>; 269 ti,mbox-num-users = <4>; 270 ti,mbox-num-fifos = <16>; 271 interrupt-parent = <&main_navss_intr>; 272 status = "disabled"; 273 }; 274 275 mailbox0_cluster3: mailbox@31f83000 { 276 compatible = "ti,am654-mailbox"; 277 reg = <0x00 0x31f83000 0x00 0x200>; 278 #mbox-cells = <1>; 279 ti,mbox-num-users = <4>; 280 ti,mbox-num-fifos = <16>; 281 interrupt-parent = <&main_navss_intr>; 282 status = "disabled"; 283 }; 284 285 mailbox0_cluster4: mailbox@31f84000 { 286 compatible = "ti,am654-mailbox"; 287 reg = <0x00 0x31f84000 0x00 0x200>; 288 #mbox-cells = <1>; 289 ti,mbox-num-users = <4>; 290 ti,mbox-num-fifos = <16>; 291 interrupt-parent = <&main_navss_intr>; 292 status = "disabled"; 293 }; 294 295 mailbox0_cluster5: mailbox@31f85000 { 296 compatible = "ti,am654-mailbox"; 297 reg = <0x00 0x31f85000 0x00 0x200>; 298 #mbox-cells = <1>; 299 ti,mbox-num-users = <4>; 300 ti,mbox-num-fifos = <16>; 301 interrupt-parent = <&main_navss_intr>; 302 status = "disabled"; 303 }; 304 305 mailbox0_cluster6: mailbox@31f86000 { 306 compatible = "ti,am654-mailbox"; 307 reg = <0x00 0x31f86000 0x00 0x200>; 308 #mbox-cells = <1>; 309 ti,mbox-num-users = <4>; 310 ti,mbox-num-fifos = <16>; 311 interrupt-parent = <&main_navss_intr>; 312 status = "disabled"; 313 }; 314 315 mailbox0_cluster7: mailbox@31f87000 { 316 compatible = "ti,am654-mailbox"; 317 reg = <0x00 0x31f87000 0x00 0x200>; 318 #mbox-cells = <1>; 319 ti,mbox-num-users = <4>; 320 ti,mbox-num-fifos = <16>; 321 interrupt-parent = <&main_navss_intr>; 322 status = "disabled"; 323 }; 324 325 mailbox0_cluster8: mailbox@31f88000 { 326 compatible = "ti,am654-mailbox"; 327 reg = <0x00 0x31f88000 0x00 0x200>; 328 #mbox-cells = <1>; 329 ti,mbox-num-users = <4>; 330 ti,mbox-num-fifos = <16>; 331 interrupt-parent = <&main_navss_intr>; 332 status = "disabled"; 333 }; 334 335 mailbox0_cluster9: mailbox@31f89000 { 336 compatible = "ti,am654-mailbox"; 337 reg = <0x00 0x31f89000 0x00 0x200>; 338 #mbox-cells = <1>; 339 ti,mbox-num-users = <4>; 340 ti,mbox-num-fifos = <16>; 341 interrupt-parent = <&main_navss_intr>; 342 status = "disabled"; 343 }; 344 345 mailbox0_cluster10: mailbox@31f8a000 { 346 compatible = "ti,am654-mailbox"; 347 reg = <0x00 0x31f8a000 0x00 0x200>; 348 #mbox-cells = <1>; 349 ti,mbox-num-users = <4>; 350 ti,mbox-num-fifos = <16>; 351 interrupt-parent = <&main_navss_intr>; 352 status = "disabled"; 353 }; 354 355 mailbox0_cluster11: mailbox@31f8b000 { 356 compatible = "ti,am654-mailbox"; 357 reg = <0x00 0x31f8b000 0x00 0x200>; 358 #mbox-cells = <1>; 359 ti,mbox-num-users = <4>; 360 ti,mbox-num-fifos = <16>; 361 interrupt-parent = <&main_navss_intr>; 362 status = "disabled"; 363 }; 364 365 main_ringacc: ringacc@3c000000 { 366 compatible = "ti,am654-navss-ringacc"; 367 reg = <0x0 0x3c000000 0x0 0x400000>, 368 <0x0 0x38000000 0x0 0x400000>, 369 <0x0 0x31120000 0x0 0x100>, 370 <0x0 0x33000000 0x0 0x40000>; 371 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 372 ti,num-rings = <1024>; 373 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 374 ti,sci = <&dmsc>; 375 ti,sci-dev-id = <211>; 376 msi-parent = <&main_udmass_inta>; 377 }; 378 379 main_udmap: dma-controller@31150000 { 380 compatible = "ti,j721e-navss-main-udmap"; 381 reg = <0x0 0x31150000 0x0 0x100>, 382 <0x0 0x34000000 0x0 0x100000>, 383 <0x0 0x35000000 0x0 0x100000>; 384 reg-names = "gcfg", "rchanrt", "tchanrt"; 385 msi-parent = <&main_udmass_inta>; 386 #dma-cells = <1>; 387 388 ti,sci = <&dmsc>; 389 ti,sci-dev-id = <212>; 390 ti,ringacc = <&main_ringacc>; 391 392 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 393 <0x0f>, /* TX_HCHAN */ 394 <0x10>; /* TX_UHCHAN */ 395 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 396 <0x0b>, /* RX_HCHAN */ 397 <0x0c>; /* RX_UHCHAN */ 398 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 399 }; 400 401 cpts@310d0000 { 402 compatible = "ti,j721e-cpts"; 403 reg = <0x0 0x310d0000 0x0 0x400>; 404 reg-names = "cpts"; 405 clocks = <&k3_clks 201 1>; 406 clock-names = "cpts"; 407 interrupts-extended = <&main_navss_intr 391>; 408 interrupt-names = "cpts"; 409 ti,cpts-periodic-outputs = <6>; 410 ti,cpts-ext-ts-inputs = <8>; 411 }; 412 }; 413 414 cpsw0: ethernet@c000000 { 415 compatible = "ti,j721e-cpswxg-nuss"; 416 #address-cells = <2>; 417 #size-cells = <2>; 418 reg = <0x0 0xc000000 0x0 0x200000>; 419 reg-names = "cpsw_nuss"; 420 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 421 clocks = <&k3_clks 19 89>; 422 clock-names = "fck"; 423 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 424 425 dmas = <&main_udmap 0xca00>, 426 <&main_udmap 0xca01>, 427 <&main_udmap 0xca02>, 428 <&main_udmap 0xca03>, 429 <&main_udmap 0xca04>, 430 <&main_udmap 0xca05>, 431 <&main_udmap 0xca06>, 432 <&main_udmap 0xca07>, 433 <&main_udmap 0x4a00>; 434 dma-names = "tx0", "tx1", "tx2", "tx3", 435 "tx4", "tx5", "tx6", "tx7", 436 "rx"; 437 438 status = "disabled"; 439 440 ethernet-ports { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 cpsw0_port1: port@1 { 444 reg = <1>; 445 ti,mac-only; 446 label = "port1"; 447 status = "disabled"; 448 }; 449 450 cpsw0_port2: port@2 { 451 reg = <2>; 452 ti,mac-only; 453 label = "port2"; 454 status = "disabled"; 455 }; 456 457 cpsw0_port3: port@3 { 458 reg = <3>; 459 ti,mac-only; 460 label = "port3"; 461 status = "disabled"; 462 }; 463 464 cpsw0_port4: port@4 { 465 reg = <4>; 466 ti,mac-only; 467 label = "port4"; 468 status = "disabled"; 469 }; 470 471 cpsw0_port5: port@5 { 472 reg = <5>; 473 ti,mac-only; 474 label = "port5"; 475 status = "disabled"; 476 }; 477 478 cpsw0_port6: port@6 { 479 reg = <6>; 480 ti,mac-only; 481 label = "port6"; 482 status = "disabled"; 483 }; 484 485 cpsw0_port7: port@7 { 486 reg = <7>; 487 ti,mac-only; 488 label = "port7"; 489 status = "disabled"; 490 }; 491 492 cpsw0_port8: port@8 { 493 reg = <8>; 494 ti,mac-only; 495 label = "port8"; 496 status = "disabled"; 497 }; 498 }; 499 500 cpsw9g_mdio: mdio@f00 { 501 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 502 reg = <0x0 0xf00 0x0 0x100>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&k3_clks 19 89>; 506 clock-names = "fck"; 507 bus_freq = <1000000>; 508 status = "disabled"; 509 }; 510 511 cpts@3d000 { 512 compatible = "ti,j721e-cpts"; 513 reg = <0x0 0x3d000 0x0 0x400>; 514 clocks = <&k3_clks 19 16>; 515 clock-names = "cpts"; 516 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 517 interrupt-names = "cpts"; 518 ti,cpts-ext-ts-inputs = <4>; 519 ti,cpts-periodic-outputs = <2>; 520 }; 521 }; 522 523 main_crypto: crypto@4e00000 { 524 compatible = "ti,j721e-sa2ul"; 525 reg = <0x0 0x4e00000 0x0 0x1200>; 526 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 527 #address-cells = <2>; 528 #size-cells = <2>; 529 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 530 531 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 532 <&main_udmap 0x4001>; 533 dma-names = "tx", "rx1", "rx2"; 534 535 rng: rng@4e10000 { 536 compatible = "inside-secure,safexcel-eip76"; 537 reg = <0x0 0x4e10000 0x0 0x7d>; 538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 }; 541 542 main_pmx0: pinctrl@11c000 { 543 compatible = "pinctrl-single"; 544 /* Proxy 0 addressing */ 545 reg = <0x0 0x11c000 0x0 0x2b4>; 546 #pinctrl-cells = <1>; 547 pinctrl-single,register-width = <32>; 548 pinctrl-single,function-mask = <0xffffffff>; 549 }; 550 551 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 552 main_timerio_input: pinctrl@104200 { 553 compatible = "pinctrl-single"; 554 reg = <0x00 0x104200 0x00 0x50>; 555 #pinctrl-cells = <1>; 556 pinctrl-single,register-width = <32>; 557 pinctrl-single,function-mask = <0x00000007>; 558 }; 559 560 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 561 main_timerio_output: pinctrl@104280 { 562 compatible = "pinctrl-single"; 563 reg = <0x00 0x104280 0x00 0x20>; 564 #pinctrl-cells = <1>; 565 pinctrl-single,register-width = <32>; 566 pinctrl-single,function-mask = <0x0000001f>; 567 }; 568 569 serdes_wiz0: wiz@5000000 { 570 compatible = "ti,j721e-wiz-16g"; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 574 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 575 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 576 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 577 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 578 num-lanes = <2>; 579 #reset-cells = <1>; 580 ranges = <0x5000000 0x0 0x5000000 0x10000>; 581 582 wiz0_pll0_refclk: pll0-refclk { 583 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 584 #clock-cells = <0>; 585 assigned-clocks = <&wiz0_pll0_refclk>; 586 assigned-clock-parents = <&k3_clks 292 11>; 587 }; 588 589 wiz0_pll1_refclk: pll1-refclk { 590 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 591 #clock-cells = <0>; 592 assigned-clocks = <&wiz0_pll1_refclk>; 593 assigned-clock-parents = <&k3_clks 292 0>; 594 }; 595 596 wiz0_refclk_dig: refclk-dig { 597 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 598 #clock-cells = <0>; 599 assigned-clocks = <&wiz0_refclk_dig>; 600 assigned-clock-parents = <&k3_clks 292 11>; 601 }; 602 603 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 604 clocks = <&wiz0_refclk_dig>; 605 #clock-cells = <0>; 606 }; 607 608 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 609 clocks = <&wiz0_pll1_refclk>; 610 #clock-cells = <0>; 611 }; 612 613 serdes0: serdes@5000000 { 614 compatible = "ti,sierra-phy-t0"; 615 reg-names = "serdes"; 616 reg = <0x5000000 0x10000>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 #clock-cells = <1>; 620 resets = <&serdes_wiz0 0>; 621 reset-names = "sierra_reset"; 622 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 623 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 624 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 625 "pll0_refclk", "pll1_refclk"; 626 }; 627 }; 628 629 serdes_wiz1: wiz@5010000 { 630 compatible = "ti,j721e-wiz-16g"; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 634 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 635 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 636 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 637 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 638 num-lanes = <2>; 639 #reset-cells = <1>; 640 ranges = <0x5010000 0x0 0x5010000 0x10000>; 641 642 wiz1_pll0_refclk: pll0-refclk { 643 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 644 #clock-cells = <0>; 645 assigned-clocks = <&wiz1_pll0_refclk>; 646 assigned-clock-parents = <&k3_clks 293 13>; 647 }; 648 649 wiz1_pll1_refclk: pll1-refclk { 650 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 651 #clock-cells = <0>; 652 assigned-clocks = <&wiz1_pll1_refclk>; 653 assigned-clock-parents = <&k3_clks 293 0>; 654 }; 655 656 wiz1_refclk_dig: refclk-dig { 657 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 658 #clock-cells = <0>; 659 assigned-clocks = <&wiz1_refclk_dig>; 660 assigned-clock-parents = <&k3_clks 293 13>; 661 }; 662 663 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 664 clocks = <&wiz1_refclk_dig>; 665 #clock-cells = <0>; 666 }; 667 668 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 669 clocks = <&wiz1_pll1_refclk>; 670 #clock-cells = <0>; 671 }; 672 673 serdes1: serdes@5010000 { 674 compatible = "ti,sierra-phy-t0"; 675 reg-names = "serdes"; 676 reg = <0x5010000 0x10000>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 #clock-cells = <1>; 680 resets = <&serdes_wiz1 0>; 681 reset-names = "sierra_reset"; 682 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 683 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 684 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 685 "pll0_refclk", "pll1_refclk"; 686 }; 687 }; 688 689 serdes_wiz2: wiz@5020000 { 690 compatible = "ti,j721e-wiz-16g"; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 694 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 695 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 696 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 697 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 698 num-lanes = <2>; 699 #reset-cells = <1>; 700 ranges = <0x5020000 0x0 0x5020000 0x10000>; 701 702 wiz2_pll0_refclk: pll0-refclk { 703 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 704 #clock-cells = <0>; 705 assigned-clocks = <&wiz2_pll0_refclk>; 706 assigned-clock-parents = <&k3_clks 294 11>; 707 }; 708 709 wiz2_pll1_refclk: pll1-refclk { 710 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 711 #clock-cells = <0>; 712 assigned-clocks = <&wiz2_pll1_refclk>; 713 assigned-clock-parents = <&k3_clks 294 0>; 714 }; 715 716 wiz2_refclk_dig: refclk-dig { 717 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 718 #clock-cells = <0>; 719 assigned-clocks = <&wiz2_refclk_dig>; 720 assigned-clock-parents = <&k3_clks 294 11>; 721 }; 722 723 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 724 clocks = <&wiz2_refclk_dig>; 725 #clock-cells = <0>; 726 }; 727 728 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 729 clocks = <&wiz2_pll1_refclk>; 730 #clock-cells = <0>; 731 }; 732 733 serdes2: serdes@5020000 { 734 compatible = "ti,sierra-phy-t0"; 735 reg-names = "serdes"; 736 reg = <0x5020000 0x10000>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 #clock-cells = <1>; 740 resets = <&serdes_wiz2 0>; 741 reset-names = "sierra_reset"; 742 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 743 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 744 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 745 "pll0_refclk", "pll1_refclk"; 746 }; 747 }; 748 749 serdes_wiz3: wiz@5030000 { 750 compatible = "ti,j721e-wiz-16g"; 751 #address-cells = <1>; 752 #size-cells = <1>; 753 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 754 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 755 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 756 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 757 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 758 num-lanes = <2>; 759 #reset-cells = <1>; 760 ranges = <0x5030000 0x0 0x5030000 0x10000>; 761 762 wiz3_pll0_refclk: pll0-refclk { 763 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 764 #clock-cells = <0>; 765 assigned-clocks = <&wiz3_pll0_refclk>; 766 assigned-clock-parents = <&k3_clks 295 9>; 767 }; 768 769 wiz3_pll1_refclk: pll1-refclk { 770 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 771 #clock-cells = <0>; 772 assigned-clocks = <&wiz3_pll1_refclk>; 773 assigned-clock-parents = <&k3_clks 295 0>; 774 }; 775 776 wiz3_refclk_dig: refclk-dig { 777 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 778 #clock-cells = <0>; 779 assigned-clocks = <&wiz3_refclk_dig>; 780 assigned-clock-parents = <&k3_clks 295 9>; 781 }; 782 783 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 784 clocks = <&wiz3_refclk_dig>; 785 #clock-cells = <0>; 786 }; 787 788 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 789 clocks = <&wiz3_pll1_refclk>; 790 #clock-cells = <0>; 791 }; 792 793 serdes3: serdes@5030000 { 794 compatible = "ti,sierra-phy-t0"; 795 reg-names = "serdes"; 796 reg = <0x5030000 0x10000>; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 #clock-cells = <1>; 800 resets = <&serdes_wiz3 0>; 801 reset-names = "sierra_reset"; 802 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 803 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 804 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 805 "pll0_refclk", "pll1_refclk"; 806 }; 807 }; 808 809 pcie0_rc: pcie@2900000 { 810 compatible = "ti,j721e-pcie-host"; 811 reg = <0x00 0x02900000 0x00 0x1000>, 812 <0x00 0x02907000 0x00 0x400>, 813 <0x00 0x0d000000 0x00 0x00800000>, 814 <0x00 0x10000000 0x00 0x00001000>; 815 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 816 interrupt-names = "link_state"; 817 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 818 device_type = "pci"; 819 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 820 max-link-speed = <3>; 821 num-lanes = <2>; 822 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 823 clocks = <&k3_clks 239 1>; 824 clock-names = "fck"; 825 #address-cells = <3>; 826 #size-cells = <2>; 827 bus-range = <0x0 0xff>; 828 vendor-id = <0x104c>; 829 device-id = <0xb00d>; 830 msi-map = <0x0 &gic_its 0x0 0x10000>; 831 dma-coherent; 832 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 833 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 834 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 835 status = "disabled"; 836 }; 837 838 pcie1_rc: pcie@2910000 { 839 compatible = "ti,j721e-pcie-host"; 840 reg = <0x00 0x02910000 0x00 0x1000>, 841 <0x00 0x02917000 0x00 0x400>, 842 <0x00 0x0d800000 0x00 0x00800000>, 843 <0x00 0x18000000 0x00 0x00001000>; 844 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 845 interrupt-names = "link_state"; 846 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 847 device_type = "pci"; 848 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 849 max-link-speed = <3>; 850 num-lanes = <2>; 851 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 852 clocks = <&k3_clks 240 1>; 853 clock-names = "fck"; 854 #address-cells = <3>; 855 #size-cells = <2>; 856 bus-range = <0x0 0xff>; 857 vendor-id = <0x104c>; 858 device-id = <0xb00d>; 859 msi-map = <0x0 &gic_its 0x10000 0x10000>; 860 dma-coherent; 861 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 862 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 863 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 864 status = "disabled"; 865 }; 866 867 pcie2_rc: pcie@2920000 { 868 compatible = "ti,j721e-pcie-host"; 869 reg = <0x00 0x02920000 0x00 0x1000>, 870 <0x00 0x02927000 0x00 0x400>, 871 <0x00 0x0e000000 0x00 0x00800000>, 872 <0x44 0x00000000 0x00 0x00001000>; 873 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 874 interrupt-names = "link_state"; 875 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 876 device_type = "pci"; 877 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 878 max-link-speed = <3>; 879 num-lanes = <2>; 880 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 881 clocks = <&k3_clks 241 1>; 882 clock-names = "fck"; 883 #address-cells = <3>; 884 #size-cells = <2>; 885 bus-range = <0x0 0xff>; 886 vendor-id = <0x104c>; 887 device-id = <0xb00d>; 888 msi-map = <0x0 &gic_its 0x20000 0x10000>; 889 dma-coherent; 890 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 891 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 892 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 893 status = "disabled"; 894 }; 895 896 pcie3_rc: pcie@2930000 { 897 compatible = "ti,j721e-pcie-host"; 898 reg = <0x00 0x02930000 0x00 0x1000>, 899 <0x00 0x02937000 0x00 0x400>, 900 <0x00 0x0e800000 0x00 0x00800000>, 901 <0x44 0x10000000 0x00 0x00001000>; 902 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 903 interrupt-names = "link_state"; 904 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 905 device_type = "pci"; 906 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 907 max-link-speed = <3>; 908 num-lanes = <2>; 909 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&k3_clks 242 1>; 911 clock-names = "fck"; 912 #address-cells = <3>; 913 #size-cells = <2>; 914 bus-range = <0x0 0xff>; 915 vendor-id = <0x104c>; 916 device-id = <0xb00d>; 917 msi-map = <0x0 &gic_its 0x30000 0x10000>; 918 dma-coherent; 919 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 920 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 921 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 922 status = "disabled"; 923 }; 924 925 serdes_wiz4: wiz@5050000 { 926 compatible = "ti,am64-wiz-10g"; 927 #address-cells = <1>; 928 #size-cells = <1>; 929 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 931 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 932 assigned-clocks = <&k3_clks 297 9>; 933 assigned-clock-parents = <&k3_clks 297 10>; 934 assigned-clock-rates = <19200000>; 935 num-lanes = <4>; 936 #reset-cells = <1>; 937 #clock-cells = <1>; 938 ranges = <0x05050000 0x00 0x05050000 0x010000>, 939 <0x0a030a00 0x00 0x0a030a00 0x40>; 940 941 serdes4: serdes@5050000 { 942 /* 943 * Note: we also map DPTX PHY registers as the Torrent 944 * needs to manage those. 945 */ 946 compatible = "ti,j721e-serdes-10g"; 947 reg = <0x05050000 0x010000>, 948 <0x0a030a00 0x40>; /* DPTX PHY */ 949 reg-names = "torrent_phy", "dptx_phy"; 950 951 resets = <&serdes_wiz4 0>; 952 reset-names = "torrent_reset"; 953 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 954 clock-names = "refclk"; 955 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 956 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 957 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 958 assigned-clock-parents = <&k3_clks 297 9>, 959 <&k3_clks 297 9>, 960 <&k3_clks 297 9>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 }; 964 }; 965 966 main_timer0: timer@2400000 { 967 compatible = "ti,am654-timer"; 968 reg = <0x00 0x2400000 0x00 0x400>; 969 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&k3_clks 49 1>; 971 clock-names = "fck"; 972 assigned-clocks = <&k3_clks 49 1>; 973 assigned-clock-parents = <&k3_clks 49 2>; 974 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 975 ti,timer-pwm; 976 }; 977 978 main_timer1: timer@2410000 { 979 compatible = "ti,am654-timer"; 980 reg = <0x00 0x2410000 0x00 0x400>; 981 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&k3_clks 50 1>; 983 clock-names = "fck"; 984 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; 985 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; 986 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 987 ti,timer-pwm; 988 }; 989 990 main_timer2: timer@2420000 { 991 compatible = "ti,am654-timer"; 992 reg = <0x00 0x2420000 0x00 0x400>; 993 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&k3_clks 51 1>; 995 clock-names = "fck"; 996 assigned-clocks = <&k3_clks 51 1>; 997 assigned-clock-parents = <&k3_clks 51 2>; 998 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 999 ti,timer-pwm; 1000 }; 1001 1002 main_timer3: timer@2430000 { 1003 compatible = "ti,am654-timer"; 1004 reg = <0x00 0x2430000 0x00 0x400>; 1005 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&k3_clks 52 1>; 1007 clock-names = "fck"; 1008 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; 1009 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; 1010 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1011 ti,timer-pwm; 1012 }; 1013 1014 main_timer4: timer@2440000 { 1015 compatible = "ti,am654-timer"; 1016 reg = <0x00 0x2440000 0x00 0x400>; 1017 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&k3_clks 53 1>; 1019 clock-names = "fck"; 1020 assigned-clocks = <&k3_clks 53 1>; 1021 assigned-clock-parents = <&k3_clks 53 2>; 1022 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1023 ti,timer-pwm; 1024 }; 1025 1026 main_timer5: timer@2450000 { 1027 compatible = "ti,am654-timer"; 1028 reg = <0x00 0x2450000 0x00 0x400>; 1029 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&k3_clks 54 1>; 1031 clock-names = "fck"; 1032 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; 1033 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; 1034 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1035 ti,timer-pwm; 1036 }; 1037 1038 main_timer6: timer@2460000 { 1039 compatible = "ti,am654-timer"; 1040 reg = <0x00 0x2460000 0x00 0x400>; 1041 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&k3_clks 55 1>; 1043 clock-names = "fck"; 1044 assigned-clocks = <&k3_clks 55 1>; 1045 assigned-clock-parents = <&k3_clks 55 2>; 1046 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1047 ti,timer-pwm; 1048 }; 1049 1050 main_timer7: timer@2470000 { 1051 compatible = "ti,am654-timer"; 1052 reg = <0x00 0x2470000 0x00 0x400>; 1053 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&k3_clks 57 1>; 1055 clock-names = "fck"; 1056 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; 1057 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; 1058 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1059 ti,timer-pwm; 1060 }; 1061 1062 main_timer8: timer@2480000 { 1063 compatible = "ti,am654-timer"; 1064 reg = <0x00 0x2480000 0x00 0x400>; 1065 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&k3_clks 58 1>; 1067 clock-names = "fck"; 1068 assigned-clocks = <&k3_clks 58 1>; 1069 assigned-clock-parents = <&k3_clks 58 2>; 1070 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1071 ti,timer-pwm; 1072 }; 1073 1074 main_timer9: timer@2490000 { 1075 compatible = "ti,am654-timer"; 1076 reg = <0x00 0x2490000 0x00 0x400>; 1077 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&k3_clks 59 1>; 1079 clock-names = "fck"; 1080 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; 1081 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; 1082 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1083 ti,timer-pwm; 1084 }; 1085 1086 main_timer10: timer@24a0000 { 1087 compatible = "ti,am654-timer"; 1088 reg = <0x00 0x24a0000 0x00 0x400>; 1089 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&k3_clks 60 1>; 1091 clock-names = "fck"; 1092 assigned-clocks = <&k3_clks 60 1>; 1093 assigned-clock-parents = <&k3_clks 60 2>; 1094 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1095 ti,timer-pwm; 1096 }; 1097 1098 main_timer11: timer@24b0000 { 1099 compatible = "ti,am654-timer"; 1100 reg = <0x00 0x24b0000 0x00 0x400>; 1101 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&k3_clks 62 1>; 1103 clock-names = "fck"; 1104 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; 1105 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; 1106 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1107 ti,timer-pwm; 1108 }; 1109 1110 main_timer12: timer@24c0000 { 1111 compatible = "ti,am654-timer"; 1112 reg = <0x00 0x24c0000 0x00 0x400>; 1113 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&k3_clks 63 1>; 1115 clock-names = "fck"; 1116 assigned-clocks = <&k3_clks 63 1>; 1117 assigned-clock-parents = <&k3_clks 63 2>; 1118 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1119 ti,timer-pwm; 1120 }; 1121 1122 main_timer13: timer@24d0000 { 1123 compatible = "ti,am654-timer"; 1124 reg = <0x00 0x24d0000 0x00 0x400>; 1125 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&k3_clks 64 1>; 1127 clock-names = "fck"; 1128 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; 1129 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; 1130 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1131 ti,timer-pwm; 1132 }; 1133 1134 main_timer14: timer@24e0000 { 1135 compatible = "ti,am654-timer"; 1136 reg = <0x00 0x24e0000 0x00 0x400>; 1137 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&k3_clks 65 1>; 1139 clock-names = "fck"; 1140 assigned-clocks = <&k3_clks 65 1>; 1141 assigned-clock-parents = <&k3_clks 65 2>; 1142 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1143 ti,timer-pwm; 1144 }; 1145 1146 main_timer15: timer@24f0000 { 1147 compatible = "ti,am654-timer"; 1148 reg = <0x00 0x24f0000 0x00 0x400>; 1149 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&k3_clks 66 1>; 1151 clock-names = "fck"; 1152 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; 1153 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; 1154 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1155 ti,timer-pwm; 1156 }; 1157 1158 main_timer16: timer@2500000 { 1159 compatible = "ti,am654-timer"; 1160 reg = <0x00 0x2500000 0x00 0x400>; 1161 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&k3_clks 67 1>; 1163 clock-names = "fck"; 1164 assigned-clocks = <&k3_clks 67 1>; 1165 assigned-clock-parents = <&k3_clks 67 2>; 1166 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1167 ti,timer-pwm; 1168 }; 1169 1170 main_timer17: timer@2510000 { 1171 compatible = "ti,am654-timer"; 1172 reg = <0x00 0x2510000 0x00 0x400>; 1173 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&k3_clks 68 1>; 1175 clock-names = "fck"; 1176 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; 1177 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; 1178 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1179 ti,timer-pwm; 1180 }; 1181 1182 main_timer18: timer@2520000 { 1183 compatible = "ti,am654-timer"; 1184 reg = <0x00 0x2520000 0x00 0x400>; 1185 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&k3_clks 69 1>; 1187 clock-names = "fck"; 1188 assigned-clocks = <&k3_clks 69 1>; 1189 assigned-clock-parents = <&k3_clks 69 2>; 1190 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1191 ti,timer-pwm; 1192 }; 1193 1194 main_timer19: timer@2530000 { 1195 compatible = "ti,am654-timer"; 1196 reg = <0x00 0x2530000 0x00 0x400>; 1197 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&k3_clks 70 1>; 1199 clock-names = "fck"; 1200 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; 1201 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; 1202 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1203 ti,timer-pwm; 1204 }; 1205 1206 main_uart0: serial@2800000 { 1207 compatible = "ti,j721e-uart", "ti,am654-uart"; 1208 reg = <0x00 0x02800000 0x00 0x100>; 1209 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1210 clock-frequency = <48000000>; 1211 current-speed = <115200>; 1212 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 1213 clocks = <&k3_clks 146 0>; 1214 clock-names = "fclk"; 1215 status = "disabled"; 1216 }; 1217 1218 main_uart1: serial@2810000 { 1219 compatible = "ti,j721e-uart", "ti,am654-uart"; 1220 reg = <0x00 0x02810000 0x00 0x100>; 1221 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1222 clock-frequency = <48000000>; 1223 current-speed = <115200>; 1224 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1225 clocks = <&k3_clks 278 0>; 1226 clock-names = "fclk"; 1227 status = "disabled"; 1228 }; 1229 1230 main_uart2: serial@2820000 { 1231 compatible = "ti,j721e-uart", "ti,am654-uart"; 1232 reg = <0x00 0x02820000 0x00 0x100>; 1233 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1234 clock-frequency = <48000000>; 1235 current-speed = <115200>; 1236 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 1237 clocks = <&k3_clks 279 0>; 1238 clock-names = "fclk"; 1239 status = "disabled"; 1240 }; 1241 1242 main_uart3: serial@2830000 { 1243 compatible = "ti,j721e-uart", "ti,am654-uart"; 1244 reg = <0x00 0x02830000 0x00 0x100>; 1245 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1246 clock-frequency = <48000000>; 1247 current-speed = <115200>; 1248 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 1249 clocks = <&k3_clks 280 0>; 1250 clock-names = "fclk"; 1251 status = "disabled"; 1252 }; 1253 1254 main_uart4: serial@2840000 { 1255 compatible = "ti,j721e-uart", "ti,am654-uart"; 1256 reg = <0x00 0x02840000 0x00 0x100>; 1257 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1258 clock-frequency = <48000000>; 1259 current-speed = <115200>; 1260 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 1261 clocks = <&k3_clks 281 0>; 1262 clock-names = "fclk"; 1263 status = "disabled"; 1264 }; 1265 1266 main_uart5: serial@2850000 { 1267 compatible = "ti,j721e-uart", "ti,am654-uart"; 1268 reg = <0x00 0x02850000 0x00 0x100>; 1269 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1270 clock-frequency = <48000000>; 1271 current-speed = <115200>; 1272 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1273 clocks = <&k3_clks 282 0>; 1274 clock-names = "fclk"; 1275 status = "disabled"; 1276 }; 1277 1278 main_uart6: serial@2860000 { 1279 compatible = "ti,j721e-uart", "ti,am654-uart"; 1280 reg = <0x00 0x02860000 0x00 0x100>; 1281 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1282 clock-frequency = <48000000>; 1283 current-speed = <115200>; 1284 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1285 clocks = <&k3_clks 283 0>; 1286 clock-names = "fclk"; 1287 status = "disabled"; 1288 }; 1289 1290 main_uart7: serial@2870000 { 1291 compatible = "ti,j721e-uart", "ti,am654-uart"; 1292 reg = <0x00 0x02870000 0x00 0x100>; 1293 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1294 clock-frequency = <48000000>; 1295 current-speed = <115200>; 1296 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1297 clocks = <&k3_clks 284 0>; 1298 clock-names = "fclk"; 1299 status = "disabled"; 1300 }; 1301 1302 main_uart8: serial@2880000 { 1303 compatible = "ti,j721e-uart", "ti,am654-uart"; 1304 reg = <0x00 0x02880000 0x00 0x100>; 1305 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1306 clock-frequency = <48000000>; 1307 current-speed = <115200>; 1308 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1309 clocks = <&k3_clks 285 0>; 1310 clock-names = "fclk"; 1311 status = "disabled"; 1312 }; 1313 1314 main_uart9: serial@2890000 { 1315 compatible = "ti,j721e-uart", "ti,am654-uart"; 1316 reg = <0x00 0x02890000 0x00 0x100>; 1317 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1318 clock-frequency = <48000000>; 1319 current-speed = <115200>; 1320 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1321 clocks = <&k3_clks 286 0>; 1322 clock-names = "fclk"; 1323 status = "disabled"; 1324 }; 1325 1326 main_gpio0: gpio@600000 { 1327 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1328 reg = <0x0 0x00600000 0x0 0x100>; 1329 gpio-controller; 1330 #gpio-cells = <2>; 1331 interrupt-parent = <&main_gpio_intr>; 1332 interrupts = <256>, <257>, <258>, <259>, 1333 <260>, <261>, <262>, <263>; 1334 interrupt-controller; 1335 #interrupt-cells = <2>; 1336 ti,ngpio = <128>; 1337 ti,davinci-gpio-unbanked = <0>; 1338 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1339 clocks = <&k3_clks 105 0>; 1340 clock-names = "gpio"; 1341 }; 1342 1343 main_gpio1: gpio@601000 { 1344 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1345 reg = <0x0 0x00601000 0x0 0x100>; 1346 gpio-controller; 1347 #gpio-cells = <2>; 1348 interrupt-parent = <&main_gpio_intr>; 1349 interrupts = <288>, <289>, <290>; 1350 interrupt-controller; 1351 #interrupt-cells = <2>; 1352 ti,ngpio = <36>; 1353 ti,davinci-gpio-unbanked = <0>; 1354 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1355 clocks = <&k3_clks 106 0>; 1356 clock-names = "gpio"; 1357 }; 1358 1359 main_gpio2: gpio@610000 { 1360 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1361 reg = <0x0 0x00610000 0x0 0x100>; 1362 gpio-controller; 1363 #gpio-cells = <2>; 1364 interrupt-parent = <&main_gpio_intr>; 1365 interrupts = <264>, <265>, <266>, <267>, 1366 <268>, <269>, <270>, <271>; 1367 interrupt-controller; 1368 #interrupt-cells = <2>; 1369 ti,ngpio = <128>; 1370 ti,davinci-gpio-unbanked = <0>; 1371 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1372 clocks = <&k3_clks 107 0>; 1373 clock-names = "gpio"; 1374 }; 1375 1376 main_gpio3: gpio@611000 { 1377 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1378 reg = <0x0 0x00611000 0x0 0x100>; 1379 gpio-controller; 1380 #gpio-cells = <2>; 1381 interrupt-parent = <&main_gpio_intr>; 1382 interrupts = <292>, <293>, <294>; 1383 interrupt-controller; 1384 #interrupt-cells = <2>; 1385 ti,ngpio = <36>; 1386 ti,davinci-gpio-unbanked = <0>; 1387 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1388 clocks = <&k3_clks 108 0>; 1389 clock-names = "gpio"; 1390 }; 1391 1392 main_gpio4: gpio@620000 { 1393 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1394 reg = <0x0 0x00620000 0x0 0x100>; 1395 gpio-controller; 1396 #gpio-cells = <2>; 1397 interrupt-parent = <&main_gpio_intr>; 1398 interrupts = <272>, <273>, <274>, <275>, 1399 <276>, <277>, <278>, <279>; 1400 interrupt-controller; 1401 #interrupt-cells = <2>; 1402 ti,ngpio = <128>; 1403 ti,davinci-gpio-unbanked = <0>; 1404 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1405 clocks = <&k3_clks 109 0>; 1406 clock-names = "gpio"; 1407 }; 1408 1409 main_gpio5: gpio@621000 { 1410 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1411 reg = <0x0 0x00621000 0x0 0x100>; 1412 gpio-controller; 1413 #gpio-cells = <2>; 1414 interrupt-parent = <&main_gpio_intr>; 1415 interrupts = <296>, <297>, <298>; 1416 interrupt-controller; 1417 #interrupt-cells = <2>; 1418 ti,ngpio = <36>; 1419 ti,davinci-gpio-unbanked = <0>; 1420 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1421 clocks = <&k3_clks 110 0>; 1422 clock-names = "gpio"; 1423 }; 1424 1425 main_gpio6: gpio@630000 { 1426 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1427 reg = <0x0 0x00630000 0x0 0x100>; 1428 gpio-controller; 1429 #gpio-cells = <2>; 1430 interrupt-parent = <&main_gpio_intr>; 1431 interrupts = <280>, <281>, <282>, <283>, 1432 <284>, <285>, <286>, <287>; 1433 interrupt-controller; 1434 #interrupt-cells = <2>; 1435 ti,ngpio = <128>; 1436 ti,davinci-gpio-unbanked = <0>; 1437 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1438 clocks = <&k3_clks 111 0>; 1439 clock-names = "gpio"; 1440 }; 1441 1442 main_gpio7: gpio@631000 { 1443 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1444 reg = <0x0 0x00631000 0x0 0x100>; 1445 gpio-controller; 1446 #gpio-cells = <2>; 1447 interrupt-parent = <&main_gpio_intr>; 1448 interrupts = <300>, <301>, <302>; 1449 interrupt-controller; 1450 #interrupt-cells = <2>; 1451 ti,ngpio = <36>; 1452 ti,davinci-gpio-unbanked = <0>; 1453 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1454 clocks = <&k3_clks 112 0>; 1455 clock-names = "gpio"; 1456 }; 1457 1458 main_sdhci0: mmc@4f80000 { 1459 compatible = "ti,j721e-sdhci-8bit"; 1460 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1461 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1462 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1463 clock-names = "clk_ahb", "clk_xin"; 1464 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1465 assigned-clocks = <&k3_clks 91 1>; 1466 assigned-clock-parents = <&k3_clks 91 2>; 1467 bus-width = <8>; 1468 mmc-hs200-1_8v; 1469 mmc-ddr-1_8v; 1470 ti,otap-del-sel-legacy = <0x0>; 1471 ti,otap-del-sel-mmc-hs = <0x0>; 1472 ti,otap-del-sel-ddr52 = <0x5>; 1473 ti,otap-del-sel-hs200 = <0x6>; 1474 ti,otap-del-sel-hs400 = <0x0>; 1475 ti,itap-del-sel-legacy = <0x10>; 1476 ti,itap-del-sel-mmc-hs = <0xa>; 1477 ti,itap-del-sel-ddr52 = <0x3>; 1478 ti,trm-icp = <0x8>; 1479 dma-coherent; 1480 }; 1481 1482 main_sdhci1: mmc@4fb0000 { 1483 compatible = "ti,j721e-sdhci-4bit"; 1484 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1485 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1486 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1487 clock-names = "clk_ahb", "clk_xin"; 1488 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1489 assigned-clocks = <&k3_clks 92 0>; 1490 assigned-clock-parents = <&k3_clks 92 1>; 1491 ti,otap-del-sel-legacy = <0x0>; 1492 ti,otap-del-sel-sd-hs = <0x0>; 1493 ti,otap-del-sel-sdr12 = <0xf>; 1494 ti,otap-del-sel-sdr25 = <0xf>; 1495 ti,otap-del-sel-sdr50 = <0xc>; 1496 ti,otap-del-sel-ddr50 = <0xc>; 1497 ti,otap-del-sel-sdr104 = <0x5>; 1498 ti,itap-del-sel-legacy = <0x0>; 1499 ti,itap-del-sel-sd-hs = <0x0>; 1500 ti,itap-del-sel-sdr12 = <0x0>; 1501 ti,itap-del-sel-sdr25 = <0x0>; 1502 ti,itap-del-sel-ddr50 = <0x2>; 1503 ti,trm-icp = <0x8>; 1504 ti,clkbuf-sel = <0x7>; 1505 dma-coherent; 1506 sdhci-caps-mask = <0x2 0x0>; 1507 }; 1508 1509 main_sdhci2: mmc@4f98000 { 1510 compatible = "ti,j721e-sdhci-4bit"; 1511 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1512 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1514 clock-names = "clk_ahb", "clk_xin"; 1515 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1516 assigned-clocks = <&k3_clks 93 0>; 1517 assigned-clock-parents = <&k3_clks 93 1>; 1518 ti,otap-del-sel-legacy = <0x0>; 1519 ti,otap-del-sel-sd-hs = <0x0>; 1520 ti,otap-del-sel-sdr12 = <0xf>; 1521 ti,otap-del-sel-sdr25 = <0xf>; 1522 ti,otap-del-sel-sdr50 = <0xc>; 1523 ti,otap-del-sel-ddr50 = <0xc>; 1524 ti,otap-del-sel-sdr104 = <0x5>; 1525 ti,itap-del-sel-legacy = <0x0>; 1526 ti,itap-del-sel-sd-hs = <0x0>; 1527 ti,itap-del-sel-sdr12 = <0x0>; 1528 ti,itap-del-sel-sdr25 = <0x0>; 1529 ti,itap-del-sel-ddr50 = <0x2>; 1530 ti,trm-icp = <0x8>; 1531 ti,clkbuf-sel = <0x7>; 1532 dma-coherent; 1533 sdhci-caps-mask = <0x2 0x0>; 1534 }; 1535 1536 usbss0: cdns-usb@4104000 { 1537 compatible = "ti,j721e-usb"; 1538 reg = <0x00 0x4104000 0x00 0x100>; 1539 dma-coherent; 1540 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1541 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1542 clock-names = "ref", "lpm"; 1543 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1544 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1545 #address-cells = <2>; 1546 #size-cells = <2>; 1547 ranges; 1548 1549 usb0: usb@6000000 { 1550 compatible = "cdns,usb3"; 1551 reg = <0x00 0x6000000 0x00 0x10000>, 1552 <0x00 0x6010000 0x00 0x10000>, 1553 <0x00 0x6020000 0x00 0x10000>; 1554 reg-names = "otg", "xhci", "dev"; 1555 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1556 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1557 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1558 interrupt-names = "host", 1559 "peripheral", 1560 "otg"; 1561 maximum-speed = "super-speed"; 1562 dr_mode = "otg"; 1563 }; 1564 }; 1565 1566 usbss1: cdns-usb@4114000 { 1567 compatible = "ti,j721e-usb"; 1568 reg = <0x00 0x4114000 0x00 0x100>; 1569 dma-coherent; 1570 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1571 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1572 clock-names = "ref", "lpm"; 1573 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1574 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1575 #address-cells = <2>; 1576 #size-cells = <2>; 1577 ranges; 1578 1579 usb1: usb@6400000 { 1580 compatible = "cdns,usb3"; 1581 reg = <0x00 0x6400000 0x00 0x10000>, 1582 <0x00 0x6410000 0x00 0x10000>, 1583 <0x00 0x6420000 0x00 0x10000>; 1584 reg-names = "otg", "xhci", "dev"; 1585 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1586 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1587 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1588 interrupt-names = "host", 1589 "peripheral", 1590 "otg"; 1591 maximum-speed = "super-speed"; 1592 dr_mode = "otg"; 1593 }; 1594 }; 1595 1596 main_i2c0: i2c@2000000 { 1597 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1598 reg = <0x0 0x2000000 0x0 0x100>; 1599 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 clock-names = "fck"; 1603 clocks = <&k3_clks 187 0>; 1604 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1605 status = "disabled"; 1606 }; 1607 1608 main_i2c1: i2c@2010000 { 1609 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1610 reg = <0x0 0x2010000 0x0 0x100>; 1611 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 clock-names = "fck"; 1615 clocks = <&k3_clks 188 0>; 1616 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1617 status = "disabled"; 1618 }; 1619 1620 main_i2c2: i2c@2020000 { 1621 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1622 reg = <0x0 0x2020000 0x0 0x100>; 1623 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 clock-names = "fck"; 1627 clocks = <&k3_clks 189 0>; 1628 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1629 status = "disabled"; 1630 }; 1631 1632 main_i2c3: i2c@2030000 { 1633 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1634 reg = <0x0 0x2030000 0x0 0x100>; 1635 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 clock-names = "fck"; 1639 clocks = <&k3_clks 190 0>; 1640 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1641 status = "disabled"; 1642 }; 1643 1644 main_i2c4: i2c@2040000 { 1645 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1646 reg = <0x0 0x2040000 0x0 0x100>; 1647 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 clock-names = "fck"; 1651 clocks = <&k3_clks 191 0>; 1652 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1653 status = "disabled"; 1654 }; 1655 1656 main_i2c5: i2c@2050000 { 1657 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1658 reg = <0x0 0x2050000 0x0 0x100>; 1659 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 clock-names = "fck"; 1663 clocks = <&k3_clks 192 0>; 1664 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1665 status = "disabled"; 1666 }; 1667 1668 main_i2c6: i2c@2060000 { 1669 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1670 reg = <0x0 0x2060000 0x0 0x100>; 1671 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 clock-names = "fck"; 1675 clocks = <&k3_clks 193 0>; 1676 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1677 status = "disabled"; 1678 }; 1679 1680 ufs_wrapper: ufs-wrapper@4e80000 { 1681 compatible = "ti,j721e-ufs"; 1682 reg = <0x0 0x4e80000 0x0 0x100>; 1683 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1684 clocks = <&k3_clks 277 1>; 1685 assigned-clocks = <&k3_clks 277 1>; 1686 assigned-clock-parents = <&k3_clks 277 4>; 1687 ranges; 1688 #address-cells = <2>; 1689 #size-cells = <2>; 1690 1691 ufs@4e84000 { 1692 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1693 reg = <0x0 0x4e84000 0x0 0x10000>; 1694 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1695 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1696 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1697 clock-names = "core_clk", "phy_clk", "ref_clk"; 1698 dma-coherent; 1699 }; 1700 }; 1701 1702 mhdp: dp-bridge@a000000 { 1703 compatible = "ti,j721e-mhdp8546"; 1704 /* 1705 * Note: we do not map DPTX PHY area, as that is handled by 1706 * the PHY driver. 1707 */ 1708 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1709 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1710 reg-names = "mhdptx", "j721e-intg"; 1711 1712 clocks = <&k3_clks 151 36>; 1713 1714 interrupt-parent = <&gic500>; 1715 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1716 1717 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1718 1719 dp0_ports: ports { 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 1723 port@0 { 1724 reg = <0>; 1725 }; 1726 1727 port@4 { 1728 reg = <4>; 1729 }; 1730 }; 1731 }; 1732 1733 dss: dss@4a00000 { 1734 compatible = "ti,j721e-dss"; 1735 reg = 1736 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1737 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1738 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1739 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1740 1741 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1742 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1743 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1744 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1745 1746 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1747 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1748 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1749 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1750 1751 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1752 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1753 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1754 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1755 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1756 1757 reg-names = "common_m", "common_s0", 1758 "common_s1", "common_s2", 1759 "vidl1", "vidl2","vid1","vid2", 1760 "ovr1", "ovr2", "ovr3", "ovr4", 1761 "vp1", "vp2", "vp3", "vp4", 1762 "wb"; 1763 1764 clocks = <&k3_clks 152 0>, 1765 <&k3_clks 152 1>, 1766 <&k3_clks 152 4>, 1767 <&k3_clks 152 9>, 1768 <&k3_clks 152 13>; 1769 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1770 1771 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1772 1773 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1777 interrupt-names = "common_m", 1778 "common_s0", 1779 "common_s1", 1780 "common_s2"; 1781 1782 dss_ports: ports { 1783 }; 1784 }; 1785 1786 mcasp0: mcasp@2b00000 { 1787 compatible = "ti,am33xx-mcasp-audio"; 1788 reg = <0x0 0x02b00000 0x0 0x2000>, 1789 <0x0 0x02b08000 0x0 0x1000>; 1790 reg-names = "mpu","dat"; 1791 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1793 interrupt-names = "tx", "rx"; 1794 1795 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1796 dma-names = "tx", "rx"; 1797 1798 clocks = <&k3_clks 174 1>; 1799 clock-names = "fck"; 1800 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1801 status = "disabled"; 1802 }; 1803 1804 mcasp1: mcasp@2b10000 { 1805 compatible = "ti,am33xx-mcasp-audio"; 1806 reg = <0x0 0x02b10000 0x0 0x2000>, 1807 <0x0 0x02b18000 0x0 0x1000>; 1808 reg-names = "mpu","dat"; 1809 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1811 interrupt-names = "tx", "rx"; 1812 1813 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1814 dma-names = "tx", "rx"; 1815 1816 clocks = <&k3_clks 175 1>; 1817 clock-names = "fck"; 1818 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1819 status = "disabled"; 1820 }; 1821 1822 mcasp2: mcasp@2b20000 { 1823 compatible = "ti,am33xx-mcasp-audio"; 1824 reg = <0x0 0x02b20000 0x0 0x2000>, 1825 <0x0 0x02b28000 0x0 0x1000>; 1826 reg-names = "mpu","dat"; 1827 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1829 interrupt-names = "tx", "rx"; 1830 1831 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1832 dma-names = "tx", "rx"; 1833 1834 clocks = <&k3_clks 176 1>; 1835 clock-names = "fck"; 1836 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1837 status = "disabled"; 1838 }; 1839 1840 mcasp3: mcasp@2b30000 { 1841 compatible = "ti,am33xx-mcasp-audio"; 1842 reg = <0x0 0x02b30000 0x0 0x2000>, 1843 <0x0 0x02b38000 0x0 0x1000>; 1844 reg-names = "mpu","dat"; 1845 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1847 interrupt-names = "tx", "rx"; 1848 1849 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1850 dma-names = "tx", "rx"; 1851 1852 clocks = <&k3_clks 177 1>; 1853 clock-names = "fck"; 1854 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1855 status = "disabled"; 1856 }; 1857 1858 mcasp4: mcasp@2b40000 { 1859 compatible = "ti,am33xx-mcasp-audio"; 1860 reg = <0x0 0x02b40000 0x0 0x2000>, 1861 <0x0 0x02b48000 0x0 0x1000>; 1862 reg-names = "mpu","dat"; 1863 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1865 interrupt-names = "tx", "rx"; 1866 1867 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1868 dma-names = "tx", "rx"; 1869 1870 clocks = <&k3_clks 178 1>; 1871 clock-names = "fck"; 1872 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1873 status = "disabled"; 1874 }; 1875 1876 mcasp5: mcasp@2b50000 { 1877 compatible = "ti,am33xx-mcasp-audio"; 1878 reg = <0x0 0x02b50000 0x0 0x2000>, 1879 <0x0 0x02b58000 0x0 0x1000>; 1880 reg-names = "mpu","dat"; 1881 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1883 interrupt-names = "tx", "rx"; 1884 1885 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1886 dma-names = "tx", "rx"; 1887 1888 clocks = <&k3_clks 179 1>; 1889 clock-names = "fck"; 1890 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1891 status = "disabled"; 1892 }; 1893 1894 mcasp6: mcasp@2b60000 { 1895 compatible = "ti,am33xx-mcasp-audio"; 1896 reg = <0x0 0x02b60000 0x0 0x2000>, 1897 <0x0 0x02b68000 0x0 0x1000>; 1898 reg-names = "mpu","dat"; 1899 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1901 interrupt-names = "tx", "rx"; 1902 1903 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1904 dma-names = "tx", "rx"; 1905 1906 clocks = <&k3_clks 180 1>; 1907 clock-names = "fck"; 1908 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1909 status = "disabled"; 1910 }; 1911 1912 mcasp7: mcasp@2b70000 { 1913 compatible = "ti,am33xx-mcasp-audio"; 1914 reg = <0x0 0x02b70000 0x0 0x2000>, 1915 <0x0 0x02b78000 0x0 0x1000>; 1916 reg-names = "mpu","dat"; 1917 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1919 interrupt-names = "tx", "rx"; 1920 1921 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1922 dma-names = "tx", "rx"; 1923 1924 clocks = <&k3_clks 181 1>; 1925 clock-names = "fck"; 1926 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1927 status = "disabled"; 1928 }; 1929 1930 mcasp8: mcasp@2b80000 { 1931 compatible = "ti,am33xx-mcasp-audio"; 1932 reg = <0x0 0x02b80000 0x0 0x2000>, 1933 <0x0 0x02b88000 0x0 0x1000>; 1934 reg-names = "mpu","dat"; 1935 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1937 interrupt-names = "tx", "rx"; 1938 1939 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1940 dma-names = "tx", "rx"; 1941 1942 clocks = <&k3_clks 182 1>; 1943 clock-names = "fck"; 1944 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1945 status = "disabled"; 1946 }; 1947 1948 mcasp9: mcasp@2b90000 { 1949 compatible = "ti,am33xx-mcasp-audio"; 1950 reg = <0x0 0x02b90000 0x0 0x2000>, 1951 <0x0 0x02b98000 0x0 0x1000>; 1952 reg-names = "mpu","dat"; 1953 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1955 interrupt-names = "tx", "rx"; 1956 1957 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1958 dma-names = "tx", "rx"; 1959 1960 clocks = <&k3_clks 183 1>; 1961 clock-names = "fck"; 1962 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1963 status = "disabled"; 1964 }; 1965 1966 mcasp10: mcasp@2ba0000 { 1967 compatible = "ti,am33xx-mcasp-audio"; 1968 reg = <0x0 0x02ba0000 0x0 0x2000>, 1969 <0x0 0x02ba8000 0x0 0x1000>; 1970 reg-names = "mpu","dat"; 1971 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "tx", "rx"; 1974 1975 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1976 dma-names = "tx", "rx"; 1977 1978 clocks = <&k3_clks 184 1>; 1979 clock-names = "fck"; 1980 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1981 status = "disabled"; 1982 }; 1983 1984 mcasp11: mcasp@2bb0000 { 1985 compatible = "ti,am33xx-mcasp-audio"; 1986 reg = <0x0 0x02bb0000 0x0 0x2000>, 1987 <0x0 0x02bb8000 0x0 0x1000>; 1988 reg-names = "mpu","dat"; 1989 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1991 interrupt-names = "tx", "rx"; 1992 1993 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1994 dma-names = "tx", "rx"; 1995 1996 clocks = <&k3_clks 185 1>; 1997 clock-names = "fck"; 1998 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1999 status = "disabled"; 2000 }; 2001 2002 watchdog0: watchdog@2200000 { 2003 compatible = "ti,j7-rti-wdt"; 2004 reg = <0x0 0x2200000 0x0 0x100>; 2005 clocks = <&k3_clks 252 1>; 2006 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 2007 assigned-clocks = <&k3_clks 252 1>; 2008 assigned-clock-parents = <&k3_clks 252 5>; 2009 }; 2010 2011 watchdog1: watchdog@2210000 { 2012 compatible = "ti,j7-rti-wdt"; 2013 reg = <0x0 0x2210000 0x0 0x100>; 2014 clocks = <&k3_clks 253 1>; 2015 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 2016 assigned-clocks = <&k3_clks 253 1>; 2017 assigned-clock-parents = <&k3_clks 253 5>; 2018 }; 2019 2020 main_r5fss0: r5fss@5c00000 { 2021 compatible = "ti,j721e-r5fss"; 2022 ti,cluster-mode = <1>; 2023 #address-cells = <1>; 2024 #size-cells = <1>; 2025 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2026 <0x5d00000 0x00 0x5d00000 0x20000>; 2027 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 2028 2029 main_r5fss0_core0: r5f@5c00000 { 2030 compatible = "ti,j721e-r5f"; 2031 reg = <0x5c00000 0x00008000>, 2032 <0x5c10000 0x00008000>; 2033 reg-names = "atcm", "btcm"; 2034 ti,sci = <&dmsc>; 2035 ti,sci-dev-id = <245>; 2036 ti,sci-proc-ids = <0x06 0xff>; 2037 resets = <&k3_reset 245 1>; 2038 firmware-name = "j7-main-r5f0_0-fw"; 2039 ti,atcm-enable = <1>; 2040 ti,btcm-enable = <1>; 2041 ti,loczrama = <1>; 2042 }; 2043 2044 main_r5fss0_core1: r5f@5d00000 { 2045 compatible = "ti,j721e-r5f"; 2046 reg = <0x5d00000 0x00008000>, 2047 <0x5d10000 0x00008000>; 2048 reg-names = "atcm", "btcm"; 2049 ti,sci = <&dmsc>; 2050 ti,sci-dev-id = <246>; 2051 ti,sci-proc-ids = <0x07 0xff>; 2052 resets = <&k3_reset 246 1>; 2053 firmware-name = "j7-main-r5f0_1-fw"; 2054 ti,atcm-enable = <1>; 2055 ti,btcm-enable = <1>; 2056 ti,loczrama = <1>; 2057 }; 2058 }; 2059 2060 main_r5fss1: r5fss@5e00000 { 2061 compatible = "ti,j721e-r5fss"; 2062 ti,cluster-mode = <1>; 2063 #address-cells = <1>; 2064 #size-cells = <1>; 2065 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2066 <0x5f00000 0x00 0x5f00000 0x20000>; 2067 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 2068 2069 main_r5fss1_core0: r5f@5e00000 { 2070 compatible = "ti,j721e-r5f"; 2071 reg = <0x5e00000 0x00008000>, 2072 <0x5e10000 0x00008000>; 2073 reg-names = "atcm", "btcm"; 2074 ti,sci = <&dmsc>; 2075 ti,sci-dev-id = <247>; 2076 ti,sci-proc-ids = <0x08 0xff>; 2077 resets = <&k3_reset 247 1>; 2078 firmware-name = "j7-main-r5f1_0-fw"; 2079 ti,atcm-enable = <1>; 2080 ti,btcm-enable = <1>; 2081 ti,loczrama = <1>; 2082 }; 2083 2084 main_r5fss1_core1: r5f@5f00000 { 2085 compatible = "ti,j721e-r5f"; 2086 reg = <0x5f00000 0x00008000>, 2087 <0x5f10000 0x00008000>; 2088 reg-names = "atcm", "btcm"; 2089 ti,sci = <&dmsc>; 2090 ti,sci-dev-id = <248>; 2091 ti,sci-proc-ids = <0x09 0xff>; 2092 resets = <&k3_reset 248 1>; 2093 firmware-name = "j7-main-r5f1_1-fw"; 2094 ti,atcm-enable = <1>; 2095 ti,btcm-enable = <1>; 2096 ti,loczrama = <1>; 2097 }; 2098 }; 2099 2100 c66_0: dsp@4d80800000 { 2101 compatible = "ti,j721e-c66-dsp"; 2102 reg = <0x4d 0x80800000 0x00 0x00048000>, 2103 <0x4d 0x80e00000 0x00 0x00008000>, 2104 <0x4d 0x80f00000 0x00 0x00008000>; 2105 reg-names = "l2sram", "l1pram", "l1dram"; 2106 ti,sci = <&dmsc>; 2107 ti,sci-dev-id = <142>; 2108 ti,sci-proc-ids = <0x03 0xff>; 2109 resets = <&k3_reset 142 1>; 2110 firmware-name = "j7-c66_0-fw"; 2111 }; 2112 2113 c66_1: dsp@4d81800000 { 2114 compatible = "ti,j721e-c66-dsp"; 2115 reg = <0x4d 0x81800000 0x00 0x00048000>, 2116 <0x4d 0x81e00000 0x00 0x00008000>, 2117 <0x4d 0x81f00000 0x00 0x00008000>; 2118 reg-names = "l2sram", "l1pram", "l1dram"; 2119 ti,sci = <&dmsc>; 2120 ti,sci-dev-id = <143>; 2121 ti,sci-proc-ids = <0x04 0xff>; 2122 resets = <&k3_reset 143 1>; 2123 firmware-name = "j7-c66_1-fw"; 2124 }; 2125 2126 c71_0: dsp@64800000 { 2127 compatible = "ti,j721e-c71-dsp"; 2128 reg = <0x00 0x64800000 0x00 0x00080000>, 2129 <0x00 0x64e00000 0x00 0x0000c000>; 2130 reg-names = "l2sram", "l1dram"; 2131 ti,sci = <&dmsc>; 2132 ti,sci-dev-id = <15>; 2133 ti,sci-proc-ids = <0x30 0xff>; 2134 resets = <&k3_reset 15 1>; 2135 firmware-name = "j7-c71_0-fw"; 2136 }; 2137 2138 icssg0: icssg@b000000 { 2139 compatible = "ti,j721e-icssg"; 2140 reg = <0x00 0xb000000 0x00 0x80000>; 2141 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 2142 #address-cells = <1>; 2143 #size-cells = <1>; 2144 ranges = <0x0 0x00 0x0b000000 0x100000>; 2145 2146 icssg0_mem: memories@0 { 2147 reg = <0x0 0x2000>, 2148 <0x2000 0x2000>, 2149 <0x10000 0x10000>; 2150 reg-names = "dram0", "dram1", 2151 "shrdram2"; 2152 }; 2153 2154 icssg0_cfg: cfg@26000 { 2155 compatible = "ti,pruss-cfg", "syscon"; 2156 reg = <0x26000 0x200>; 2157 #address-cells = <1>; 2158 #size-cells = <1>; 2159 ranges = <0x0 0x26000 0x2000>; 2160 2161 clocks { 2162 #address-cells = <1>; 2163 #size-cells = <0>; 2164 2165 icssg0_coreclk_mux: coreclk-mux@3c { 2166 reg = <0x3c>; 2167 #clock-cells = <0>; 2168 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 2169 <&k3_clks 119 1>; /* icssg0_iclk */ 2170 assigned-clocks = <&icssg0_coreclk_mux>; 2171 assigned-clock-parents = <&k3_clks 119 1>; 2172 }; 2173 2174 icssg0_iepclk_mux: iepclk-mux@30 { 2175 reg = <0x30>; 2176 #clock-cells = <0>; 2177 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 2178 <&icssg0_coreclk_mux>; /* core_clk */ 2179 assigned-clocks = <&icssg0_iepclk_mux>; 2180 assigned-clock-parents = <&icssg0_coreclk_mux>; 2181 }; 2182 }; 2183 }; 2184 2185 icssg0_mii_rt: mii-rt@32000 { 2186 compatible = "ti,pruss-mii", "syscon"; 2187 reg = <0x32000 0x100>; 2188 }; 2189 2190 icssg0_mii_g_rt: mii-g-rt@33000 { 2191 compatible = "ti,pruss-mii-g", "syscon"; 2192 reg = <0x33000 0x1000>; 2193 }; 2194 2195 icssg0_intc: interrupt-controller@20000 { 2196 compatible = "ti,icssg-intc"; 2197 reg = <0x20000 0x2000>; 2198 interrupt-controller; 2199 #interrupt-cells = <3>; 2200 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 2208 interrupt-names = "host_intr0", "host_intr1", 2209 "host_intr2", "host_intr3", 2210 "host_intr4", "host_intr5", 2211 "host_intr6", "host_intr7"; 2212 }; 2213 2214 pru0_0: pru@34000 { 2215 compatible = "ti,j721e-pru"; 2216 reg = <0x34000 0x3000>, 2217 <0x22000 0x100>, 2218 <0x22400 0x100>; 2219 reg-names = "iram", "control", "debug"; 2220 firmware-name = "j7-pru0_0-fw"; 2221 }; 2222 2223 rtu0_0: rtu@4000 { 2224 compatible = "ti,j721e-rtu"; 2225 reg = <0x4000 0x2000>, 2226 <0x23000 0x100>, 2227 <0x23400 0x100>; 2228 reg-names = "iram", "control", "debug"; 2229 firmware-name = "j7-rtu0_0-fw"; 2230 }; 2231 2232 tx_pru0_0: txpru@a000 { 2233 compatible = "ti,j721e-tx-pru"; 2234 reg = <0xa000 0x1800>, 2235 <0x25000 0x100>, 2236 <0x25400 0x100>; 2237 reg-names = "iram", "control", "debug"; 2238 firmware-name = "j7-txpru0_0-fw"; 2239 }; 2240 2241 pru0_1: pru@38000 { 2242 compatible = "ti,j721e-pru"; 2243 reg = <0x38000 0x3000>, 2244 <0x24000 0x100>, 2245 <0x24400 0x100>; 2246 reg-names = "iram", "control", "debug"; 2247 firmware-name = "j7-pru0_1-fw"; 2248 }; 2249 2250 rtu0_1: rtu@6000 { 2251 compatible = "ti,j721e-rtu"; 2252 reg = <0x6000 0x2000>, 2253 <0x23800 0x100>, 2254 <0x23c00 0x100>; 2255 reg-names = "iram", "control", "debug"; 2256 firmware-name = "j7-rtu0_1-fw"; 2257 }; 2258 2259 tx_pru0_1: txpru@c000 { 2260 compatible = "ti,j721e-tx-pru"; 2261 reg = <0xc000 0x1800>, 2262 <0x25800 0x100>, 2263 <0x25c00 0x100>; 2264 reg-names = "iram", "control", "debug"; 2265 firmware-name = "j7-txpru0_1-fw"; 2266 }; 2267 2268 icssg0_mdio: mdio@32400 { 2269 compatible = "ti,davinci_mdio"; 2270 reg = <0x32400 0x100>; 2271 clocks = <&k3_clks 119 1>; 2272 clock-names = "fck"; 2273 #address-cells = <1>; 2274 #size-cells = <0>; 2275 bus_freq = <1000000>; 2276 status = "disabled"; 2277 }; 2278 }; 2279 2280 icssg1: icssg@b100000 { 2281 compatible = "ti,j721e-icssg"; 2282 reg = <0x00 0xb100000 0x00 0x80000>; 2283 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2284 #address-cells = <1>; 2285 #size-cells = <1>; 2286 ranges = <0x0 0x00 0x0b100000 0x100000>; 2287 2288 icssg1_mem: memories@b100000 { 2289 reg = <0x0 0x2000>, 2290 <0x2000 0x2000>, 2291 <0x10000 0x10000>; 2292 reg-names = "dram0", "dram1", 2293 "shrdram2"; 2294 }; 2295 2296 icssg1_cfg: cfg@26000 { 2297 compatible = "ti,pruss-cfg", "syscon"; 2298 reg = <0x26000 0x200>; 2299 #address-cells = <1>; 2300 #size-cells = <1>; 2301 ranges = <0x0 0x26000 0x2000>; 2302 2303 clocks { 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 2307 icssg1_coreclk_mux: coreclk-mux@3c { 2308 reg = <0x3c>; 2309 #clock-cells = <0>; 2310 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2311 <&k3_clks 120 4>; /* icssg1_iclk */ 2312 assigned-clocks = <&icssg1_coreclk_mux>; 2313 assigned-clock-parents = <&k3_clks 120 4>; 2314 }; 2315 2316 icssg1_iepclk_mux: iepclk-mux@30 { 2317 reg = <0x30>; 2318 #clock-cells = <0>; 2319 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2320 <&icssg1_coreclk_mux>; /* core_clk */ 2321 assigned-clocks = <&icssg1_iepclk_mux>; 2322 assigned-clock-parents = <&icssg1_coreclk_mux>; 2323 }; 2324 }; 2325 }; 2326 2327 icssg1_mii_rt: mii-rt@32000 { 2328 compatible = "ti,pruss-mii", "syscon"; 2329 reg = <0x32000 0x100>; 2330 }; 2331 2332 icssg1_mii_g_rt: mii-g-rt@33000 { 2333 compatible = "ti,pruss-mii-g", "syscon"; 2334 reg = <0x33000 0x1000>; 2335 }; 2336 2337 icssg1_intc: interrupt-controller@20000 { 2338 compatible = "ti,icssg-intc"; 2339 reg = <0x20000 0x2000>; 2340 interrupt-controller; 2341 #interrupt-cells = <3>; 2342 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2343 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2344 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2350 interrupt-names = "host_intr0", "host_intr1", 2351 "host_intr2", "host_intr3", 2352 "host_intr4", "host_intr5", 2353 "host_intr6", "host_intr7"; 2354 }; 2355 2356 pru1_0: pru@34000 { 2357 compatible = "ti,j721e-pru"; 2358 reg = <0x34000 0x4000>, 2359 <0x22000 0x100>, 2360 <0x22400 0x100>; 2361 reg-names = "iram", "control", "debug"; 2362 firmware-name = "j7-pru1_0-fw"; 2363 }; 2364 2365 rtu1_0: rtu@4000 { 2366 compatible = "ti,j721e-rtu"; 2367 reg = <0x4000 0x2000>, 2368 <0x23000 0x100>, 2369 <0x23400 0x100>; 2370 reg-names = "iram", "control", "debug"; 2371 firmware-name = "j7-rtu1_0-fw"; 2372 }; 2373 2374 tx_pru1_0: txpru@a000 { 2375 compatible = "ti,j721e-tx-pru"; 2376 reg = <0xa000 0x1800>, 2377 <0x25000 0x100>, 2378 <0x25400 0x100>; 2379 reg-names = "iram", "control", "debug"; 2380 firmware-name = "j7-txpru1_0-fw"; 2381 }; 2382 2383 pru1_1: pru@38000 { 2384 compatible = "ti,j721e-pru"; 2385 reg = <0x38000 0x4000>, 2386 <0x24000 0x100>, 2387 <0x24400 0x100>; 2388 reg-names = "iram", "control", "debug"; 2389 firmware-name = "j7-pru1_1-fw"; 2390 }; 2391 2392 rtu1_1: rtu@6000 { 2393 compatible = "ti,j721e-rtu"; 2394 reg = <0x6000 0x2000>, 2395 <0x23800 0x100>, 2396 <0x23c00 0x100>; 2397 reg-names = "iram", "control", "debug"; 2398 firmware-name = "j7-rtu1_1-fw"; 2399 }; 2400 2401 tx_pru1_1: txpru@c000 { 2402 compatible = "ti,j721e-tx-pru"; 2403 reg = <0xc000 0x1800>, 2404 <0x25800 0x100>, 2405 <0x25c00 0x100>; 2406 reg-names = "iram", "control", "debug"; 2407 firmware-name = "j7-txpru1_1-fw"; 2408 }; 2409 2410 icssg1_mdio: mdio@32400 { 2411 compatible = "ti,davinci_mdio"; 2412 reg = <0x32400 0x100>; 2413 clocks = <&k3_clks 120 4>; 2414 clock-names = "fck"; 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 bus_freq = <1000000>; 2418 status = "disabled"; 2419 }; 2420 }; 2421 2422 main_mcan0: can@2701000 { 2423 compatible = "bosch,m_can"; 2424 reg = <0x00 0x02701000 0x00 0x200>, 2425 <0x00 0x02708000 0x00 0x8000>; 2426 reg-names = "m_can", "message_ram"; 2427 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2428 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2429 clock-names = "hclk", "cclk"; 2430 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2432 interrupt-names = "int0", "int1"; 2433 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2434 status = "disabled"; 2435 }; 2436 2437 main_mcan1: can@2711000 { 2438 compatible = "bosch,m_can"; 2439 reg = <0x00 0x02711000 0x00 0x200>, 2440 <0x00 0x02718000 0x00 0x8000>; 2441 reg-names = "m_can", "message_ram"; 2442 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2443 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2444 clock-names = "hclk", "cclk"; 2445 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2447 interrupt-names = "int0", "int1"; 2448 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2449 status = "disabled"; 2450 }; 2451 2452 main_mcan2: can@2721000 { 2453 compatible = "bosch,m_can"; 2454 reg = <0x00 0x02721000 0x00 0x200>, 2455 <0x00 0x02728000 0x00 0x8000>; 2456 reg-names = "m_can", "message_ram"; 2457 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2458 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2459 clock-names = "hclk", "cclk"; 2460 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2462 interrupt-names = "int0", "int1"; 2463 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2464 status = "disabled"; 2465 }; 2466 2467 main_mcan3: can@2731000 { 2468 compatible = "bosch,m_can"; 2469 reg = <0x00 0x02731000 0x00 0x200>, 2470 <0x00 0x02738000 0x00 0x8000>; 2471 reg-names = "m_can", "message_ram"; 2472 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2473 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2474 clock-names = "hclk", "cclk"; 2475 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2477 interrupt-names = "int0", "int1"; 2478 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2479 status = "disabled"; 2480 }; 2481 2482 main_mcan4: can@2741000 { 2483 compatible = "bosch,m_can"; 2484 reg = <0x00 0x02741000 0x00 0x200>, 2485 <0x00 0x02748000 0x00 0x8000>; 2486 reg-names = "m_can", "message_ram"; 2487 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2488 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2489 clock-names = "hclk", "cclk"; 2490 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2492 interrupt-names = "int0", "int1"; 2493 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2494 status = "disabled"; 2495 }; 2496 2497 main_mcan5: can@2751000 { 2498 compatible = "bosch,m_can"; 2499 reg = <0x00 0x02751000 0x00 0x200>, 2500 <0x00 0x02758000 0x00 0x8000>; 2501 reg-names = "m_can", "message_ram"; 2502 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2503 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2504 clock-names = "hclk", "cclk"; 2505 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2507 interrupt-names = "int0", "int1"; 2508 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2509 status = "disabled"; 2510 }; 2511 2512 main_mcan6: can@2761000 { 2513 compatible = "bosch,m_can"; 2514 reg = <0x00 0x02761000 0x00 0x200>, 2515 <0x00 0x02768000 0x00 0x8000>; 2516 reg-names = "m_can", "message_ram"; 2517 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2518 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2519 clock-names = "hclk", "cclk"; 2520 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2522 interrupt-names = "int0", "int1"; 2523 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2524 status = "disabled"; 2525 }; 2526 2527 main_mcan7: can@2771000 { 2528 compatible = "bosch,m_can"; 2529 reg = <0x00 0x02771000 0x00 0x200>, 2530 <0x00 0x02778000 0x00 0x8000>; 2531 reg-names = "m_can", "message_ram"; 2532 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2533 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2534 clock-names = "hclk", "cclk"; 2535 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2537 interrupt-names = "int0", "int1"; 2538 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2539 status = "disabled"; 2540 }; 2541 2542 main_mcan8: can@2781000 { 2543 compatible = "bosch,m_can"; 2544 reg = <0x00 0x02781000 0x00 0x200>, 2545 <0x00 0x02788000 0x00 0x8000>; 2546 reg-names = "m_can", "message_ram"; 2547 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2548 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2549 clock-names = "hclk", "cclk"; 2550 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2552 interrupt-names = "int0", "int1"; 2553 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2554 status = "disabled"; 2555 }; 2556 2557 main_mcan9: can@2791000 { 2558 compatible = "bosch,m_can"; 2559 reg = <0x00 0x02791000 0x00 0x200>, 2560 <0x00 0x02798000 0x00 0x8000>; 2561 reg-names = "m_can", "message_ram"; 2562 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2563 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2564 clock-names = "hclk", "cclk"; 2565 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2567 interrupt-names = "int0", "int1"; 2568 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2569 status = "disabled"; 2570 }; 2571 2572 main_mcan10: can@27a1000 { 2573 compatible = "bosch,m_can"; 2574 reg = <0x00 0x027a1000 0x00 0x200>, 2575 <0x00 0x027a8000 0x00 0x8000>; 2576 reg-names = "m_can", "message_ram"; 2577 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2578 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2579 clock-names = "hclk", "cclk"; 2580 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2582 interrupt-names = "int0", "int1"; 2583 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2584 status = "disabled"; 2585 }; 2586 2587 main_mcan11: can@27b1000 { 2588 compatible = "bosch,m_can"; 2589 reg = <0x00 0x027b1000 0x00 0x200>, 2590 <0x00 0x027b8000 0x00 0x8000>; 2591 reg-names = "m_can", "message_ram"; 2592 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2593 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2594 clock-names = "hclk", "cclk"; 2595 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2597 interrupt-names = "int0", "int1"; 2598 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2599 status = "disabled"; 2600 }; 2601 2602 main_mcan12: can@27c1000 { 2603 compatible = "bosch,m_can"; 2604 reg = <0x00 0x027c1000 0x00 0x200>, 2605 <0x00 0x027c8000 0x00 0x8000>; 2606 reg-names = "m_can", "message_ram"; 2607 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2608 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2609 clock-names = "hclk", "cclk"; 2610 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2612 interrupt-names = "int0", "int1"; 2613 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2614 status = "disabled"; 2615 }; 2616 2617 main_mcan13: can@27d1000 { 2618 compatible = "bosch,m_can"; 2619 reg = <0x00 0x027d1000 0x00 0x200>, 2620 <0x00 0x027d8000 0x00 0x8000>; 2621 reg-names = "m_can", "message_ram"; 2622 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2623 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2624 clock-names = "hclk", "cclk"; 2625 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2627 interrupt-names = "int0", "int1"; 2628 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2629 status = "disabled"; 2630 }; 2631 2632 main_spi0: spi@2100000 { 2633 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2634 reg = <0x00 0x02100000 0x00 0x400>; 2635 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2639 clocks = <&k3_clks 266 1>; 2640 status = "disabled"; 2641 }; 2642 2643 main_spi1: spi@2110000 { 2644 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2645 reg = <0x00 0x02110000 0x00 0x400>; 2646 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2647 #address-cells = <1>; 2648 #size-cells = <0>; 2649 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2650 clocks = <&k3_clks 267 1>; 2651 status = "disabled"; 2652 }; 2653 2654 main_spi2: spi@2120000 { 2655 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2656 reg = <0x00 0x02120000 0x00 0x400>; 2657 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2658 #address-cells = <1>; 2659 #size-cells = <0>; 2660 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2661 clocks = <&k3_clks 268 1>; 2662 status = "disabled"; 2663 }; 2664 2665 main_spi3: spi@2130000 { 2666 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2667 reg = <0x00 0x02130000 0x00 0x400>; 2668 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2669 #address-cells = <1>; 2670 #size-cells = <0>; 2671 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2672 clocks = <&k3_clks 269 1>; 2673 status = "disabled"; 2674 }; 2675 2676 main_spi4: spi@2140000 { 2677 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2678 reg = <0x00 0x02140000 0x00 0x400>; 2679 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2680 #address-cells = <1>; 2681 #size-cells = <0>; 2682 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2683 clocks = <&k3_clks 270 1>; 2684 status = "disabled"; 2685 }; 2686 2687 main_spi5: spi@2150000 { 2688 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2689 reg = <0x00 0x02150000 0x00 0x400>; 2690 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2691 #address-cells = <1>; 2692 #size-cells = <0>; 2693 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2694 clocks = <&k3_clks 271 1>; 2695 status = "disabled"; 2696 }; 2697 2698 main_spi6: spi@2160000 { 2699 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2700 reg = <0x00 0x02160000 0x00 0x400>; 2701 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2702 #address-cells = <1>; 2703 #size-cells = <0>; 2704 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2705 clocks = <&k3_clks 272 1>; 2706 status = "disabled"; 2707 }; 2708 2709 main_spi7: spi@2170000 { 2710 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2711 reg = <0x00 0x02170000 0x00 0x400>; 2712 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2713 #address-cells = <1>; 2714 #size-cells = <0>; 2715 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2716 clocks = <&k3_clks 273 1>; 2717 status = "disabled"; 2718 }; 2719 2720 main_esm: esm@700000 { 2721 compatible = "ti,j721e-esm"; 2722 reg = <0x0 0x700000 0x0 0x1000>; 2723 ti,esm-pins = <344>, <345>; 2724 }; 2725}; 2726