1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10#include <dt-bindings/mux/ti-serdes.h> 11 12/ { 13 cmn_refclk: clock-cmnrefclk { 14 #clock-cells = <0>; 15 compatible = "fixed-clock"; 16 clock-frequency = <0>; 17 }; 18 19 cmn_refclk1: clock-cmnrefclk1 { 20 #clock-cells = <0>; 21 compatible = "fixed-clock"; 22 clock-frequency = <0>; 23 }; 24}; 25 26&cbass_main { 27 msmc_ram: sram@70000000 { 28 compatible = "mmio-sram"; 29 reg = <0x0 0x70000000 0x0 0x800000>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 ranges = <0x0 0x0 0x70000000 0x800000>; 33 34 atf-sram@0 { 35 reg = <0x0 0x20000>; 36 }; 37 }; 38 39 scm_conf: scm-conf@100000 { 40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x0 0x00100000 0x1c000>; 45 46 serdes_ln_ctrl: mux-controller@4080 { 47 compatible = "mmio-mux"; 48 reg = <0x00004080 0x50>; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 51 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 52 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 53 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 54 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 55 /* SERDES4 lane0/1/2/3 select */ 56 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 57 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 58 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 59 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 60 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 61 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 62 }; 63 64 cpsw0_phy_gmii_sel: phy@4044 { 65 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 66 ti,qsgmii-main-ports = <2>, <2>; 67 reg = <0x4044 0x20>; 68 #phy-cells = <1>; 69 }; 70 71 usb_serdes_mux: mux-controller@4000 { 72 compatible = "mmio-mux"; 73 #mux-control-cells = <1>; 74 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 75 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 76 }; 77 78 ehrpwm_tbclk: clock-controller@4140 { 79 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 80 reg = <0x4140 0x18>; 81 #clock-cells = <1>; 82 }; 83 }; 84 85 main_ehrpwm0: pwm@3000000 { 86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 87 #pwm-cells = <3>; 88 reg = <0x00 0x3000000 0x00 0x100>; 89 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 90 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 91 clock-names = "tbclk", "fck"; 92 status = "disabled"; 93 }; 94 95 main_ehrpwm1: pwm@3010000 { 96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 97 #pwm-cells = <3>; 98 reg = <0x00 0x3010000 0x00 0x100>; 99 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 100 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 101 clock-names = "tbclk", "fck"; 102 status = "disabled"; 103 }; 104 105 main_ehrpwm2: pwm@3020000 { 106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 107 #pwm-cells = <3>; 108 reg = <0x00 0x3020000 0x00 0x100>; 109 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 110 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 111 clock-names = "tbclk", "fck"; 112 status = "disabled"; 113 }; 114 115 main_ehrpwm3: pwm@3030000 { 116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 117 #pwm-cells = <3>; 118 reg = <0x00 0x3030000 0x00 0x100>; 119 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 120 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 121 clock-names = "tbclk", "fck"; 122 status = "disabled"; 123 }; 124 125 main_ehrpwm4: pwm@3040000 { 126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 127 #pwm-cells = <3>; 128 reg = <0x00 0x3040000 0x00 0x100>; 129 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 130 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 131 clock-names = "tbclk", "fck"; 132 status = "disabled"; 133 }; 134 135 main_ehrpwm5: pwm@3050000 { 136 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 137 #pwm-cells = <3>; 138 reg = <0x00 0x3050000 0x00 0x100>; 139 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 140 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 141 clock-names = "tbclk", "fck"; 142 status = "disabled"; 143 }; 144 145 gic500: interrupt-controller@1800000 { 146 compatible = "arm,gic-v3"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 153 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 154 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 155 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 156 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 157 158 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 160 161 gic_its: msi-controller@1820000 { 162 compatible = "arm,gic-v3-its"; 163 reg = <0x00 0x01820000 0x00 0x10000>; 164 socionext,synquacer-pre-its = <0x1000000 0x400000>; 165 msi-controller; 166 #msi-cells = <1>; 167 }; 168 }; 169 170 main_gpio_intr: interrupt-controller@a00000 { 171 compatible = "ti,sci-intr"; 172 reg = <0x00 0x00a00000 0x00 0x800>; 173 ti,intr-trigger-type = <1>; 174 interrupt-controller; 175 interrupt-parent = <&gic500>; 176 #interrupt-cells = <1>; 177 ti,sci = <&dmsc>; 178 ti,sci-dev-id = <131>; 179 ti,interrupt-ranges = <8 392 56>; 180 }; 181 182 main_navss: bus@30000000 { 183 compatible = "simple-mfd"; 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 187 dma-coherent; 188 dma-ranges; 189 190 ti,sci-dev-id = <199>; 191 192 main_navss_intr: interrupt-controller@310e0000 { 193 compatible = "ti,sci-intr"; 194 reg = <0x0 0x310e0000 0x0 0x4000>; 195 ti,intr-trigger-type = <4>; 196 interrupt-controller; 197 interrupt-parent = <&gic500>; 198 #interrupt-cells = <1>; 199 ti,sci = <&dmsc>; 200 ti,sci-dev-id = <213>; 201 ti,interrupt-ranges = <0 64 64>, 202 <64 448 64>, 203 <128 672 64>; 204 }; 205 206 main_udmass_inta: interrupt-controller@33d00000 { 207 compatible = "ti,sci-inta"; 208 reg = <0x0 0x33d00000 0x0 0x100000>; 209 interrupt-controller; 210 interrupt-parent = <&main_navss_intr>; 211 msi-controller; 212 #interrupt-cells = <0>; 213 ti,sci = <&dmsc>; 214 ti,sci-dev-id = <209>; 215 ti,interrupt-ranges = <0 0 256>; 216 }; 217 218 secure_proxy_main: mailbox@32c00000 { 219 compatible = "ti,am654-secure-proxy"; 220 #mbox-cells = <1>; 221 reg-names = "target_data", "rt", "scfg"; 222 reg = <0x00 0x32c00000 0x00 0x100000>, 223 <0x00 0x32400000 0x00 0x100000>, 224 <0x00 0x32800000 0x00 0x100000>; 225 interrupt-names = "rx_011"; 226 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 smmu0: iommu@36600000 { 230 compatible = "arm,smmu-v3"; 231 reg = <0x0 0x36600000 0x0 0x100000>; 232 interrupt-parent = <&gic500>; 233 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 235 interrupt-names = "eventq", "gerror"; 236 #iommu-cells = <1>; 237 }; 238 239 hwspinlock: spinlock@30e00000 { 240 compatible = "ti,am654-hwspinlock"; 241 reg = <0x00 0x30e00000 0x00 0x1000>; 242 #hwlock-cells = <1>; 243 }; 244 245 mailbox0_cluster0: mailbox@31f80000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f80000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster1: mailbox@31f81000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f81000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 mailbox0_cluster2: mailbox@31f82000 { 266 compatible = "ti,am654-mailbox"; 267 reg = <0x00 0x31f82000 0x00 0x200>; 268 #mbox-cells = <1>; 269 ti,mbox-num-users = <4>; 270 ti,mbox-num-fifos = <16>; 271 interrupt-parent = <&main_navss_intr>; 272 status = "disabled"; 273 }; 274 275 mailbox0_cluster3: mailbox@31f83000 { 276 compatible = "ti,am654-mailbox"; 277 reg = <0x00 0x31f83000 0x00 0x200>; 278 #mbox-cells = <1>; 279 ti,mbox-num-users = <4>; 280 ti,mbox-num-fifos = <16>; 281 interrupt-parent = <&main_navss_intr>; 282 status = "disabled"; 283 }; 284 285 mailbox0_cluster4: mailbox@31f84000 { 286 compatible = "ti,am654-mailbox"; 287 reg = <0x00 0x31f84000 0x00 0x200>; 288 #mbox-cells = <1>; 289 ti,mbox-num-users = <4>; 290 ti,mbox-num-fifos = <16>; 291 interrupt-parent = <&main_navss_intr>; 292 status = "disabled"; 293 }; 294 295 mailbox0_cluster5: mailbox@31f85000 { 296 compatible = "ti,am654-mailbox"; 297 reg = <0x00 0x31f85000 0x00 0x200>; 298 #mbox-cells = <1>; 299 ti,mbox-num-users = <4>; 300 ti,mbox-num-fifos = <16>; 301 interrupt-parent = <&main_navss_intr>; 302 status = "disabled"; 303 }; 304 305 mailbox0_cluster6: mailbox@31f86000 { 306 compatible = "ti,am654-mailbox"; 307 reg = <0x00 0x31f86000 0x00 0x200>; 308 #mbox-cells = <1>; 309 ti,mbox-num-users = <4>; 310 ti,mbox-num-fifos = <16>; 311 interrupt-parent = <&main_navss_intr>; 312 status = "disabled"; 313 }; 314 315 mailbox0_cluster7: mailbox@31f87000 { 316 compatible = "ti,am654-mailbox"; 317 reg = <0x00 0x31f87000 0x00 0x200>; 318 #mbox-cells = <1>; 319 ti,mbox-num-users = <4>; 320 ti,mbox-num-fifos = <16>; 321 interrupt-parent = <&main_navss_intr>; 322 status = "disabled"; 323 }; 324 325 mailbox0_cluster8: mailbox@31f88000 { 326 compatible = "ti,am654-mailbox"; 327 reg = <0x00 0x31f88000 0x00 0x200>; 328 #mbox-cells = <1>; 329 ti,mbox-num-users = <4>; 330 ti,mbox-num-fifos = <16>; 331 interrupt-parent = <&main_navss_intr>; 332 status = "disabled"; 333 }; 334 335 mailbox0_cluster9: mailbox@31f89000 { 336 compatible = "ti,am654-mailbox"; 337 reg = <0x00 0x31f89000 0x00 0x200>; 338 #mbox-cells = <1>; 339 ti,mbox-num-users = <4>; 340 ti,mbox-num-fifos = <16>; 341 interrupt-parent = <&main_navss_intr>; 342 status = "disabled"; 343 }; 344 345 mailbox0_cluster10: mailbox@31f8a000 { 346 compatible = "ti,am654-mailbox"; 347 reg = <0x00 0x31f8a000 0x00 0x200>; 348 #mbox-cells = <1>; 349 ti,mbox-num-users = <4>; 350 ti,mbox-num-fifos = <16>; 351 interrupt-parent = <&main_navss_intr>; 352 status = "disabled"; 353 }; 354 355 mailbox0_cluster11: mailbox@31f8b000 { 356 compatible = "ti,am654-mailbox"; 357 reg = <0x00 0x31f8b000 0x00 0x200>; 358 #mbox-cells = <1>; 359 ti,mbox-num-users = <4>; 360 ti,mbox-num-fifos = <16>; 361 interrupt-parent = <&main_navss_intr>; 362 status = "disabled"; 363 }; 364 365 main_ringacc: ringacc@3c000000 { 366 compatible = "ti,am654-navss-ringacc"; 367 reg = <0x0 0x3c000000 0x0 0x400000>, 368 <0x0 0x38000000 0x0 0x400000>, 369 <0x0 0x31120000 0x0 0x100>, 370 <0x0 0x33000000 0x0 0x40000>; 371 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 372 ti,num-rings = <1024>; 373 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 374 ti,sci = <&dmsc>; 375 ti,sci-dev-id = <211>; 376 msi-parent = <&main_udmass_inta>; 377 }; 378 379 main_udmap: dma-controller@31150000 { 380 compatible = "ti,j721e-navss-main-udmap"; 381 reg = <0x0 0x31150000 0x0 0x100>, 382 <0x0 0x34000000 0x0 0x100000>, 383 <0x0 0x35000000 0x0 0x100000>; 384 reg-names = "gcfg", "rchanrt", "tchanrt"; 385 msi-parent = <&main_udmass_inta>; 386 #dma-cells = <1>; 387 388 ti,sci = <&dmsc>; 389 ti,sci-dev-id = <212>; 390 ti,ringacc = <&main_ringacc>; 391 392 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 393 <0x0f>, /* TX_HCHAN */ 394 <0x10>; /* TX_UHCHAN */ 395 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 396 <0x0b>, /* RX_HCHAN */ 397 <0x0c>; /* RX_UHCHAN */ 398 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 399 }; 400 401 cpts@310d0000 { 402 compatible = "ti,j721e-cpts"; 403 reg = <0x0 0x310d0000 0x0 0x400>; 404 reg-names = "cpts"; 405 clocks = <&k3_clks 201 1>; 406 clock-names = "cpts"; 407 interrupts-extended = <&main_navss_intr 391>; 408 interrupt-names = "cpts"; 409 ti,cpts-periodic-outputs = <6>; 410 ti,cpts-ext-ts-inputs = <8>; 411 }; 412 }; 413 414 cpsw0: ethernet@c000000 { 415 compatible = "ti,j721e-cpswxg-nuss"; 416 #address-cells = <2>; 417 #size-cells = <2>; 418 reg = <0x0 0xc000000 0x0 0x200000>; 419 reg-names = "cpsw_nuss"; 420 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 421 clocks = <&k3_clks 19 89>; 422 clock-names = "fck"; 423 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 424 425 dmas = <&main_udmap 0xca00>, 426 <&main_udmap 0xca01>, 427 <&main_udmap 0xca02>, 428 <&main_udmap 0xca03>, 429 <&main_udmap 0xca04>, 430 <&main_udmap 0xca05>, 431 <&main_udmap 0xca06>, 432 <&main_udmap 0xca07>, 433 <&main_udmap 0x4a00>; 434 dma-names = "tx0", "tx1", "tx2", "tx3", 435 "tx4", "tx5", "tx6", "tx7", 436 "rx"; 437 438 status = "disabled"; 439 440 ethernet-ports { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 cpsw0_port1: port@1 { 444 reg = <1>; 445 ti,mac-only; 446 label = "port1"; 447 status = "disabled"; 448 }; 449 450 cpsw0_port2: port@2 { 451 reg = <2>; 452 ti,mac-only; 453 label = "port2"; 454 status = "disabled"; 455 }; 456 457 cpsw0_port3: port@3 { 458 reg = <3>; 459 ti,mac-only; 460 label = "port3"; 461 status = "disabled"; 462 }; 463 464 cpsw0_port4: port@4 { 465 reg = <4>; 466 ti,mac-only; 467 label = "port4"; 468 status = "disabled"; 469 }; 470 471 cpsw0_port5: port@5 { 472 reg = <5>; 473 ti,mac-only; 474 label = "port5"; 475 status = "disabled"; 476 }; 477 478 cpsw0_port6: port@6 { 479 reg = <6>; 480 ti,mac-only; 481 label = "port6"; 482 status = "disabled"; 483 }; 484 485 cpsw0_port7: port@7 { 486 reg = <7>; 487 ti,mac-only; 488 label = "port7"; 489 status = "disabled"; 490 }; 491 492 cpsw0_port8: port@8 { 493 reg = <8>; 494 ti,mac-only; 495 label = "port8"; 496 status = "disabled"; 497 }; 498 }; 499 500 cpsw9g_mdio: mdio@f00 { 501 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 502 reg = <0x0 0xf00 0x0 0x100>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&k3_clks 19 89>; 506 clock-names = "fck"; 507 bus_freq = <1000000>; 508 status = "disabled"; 509 }; 510 511 cpts@3d000 { 512 compatible = "ti,j721e-cpts"; 513 reg = <0x0 0x3d000 0x0 0x400>; 514 clocks = <&k3_clks 19 16>; 515 clock-names = "cpts"; 516 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 517 interrupt-names = "cpts"; 518 ti,cpts-ext-ts-inputs = <4>; 519 ti,cpts-periodic-outputs = <2>; 520 }; 521 }; 522 523 main_crypto: crypto@4e00000 { 524 compatible = "ti,j721e-sa2ul"; 525 reg = <0x0 0x4e00000 0x0 0x1200>; 526 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 527 #address-cells = <2>; 528 #size-cells = <2>; 529 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 530 531 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 532 <&main_udmap 0x4001>; 533 dma-names = "tx", "rx1", "rx2"; 534 535 rng: rng@4e10000 { 536 compatible = "inside-secure,safexcel-eip76"; 537 reg = <0x0 0x4e10000 0x0 0x7d>; 538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 }; 541 542 main_pmx0: pinctrl@11c000 { 543 compatible = "pinctrl-single"; 544 /* Proxy 0 addressing */ 545 reg = <0x0 0x11c000 0x0 0x2b4>; 546 #pinctrl-cells = <1>; 547 pinctrl-single,register-width = <32>; 548 pinctrl-single,function-mask = <0xffffffff>; 549 }; 550 551 serdes_wiz0: wiz@5000000 { 552 compatible = "ti,j721e-wiz-16g"; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 556 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 557 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 558 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 559 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 560 num-lanes = <2>; 561 #reset-cells = <1>; 562 ranges = <0x5000000 0x0 0x5000000 0x10000>; 563 564 wiz0_pll0_refclk: pll0-refclk { 565 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 566 #clock-cells = <0>; 567 assigned-clocks = <&wiz0_pll0_refclk>; 568 assigned-clock-parents = <&k3_clks 292 11>; 569 }; 570 571 wiz0_pll1_refclk: pll1-refclk { 572 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 573 #clock-cells = <0>; 574 assigned-clocks = <&wiz0_pll1_refclk>; 575 assigned-clock-parents = <&k3_clks 292 0>; 576 }; 577 578 wiz0_refclk_dig: refclk-dig { 579 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 580 #clock-cells = <0>; 581 assigned-clocks = <&wiz0_refclk_dig>; 582 assigned-clock-parents = <&k3_clks 292 11>; 583 }; 584 585 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 586 clocks = <&wiz0_refclk_dig>; 587 #clock-cells = <0>; 588 }; 589 590 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 591 clocks = <&wiz0_pll1_refclk>; 592 #clock-cells = <0>; 593 }; 594 595 serdes0: serdes@5000000 { 596 compatible = "ti,sierra-phy-t0"; 597 reg-names = "serdes"; 598 reg = <0x5000000 0x10000>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 #clock-cells = <1>; 602 resets = <&serdes_wiz0 0>; 603 reset-names = "sierra_reset"; 604 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 605 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 606 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 607 "pll0_refclk", "pll1_refclk"; 608 }; 609 }; 610 611 serdes_wiz1: wiz@5010000 { 612 compatible = "ti,j721e-wiz-16g"; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 616 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 617 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 618 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 619 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 620 num-lanes = <2>; 621 #reset-cells = <1>; 622 ranges = <0x5010000 0x0 0x5010000 0x10000>; 623 624 wiz1_pll0_refclk: pll0-refclk { 625 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 626 #clock-cells = <0>; 627 assigned-clocks = <&wiz1_pll0_refclk>; 628 assigned-clock-parents = <&k3_clks 293 13>; 629 }; 630 631 wiz1_pll1_refclk: pll1-refclk { 632 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 633 #clock-cells = <0>; 634 assigned-clocks = <&wiz1_pll1_refclk>; 635 assigned-clock-parents = <&k3_clks 293 0>; 636 }; 637 638 wiz1_refclk_dig: refclk-dig { 639 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 640 #clock-cells = <0>; 641 assigned-clocks = <&wiz1_refclk_dig>; 642 assigned-clock-parents = <&k3_clks 293 13>; 643 }; 644 645 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 646 clocks = <&wiz1_refclk_dig>; 647 #clock-cells = <0>; 648 }; 649 650 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 651 clocks = <&wiz1_pll1_refclk>; 652 #clock-cells = <0>; 653 }; 654 655 serdes1: serdes@5010000 { 656 compatible = "ti,sierra-phy-t0"; 657 reg-names = "serdes"; 658 reg = <0x5010000 0x10000>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 #clock-cells = <1>; 662 resets = <&serdes_wiz1 0>; 663 reset-names = "sierra_reset"; 664 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 665 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 666 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 667 "pll0_refclk", "pll1_refclk"; 668 }; 669 }; 670 671 serdes_wiz2: wiz@5020000 { 672 compatible = "ti,j721e-wiz-16g"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 676 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 677 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 678 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 679 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 680 num-lanes = <2>; 681 #reset-cells = <1>; 682 ranges = <0x5020000 0x0 0x5020000 0x10000>; 683 684 wiz2_pll0_refclk: pll0-refclk { 685 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 686 #clock-cells = <0>; 687 assigned-clocks = <&wiz2_pll0_refclk>; 688 assigned-clock-parents = <&k3_clks 294 11>; 689 }; 690 691 wiz2_pll1_refclk: pll1-refclk { 692 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 693 #clock-cells = <0>; 694 assigned-clocks = <&wiz2_pll1_refclk>; 695 assigned-clock-parents = <&k3_clks 294 0>; 696 }; 697 698 wiz2_refclk_dig: refclk-dig { 699 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 700 #clock-cells = <0>; 701 assigned-clocks = <&wiz2_refclk_dig>; 702 assigned-clock-parents = <&k3_clks 294 11>; 703 }; 704 705 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 706 clocks = <&wiz2_refclk_dig>; 707 #clock-cells = <0>; 708 }; 709 710 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 711 clocks = <&wiz2_pll1_refclk>; 712 #clock-cells = <0>; 713 }; 714 715 serdes2: serdes@5020000 { 716 compatible = "ti,sierra-phy-t0"; 717 reg-names = "serdes"; 718 reg = <0x5020000 0x10000>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 #clock-cells = <1>; 722 resets = <&serdes_wiz2 0>; 723 reset-names = "sierra_reset"; 724 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 725 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 726 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 727 "pll0_refclk", "pll1_refclk"; 728 }; 729 }; 730 731 serdes_wiz3: wiz@5030000 { 732 compatible = "ti,j721e-wiz-16g"; 733 #address-cells = <1>; 734 #size-cells = <1>; 735 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 736 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 737 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 738 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 739 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 740 num-lanes = <2>; 741 #reset-cells = <1>; 742 ranges = <0x5030000 0x0 0x5030000 0x10000>; 743 744 wiz3_pll0_refclk: pll0-refclk { 745 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 746 #clock-cells = <0>; 747 assigned-clocks = <&wiz3_pll0_refclk>; 748 assigned-clock-parents = <&k3_clks 295 9>; 749 }; 750 751 wiz3_pll1_refclk: pll1-refclk { 752 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 753 #clock-cells = <0>; 754 assigned-clocks = <&wiz3_pll1_refclk>; 755 assigned-clock-parents = <&k3_clks 295 0>; 756 }; 757 758 wiz3_refclk_dig: refclk-dig { 759 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 760 #clock-cells = <0>; 761 assigned-clocks = <&wiz3_refclk_dig>; 762 assigned-clock-parents = <&k3_clks 295 9>; 763 }; 764 765 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 766 clocks = <&wiz3_refclk_dig>; 767 #clock-cells = <0>; 768 }; 769 770 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 771 clocks = <&wiz3_pll1_refclk>; 772 #clock-cells = <0>; 773 }; 774 775 serdes3: serdes@5030000 { 776 compatible = "ti,sierra-phy-t0"; 777 reg-names = "serdes"; 778 reg = <0x5030000 0x10000>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 #clock-cells = <1>; 782 resets = <&serdes_wiz3 0>; 783 reset-names = "sierra_reset"; 784 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 785 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 786 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 787 "pll0_refclk", "pll1_refclk"; 788 }; 789 }; 790 791 pcie0_rc: pcie@2900000 { 792 compatible = "ti,j721e-pcie-host"; 793 reg = <0x00 0x02900000 0x00 0x1000>, 794 <0x00 0x02907000 0x00 0x400>, 795 <0x00 0x0d000000 0x00 0x00800000>, 796 <0x00 0x10000000 0x00 0x00001000>; 797 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 798 interrupt-names = "link_state"; 799 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 800 device_type = "pci"; 801 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 802 max-link-speed = <3>; 803 num-lanes = <2>; 804 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 805 clocks = <&k3_clks 239 1>; 806 clock-names = "fck"; 807 #address-cells = <3>; 808 #size-cells = <2>; 809 bus-range = <0x0 0xff>; 810 vendor-id = <0x104c>; 811 device-id = <0xb00d>; 812 msi-map = <0x0 &gic_its 0x0 0x10000>; 813 dma-coherent; 814 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 815 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 816 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 817 }; 818 819 pcie0_ep: pcie-ep@2900000 { 820 compatible = "ti,j721e-pcie-ep"; 821 reg = <0x00 0x02900000 0x00 0x1000>, 822 <0x00 0x02907000 0x00 0x400>, 823 <0x00 0x0d000000 0x00 0x00800000>, 824 <0x00 0x10000000 0x00 0x08000000>; 825 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 826 interrupt-names = "link_state"; 827 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 828 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 829 max-link-speed = <3>; 830 num-lanes = <2>; 831 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 832 clocks = <&k3_clks 239 1>; 833 clock-names = "fck"; 834 max-functions = /bits/ 8 <6>; 835 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 836 dma-coherent; 837 }; 838 839 pcie1_rc: pcie@2910000 { 840 compatible = "ti,j721e-pcie-host"; 841 reg = <0x00 0x02910000 0x00 0x1000>, 842 <0x00 0x02917000 0x00 0x400>, 843 <0x00 0x0d800000 0x00 0x00800000>, 844 <0x00 0x18000000 0x00 0x00001000>; 845 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 846 interrupt-names = "link_state"; 847 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 848 device_type = "pci"; 849 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 850 max-link-speed = <3>; 851 num-lanes = <2>; 852 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 853 clocks = <&k3_clks 240 1>; 854 clock-names = "fck"; 855 #address-cells = <3>; 856 #size-cells = <2>; 857 bus-range = <0x0 0xff>; 858 vendor-id = <0x104c>; 859 device-id = <0xb00d>; 860 msi-map = <0x0 &gic_its 0x10000 0x10000>; 861 dma-coherent; 862 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 863 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 864 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 865 }; 866 867 pcie1_ep: pcie-ep@2910000 { 868 compatible = "ti,j721e-pcie-ep"; 869 reg = <0x00 0x02910000 0x00 0x1000>, 870 <0x00 0x02917000 0x00 0x400>, 871 <0x00 0x0d800000 0x00 0x00800000>, 872 <0x00 0x18000000 0x00 0x08000000>; 873 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 874 interrupt-names = "link_state"; 875 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 876 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 877 max-link-speed = <3>; 878 num-lanes = <2>; 879 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 880 clocks = <&k3_clks 240 1>; 881 clock-names = "fck"; 882 max-functions = /bits/ 8 <6>; 883 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 884 dma-coherent; 885 }; 886 887 pcie2_rc: pcie@2920000 { 888 compatible = "ti,j721e-pcie-host"; 889 reg = <0x00 0x02920000 0x00 0x1000>, 890 <0x00 0x02927000 0x00 0x400>, 891 <0x00 0x0e000000 0x00 0x00800000>, 892 <0x44 0x00000000 0x00 0x00001000>; 893 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 894 interrupt-names = "link_state"; 895 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 896 device_type = "pci"; 897 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 898 max-link-speed = <3>; 899 num-lanes = <2>; 900 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 901 clocks = <&k3_clks 241 1>; 902 clock-names = "fck"; 903 #address-cells = <3>; 904 #size-cells = <2>; 905 bus-range = <0x0 0xff>; 906 vendor-id = <0x104c>; 907 device-id = <0xb00d>; 908 msi-map = <0x0 &gic_its 0x20000 0x10000>; 909 dma-coherent; 910 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 911 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 912 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 913 }; 914 915 pcie2_ep: pcie-ep@2920000 { 916 compatible = "ti,j721e-pcie-ep"; 917 reg = <0x00 0x02920000 0x00 0x1000>, 918 <0x00 0x02927000 0x00 0x400>, 919 <0x00 0x0e000000 0x00 0x00800000>, 920 <0x44 0x00000000 0x00 0x08000000>; 921 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 922 interrupt-names = "link_state"; 923 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 924 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 925 max-link-speed = <3>; 926 num-lanes = <2>; 927 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 928 clocks = <&k3_clks 241 1>; 929 clock-names = "fck"; 930 max-functions = /bits/ 8 <6>; 931 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 932 dma-coherent; 933 }; 934 935 pcie3_rc: pcie@2930000 { 936 compatible = "ti,j721e-pcie-host"; 937 reg = <0x00 0x02930000 0x00 0x1000>, 938 <0x00 0x02937000 0x00 0x400>, 939 <0x00 0x0e800000 0x00 0x00800000>, 940 <0x44 0x10000000 0x00 0x00001000>; 941 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 942 interrupt-names = "link_state"; 943 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 944 device_type = "pci"; 945 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 946 max-link-speed = <3>; 947 num-lanes = <2>; 948 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 949 clocks = <&k3_clks 242 1>; 950 clock-names = "fck"; 951 #address-cells = <3>; 952 #size-cells = <2>; 953 bus-range = <0x0 0xff>; 954 vendor-id = <0x104c>; 955 device-id = <0xb00d>; 956 msi-map = <0x0 &gic_its 0x30000 0x10000>; 957 dma-coherent; 958 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 959 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 960 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 961 }; 962 963 pcie3_ep: pcie-ep@2930000 { 964 compatible = "ti,j721e-pcie-ep"; 965 reg = <0x00 0x02930000 0x00 0x1000>, 966 <0x00 0x02937000 0x00 0x400>, 967 <0x00 0x0e800000 0x00 0x00800000>, 968 <0x44 0x10000000 0x00 0x08000000>; 969 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 970 interrupt-names = "link_state"; 971 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 972 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 973 max-link-speed = <3>; 974 num-lanes = <2>; 975 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 976 clocks = <&k3_clks 242 1>; 977 clock-names = "fck"; 978 max-functions = /bits/ 8 <6>; 979 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 980 dma-coherent; 981 #address-cells = <2>; 982 #size-cells = <2>; 983 }; 984 985 serdes_wiz4: wiz@5050000 { 986 compatible = "ti,am64-wiz-10g"; 987 #address-cells = <1>; 988 #size-cells = <1>; 989 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 990 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 991 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 992 assigned-clocks = <&k3_clks 297 9>; 993 assigned-clock-parents = <&k3_clks 297 10>; 994 assigned-clock-rates = <19200000>; 995 num-lanes = <4>; 996 #reset-cells = <1>; 997 #clock-cells = <1>; 998 ranges = <0x05050000 0x00 0x05050000 0x010000>, 999 <0x0a030a00 0x00 0x0a030a00 0x40>; 1000 1001 serdes4: serdes@5050000 { 1002 /* 1003 * Note: we also map DPTX PHY registers as the Torrent 1004 * needs to manage those. 1005 */ 1006 compatible = "ti,j721e-serdes-10g"; 1007 reg = <0x05050000 0x010000>, 1008 <0x0a030a00 0x40>; /* DPTX PHY */ 1009 reg-names = "torrent_phy", "dptx_phy"; 1010 1011 resets = <&serdes_wiz4 0>; 1012 reset-names = "torrent_reset"; 1013 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 1014 clock-names = "refclk"; 1015 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1016 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1017 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1018 assigned-clock-parents = <&k3_clks 297 9>, 1019 <&k3_clks 297 9>, 1020 <&k3_clks 297 9>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 }; 1024 }; 1025 1026 main_uart0: serial@2800000 { 1027 compatible = "ti,j721e-uart", "ti,am654-uart"; 1028 reg = <0x00 0x02800000 0x00 0x100>; 1029 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1030 clock-frequency = <48000000>; 1031 current-speed = <115200>; 1032 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 1033 clocks = <&k3_clks 146 0>; 1034 clock-names = "fclk"; 1035 status = "disabled"; 1036 }; 1037 1038 main_uart1: serial@2810000 { 1039 compatible = "ti,j721e-uart", "ti,am654-uart"; 1040 reg = <0x00 0x02810000 0x00 0x100>; 1041 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1042 clock-frequency = <48000000>; 1043 current-speed = <115200>; 1044 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1045 clocks = <&k3_clks 278 0>; 1046 clock-names = "fclk"; 1047 status = "disabled"; 1048 }; 1049 1050 main_uart2: serial@2820000 { 1051 compatible = "ti,j721e-uart", "ti,am654-uart"; 1052 reg = <0x00 0x02820000 0x00 0x100>; 1053 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1054 clock-frequency = <48000000>; 1055 current-speed = <115200>; 1056 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 1057 clocks = <&k3_clks 279 0>; 1058 clock-names = "fclk"; 1059 status = "disabled"; 1060 }; 1061 1062 main_uart3: serial@2830000 { 1063 compatible = "ti,j721e-uart", "ti,am654-uart"; 1064 reg = <0x00 0x02830000 0x00 0x100>; 1065 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1066 clock-frequency = <48000000>; 1067 current-speed = <115200>; 1068 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 1069 clocks = <&k3_clks 280 0>; 1070 clock-names = "fclk"; 1071 status = "disabled"; 1072 }; 1073 1074 main_uart4: serial@2840000 { 1075 compatible = "ti,j721e-uart", "ti,am654-uart"; 1076 reg = <0x00 0x02840000 0x00 0x100>; 1077 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1078 clock-frequency = <48000000>; 1079 current-speed = <115200>; 1080 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 1081 clocks = <&k3_clks 281 0>; 1082 clock-names = "fclk"; 1083 status = "disabled"; 1084 }; 1085 1086 main_uart5: serial@2850000 { 1087 compatible = "ti,j721e-uart", "ti,am654-uart"; 1088 reg = <0x00 0x02850000 0x00 0x100>; 1089 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1090 clock-frequency = <48000000>; 1091 current-speed = <115200>; 1092 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1093 clocks = <&k3_clks 282 0>; 1094 clock-names = "fclk"; 1095 status = "disabled"; 1096 }; 1097 1098 main_uart6: serial@2860000 { 1099 compatible = "ti,j721e-uart", "ti,am654-uart"; 1100 reg = <0x00 0x02860000 0x00 0x100>; 1101 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1102 clock-frequency = <48000000>; 1103 current-speed = <115200>; 1104 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1105 clocks = <&k3_clks 283 0>; 1106 clock-names = "fclk"; 1107 status = "disabled"; 1108 }; 1109 1110 main_uart7: serial@2870000 { 1111 compatible = "ti,j721e-uart", "ti,am654-uart"; 1112 reg = <0x00 0x02870000 0x00 0x100>; 1113 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1114 clock-frequency = <48000000>; 1115 current-speed = <115200>; 1116 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1117 clocks = <&k3_clks 284 0>; 1118 clock-names = "fclk"; 1119 status = "disabled"; 1120 }; 1121 1122 main_uart8: serial@2880000 { 1123 compatible = "ti,j721e-uart", "ti,am654-uart"; 1124 reg = <0x00 0x02880000 0x00 0x100>; 1125 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1126 clock-frequency = <48000000>; 1127 current-speed = <115200>; 1128 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1129 clocks = <&k3_clks 285 0>; 1130 clock-names = "fclk"; 1131 status = "disabled"; 1132 }; 1133 1134 main_uart9: serial@2890000 { 1135 compatible = "ti,j721e-uart", "ti,am654-uart"; 1136 reg = <0x00 0x02890000 0x00 0x100>; 1137 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1138 clock-frequency = <48000000>; 1139 current-speed = <115200>; 1140 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1141 clocks = <&k3_clks 286 0>; 1142 clock-names = "fclk"; 1143 status = "disabled"; 1144 }; 1145 1146 main_gpio0: gpio@600000 { 1147 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1148 reg = <0x0 0x00600000 0x0 0x100>; 1149 gpio-controller; 1150 #gpio-cells = <2>; 1151 interrupt-parent = <&main_gpio_intr>; 1152 interrupts = <256>, <257>, <258>, <259>, 1153 <260>, <261>, <262>, <263>; 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 ti,ngpio = <128>; 1157 ti,davinci-gpio-unbanked = <0>; 1158 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1159 clocks = <&k3_clks 105 0>; 1160 clock-names = "gpio"; 1161 }; 1162 1163 main_gpio1: gpio@601000 { 1164 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1165 reg = <0x0 0x00601000 0x0 0x100>; 1166 gpio-controller; 1167 #gpio-cells = <2>; 1168 interrupt-parent = <&main_gpio_intr>; 1169 interrupts = <288>, <289>, <290>; 1170 interrupt-controller; 1171 #interrupt-cells = <2>; 1172 ti,ngpio = <36>; 1173 ti,davinci-gpio-unbanked = <0>; 1174 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1175 clocks = <&k3_clks 106 0>; 1176 clock-names = "gpio"; 1177 }; 1178 1179 main_gpio2: gpio@610000 { 1180 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1181 reg = <0x0 0x00610000 0x0 0x100>; 1182 gpio-controller; 1183 #gpio-cells = <2>; 1184 interrupt-parent = <&main_gpio_intr>; 1185 interrupts = <264>, <265>, <266>, <267>, 1186 <268>, <269>, <270>, <271>; 1187 interrupt-controller; 1188 #interrupt-cells = <2>; 1189 ti,ngpio = <128>; 1190 ti,davinci-gpio-unbanked = <0>; 1191 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1192 clocks = <&k3_clks 107 0>; 1193 clock-names = "gpio"; 1194 }; 1195 1196 main_gpio3: gpio@611000 { 1197 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1198 reg = <0x0 0x00611000 0x0 0x100>; 1199 gpio-controller; 1200 #gpio-cells = <2>; 1201 interrupt-parent = <&main_gpio_intr>; 1202 interrupts = <292>, <293>, <294>; 1203 interrupt-controller; 1204 #interrupt-cells = <2>; 1205 ti,ngpio = <36>; 1206 ti,davinci-gpio-unbanked = <0>; 1207 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1208 clocks = <&k3_clks 108 0>; 1209 clock-names = "gpio"; 1210 }; 1211 1212 main_gpio4: gpio@620000 { 1213 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1214 reg = <0x0 0x00620000 0x0 0x100>; 1215 gpio-controller; 1216 #gpio-cells = <2>; 1217 interrupt-parent = <&main_gpio_intr>; 1218 interrupts = <272>, <273>, <274>, <275>, 1219 <276>, <277>, <278>, <279>; 1220 interrupt-controller; 1221 #interrupt-cells = <2>; 1222 ti,ngpio = <128>; 1223 ti,davinci-gpio-unbanked = <0>; 1224 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1225 clocks = <&k3_clks 109 0>; 1226 clock-names = "gpio"; 1227 }; 1228 1229 main_gpio5: gpio@621000 { 1230 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1231 reg = <0x0 0x00621000 0x0 0x100>; 1232 gpio-controller; 1233 #gpio-cells = <2>; 1234 interrupt-parent = <&main_gpio_intr>; 1235 interrupts = <296>, <297>, <298>; 1236 interrupt-controller; 1237 #interrupt-cells = <2>; 1238 ti,ngpio = <36>; 1239 ti,davinci-gpio-unbanked = <0>; 1240 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1241 clocks = <&k3_clks 110 0>; 1242 clock-names = "gpio"; 1243 }; 1244 1245 main_gpio6: gpio@630000 { 1246 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1247 reg = <0x0 0x00630000 0x0 0x100>; 1248 gpio-controller; 1249 #gpio-cells = <2>; 1250 interrupt-parent = <&main_gpio_intr>; 1251 interrupts = <280>, <281>, <282>, <283>, 1252 <284>, <285>, <286>, <287>; 1253 interrupt-controller; 1254 #interrupt-cells = <2>; 1255 ti,ngpio = <128>; 1256 ti,davinci-gpio-unbanked = <0>; 1257 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1258 clocks = <&k3_clks 111 0>; 1259 clock-names = "gpio"; 1260 }; 1261 1262 main_gpio7: gpio@631000 { 1263 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1264 reg = <0x0 0x00631000 0x0 0x100>; 1265 gpio-controller; 1266 #gpio-cells = <2>; 1267 interrupt-parent = <&main_gpio_intr>; 1268 interrupts = <300>, <301>, <302>; 1269 interrupt-controller; 1270 #interrupt-cells = <2>; 1271 ti,ngpio = <36>; 1272 ti,davinci-gpio-unbanked = <0>; 1273 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1274 clocks = <&k3_clks 112 0>; 1275 clock-names = "gpio"; 1276 }; 1277 1278 main_sdhci0: mmc@4f80000 { 1279 compatible = "ti,j721e-sdhci-8bit"; 1280 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1281 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1283 clock-names = "clk_ahb", "clk_xin"; 1284 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1285 assigned-clocks = <&k3_clks 91 1>; 1286 assigned-clock-parents = <&k3_clks 91 2>; 1287 bus-width = <8>; 1288 mmc-hs200-1_8v; 1289 mmc-ddr-1_8v; 1290 ti,otap-del-sel-legacy = <0xf>; 1291 ti,otap-del-sel-mmc-hs = <0xf>; 1292 ti,otap-del-sel-ddr52 = <0x5>; 1293 ti,otap-del-sel-hs200 = <0x6>; 1294 ti,otap-del-sel-hs400 = <0x0>; 1295 ti,itap-del-sel-legacy = <0x10>; 1296 ti,itap-del-sel-mmc-hs = <0xa>; 1297 ti,itap-del-sel-ddr52 = <0x3>; 1298 ti,trm-icp = <0x8>; 1299 dma-coherent; 1300 }; 1301 1302 main_sdhci1: mmc@4fb0000 { 1303 compatible = "ti,j721e-sdhci-4bit"; 1304 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1305 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1306 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1307 clock-names = "clk_ahb", "clk_xin"; 1308 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1309 assigned-clocks = <&k3_clks 92 0>; 1310 assigned-clock-parents = <&k3_clks 92 1>; 1311 ti,otap-del-sel-legacy = <0x0>; 1312 ti,otap-del-sel-sd-hs = <0xf>; 1313 ti,otap-del-sel-sdr12 = <0xf>; 1314 ti,otap-del-sel-sdr25 = <0xf>; 1315 ti,otap-del-sel-sdr50 = <0xc>; 1316 ti,otap-del-sel-ddr50 = <0xc>; 1317 ti,itap-del-sel-legacy = <0x0>; 1318 ti,itap-del-sel-sd-hs = <0x0>; 1319 ti,itap-del-sel-sdr12 = <0x0>; 1320 ti,itap-del-sel-sdr25 = <0x0>; 1321 ti,itap-del-sel-ddr50 = <0x2>; 1322 ti,trm-icp = <0x8>; 1323 ti,clkbuf-sel = <0x7>; 1324 dma-coherent; 1325 sdhci-caps-mask = <0x2 0x0>; 1326 }; 1327 1328 main_sdhci2: mmc@4f98000 { 1329 compatible = "ti,j721e-sdhci-4bit"; 1330 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1331 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1332 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1333 clock-names = "clk_ahb", "clk_xin"; 1334 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1335 assigned-clocks = <&k3_clks 93 0>; 1336 assigned-clock-parents = <&k3_clks 93 1>; 1337 ti,otap-del-sel-legacy = <0x0>; 1338 ti,otap-del-sel-sd-hs = <0xf>; 1339 ti,otap-del-sel-sdr12 = <0xf>; 1340 ti,otap-del-sel-sdr25 = <0xf>; 1341 ti,otap-del-sel-sdr50 = <0xc>; 1342 ti,otap-del-sel-ddr50 = <0xc>; 1343 ti,itap-del-sel-legacy = <0x0>; 1344 ti,itap-del-sel-sd-hs = <0x0>; 1345 ti,itap-del-sel-sdr12 = <0x0>; 1346 ti,itap-del-sel-sdr25 = <0x0>; 1347 ti,itap-del-sel-ddr50 = <0x2>; 1348 ti,trm-icp = <0x8>; 1349 ti,clkbuf-sel = <0x7>; 1350 dma-coherent; 1351 sdhci-caps-mask = <0x2 0x0>; 1352 }; 1353 1354 usbss0: cdns-usb@4104000 { 1355 compatible = "ti,j721e-usb"; 1356 reg = <0x00 0x4104000 0x00 0x100>; 1357 dma-coherent; 1358 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1359 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1360 clock-names = "ref", "lpm"; 1361 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1362 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1363 #address-cells = <2>; 1364 #size-cells = <2>; 1365 ranges; 1366 1367 usb0: usb@6000000 { 1368 compatible = "cdns,usb3"; 1369 reg = <0x00 0x6000000 0x00 0x10000>, 1370 <0x00 0x6010000 0x00 0x10000>, 1371 <0x00 0x6020000 0x00 0x10000>; 1372 reg-names = "otg", "xhci", "dev"; 1373 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1374 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1375 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1376 interrupt-names = "host", 1377 "peripheral", 1378 "otg"; 1379 maximum-speed = "super-speed"; 1380 dr_mode = "otg"; 1381 }; 1382 }; 1383 1384 usbss1: cdns-usb@4114000 { 1385 compatible = "ti,j721e-usb"; 1386 reg = <0x00 0x4114000 0x00 0x100>; 1387 dma-coherent; 1388 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1389 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1390 clock-names = "ref", "lpm"; 1391 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1392 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1393 #address-cells = <2>; 1394 #size-cells = <2>; 1395 ranges; 1396 1397 usb1: usb@6400000 { 1398 compatible = "cdns,usb3"; 1399 reg = <0x00 0x6400000 0x00 0x10000>, 1400 <0x00 0x6410000 0x00 0x10000>, 1401 <0x00 0x6420000 0x00 0x10000>; 1402 reg-names = "otg", "xhci", "dev"; 1403 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1404 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1405 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1406 interrupt-names = "host", 1407 "peripheral", 1408 "otg"; 1409 maximum-speed = "super-speed"; 1410 dr_mode = "otg"; 1411 }; 1412 }; 1413 1414 main_i2c0: i2c@2000000 { 1415 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1416 reg = <0x0 0x2000000 0x0 0x100>; 1417 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 clock-names = "fck"; 1421 clocks = <&k3_clks 187 0>; 1422 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1423 status = "disabled"; 1424 }; 1425 1426 main_i2c1: i2c@2010000 { 1427 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1428 reg = <0x0 0x2010000 0x0 0x100>; 1429 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 clock-names = "fck"; 1433 clocks = <&k3_clks 188 0>; 1434 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1435 status = "disabled"; 1436 }; 1437 1438 main_i2c2: i2c@2020000 { 1439 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1440 reg = <0x0 0x2020000 0x0 0x100>; 1441 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 clock-names = "fck"; 1445 clocks = <&k3_clks 189 0>; 1446 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1447 status = "disabled"; 1448 }; 1449 1450 main_i2c3: i2c@2030000 { 1451 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1452 reg = <0x0 0x2030000 0x0 0x100>; 1453 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 clock-names = "fck"; 1457 clocks = <&k3_clks 190 0>; 1458 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1459 status = "disabled"; 1460 }; 1461 1462 main_i2c4: i2c@2040000 { 1463 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1464 reg = <0x0 0x2040000 0x0 0x100>; 1465 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 clock-names = "fck"; 1469 clocks = <&k3_clks 191 0>; 1470 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1471 status = "disabled"; 1472 }; 1473 1474 main_i2c5: i2c@2050000 { 1475 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1476 reg = <0x0 0x2050000 0x0 0x100>; 1477 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 clock-names = "fck"; 1481 clocks = <&k3_clks 192 0>; 1482 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1483 status = "disabled"; 1484 }; 1485 1486 main_i2c6: i2c@2060000 { 1487 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1488 reg = <0x0 0x2060000 0x0 0x100>; 1489 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 clock-names = "fck"; 1493 clocks = <&k3_clks 193 0>; 1494 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1495 status = "disabled"; 1496 }; 1497 1498 ufs_wrapper: ufs-wrapper@4e80000 { 1499 compatible = "ti,j721e-ufs"; 1500 reg = <0x0 0x4e80000 0x0 0x100>; 1501 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1502 clocks = <&k3_clks 277 1>; 1503 assigned-clocks = <&k3_clks 277 1>; 1504 assigned-clock-parents = <&k3_clks 277 4>; 1505 ranges; 1506 #address-cells = <2>; 1507 #size-cells = <2>; 1508 1509 ufs@4e84000 { 1510 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1511 reg = <0x0 0x4e84000 0x0 0x10000>; 1512 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1513 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1514 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1515 clock-names = "core_clk", "phy_clk", "ref_clk"; 1516 dma-coherent; 1517 }; 1518 }; 1519 1520 mhdp: dp-bridge@a000000 { 1521 compatible = "ti,j721e-mhdp8546"; 1522 /* 1523 * Note: we do not map DPTX PHY area, as that is handled by 1524 * the PHY driver. 1525 */ 1526 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1527 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1528 reg-names = "mhdptx", "j721e-intg"; 1529 1530 clocks = <&k3_clks 151 36>; 1531 1532 interrupt-parent = <&gic500>; 1533 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1534 1535 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1536 1537 dp0_ports: ports { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 port@0 { 1542 reg = <0>; 1543 }; 1544 1545 port@4 { 1546 reg = <4>; 1547 }; 1548 }; 1549 }; 1550 1551 dss: dss@4a00000 { 1552 compatible = "ti,j721e-dss"; 1553 reg = 1554 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1555 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1556 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1557 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1558 1559 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1560 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1561 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1562 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1563 1564 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1565 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1566 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1567 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1568 1569 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1570 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1571 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1572 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1573 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1574 1575 reg-names = "common_m", "common_s0", 1576 "common_s1", "common_s2", 1577 "vidl1", "vidl2","vid1","vid2", 1578 "ovr1", "ovr2", "ovr3", "ovr4", 1579 "vp1", "vp2", "vp3", "vp4", 1580 "wb"; 1581 1582 clocks = <&k3_clks 152 0>, 1583 <&k3_clks 152 1>, 1584 <&k3_clks 152 4>, 1585 <&k3_clks 152 9>, 1586 <&k3_clks 152 13>; 1587 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1588 1589 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1590 1591 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1595 interrupt-names = "common_m", 1596 "common_s0", 1597 "common_s1", 1598 "common_s2"; 1599 1600 dss_ports: ports { 1601 }; 1602 }; 1603 1604 mcasp0: mcasp@2b00000 { 1605 compatible = "ti,am33xx-mcasp-audio"; 1606 reg = <0x0 0x02b00000 0x0 0x2000>, 1607 <0x0 0x02b08000 0x0 0x1000>; 1608 reg-names = "mpu","dat"; 1609 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1611 interrupt-names = "tx", "rx"; 1612 1613 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1614 dma-names = "tx", "rx"; 1615 1616 clocks = <&k3_clks 174 1>; 1617 clock-names = "fck"; 1618 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1619 status = "disabled"; 1620 }; 1621 1622 mcasp1: mcasp@2b10000 { 1623 compatible = "ti,am33xx-mcasp-audio"; 1624 reg = <0x0 0x02b10000 0x0 0x2000>, 1625 <0x0 0x02b18000 0x0 0x1000>; 1626 reg-names = "mpu","dat"; 1627 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1629 interrupt-names = "tx", "rx"; 1630 1631 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1632 dma-names = "tx", "rx"; 1633 1634 clocks = <&k3_clks 175 1>; 1635 clock-names = "fck"; 1636 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1637 status = "disabled"; 1638 }; 1639 1640 mcasp2: mcasp@2b20000 { 1641 compatible = "ti,am33xx-mcasp-audio"; 1642 reg = <0x0 0x02b20000 0x0 0x2000>, 1643 <0x0 0x02b28000 0x0 0x1000>; 1644 reg-names = "mpu","dat"; 1645 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1647 interrupt-names = "tx", "rx"; 1648 1649 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1650 dma-names = "tx", "rx"; 1651 1652 clocks = <&k3_clks 176 1>; 1653 clock-names = "fck"; 1654 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1655 status = "disabled"; 1656 }; 1657 1658 mcasp3: mcasp@2b30000 { 1659 compatible = "ti,am33xx-mcasp-audio"; 1660 reg = <0x0 0x02b30000 0x0 0x2000>, 1661 <0x0 0x02b38000 0x0 0x1000>; 1662 reg-names = "mpu","dat"; 1663 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1665 interrupt-names = "tx", "rx"; 1666 1667 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1668 dma-names = "tx", "rx"; 1669 1670 clocks = <&k3_clks 177 1>; 1671 clock-names = "fck"; 1672 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1673 status = "disabled"; 1674 }; 1675 1676 mcasp4: mcasp@2b40000 { 1677 compatible = "ti,am33xx-mcasp-audio"; 1678 reg = <0x0 0x02b40000 0x0 0x2000>, 1679 <0x0 0x02b48000 0x0 0x1000>; 1680 reg-names = "mpu","dat"; 1681 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1683 interrupt-names = "tx", "rx"; 1684 1685 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1686 dma-names = "tx", "rx"; 1687 1688 clocks = <&k3_clks 178 1>; 1689 clock-names = "fck"; 1690 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1691 status = "disabled"; 1692 }; 1693 1694 mcasp5: mcasp@2b50000 { 1695 compatible = "ti,am33xx-mcasp-audio"; 1696 reg = <0x0 0x02b50000 0x0 0x2000>, 1697 <0x0 0x02b58000 0x0 0x1000>; 1698 reg-names = "mpu","dat"; 1699 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1701 interrupt-names = "tx", "rx"; 1702 1703 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1704 dma-names = "tx", "rx"; 1705 1706 clocks = <&k3_clks 179 1>; 1707 clock-names = "fck"; 1708 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1709 status = "disabled"; 1710 }; 1711 1712 mcasp6: mcasp@2b60000 { 1713 compatible = "ti,am33xx-mcasp-audio"; 1714 reg = <0x0 0x02b60000 0x0 0x2000>, 1715 <0x0 0x02b68000 0x0 0x1000>; 1716 reg-names = "mpu","dat"; 1717 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1719 interrupt-names = "tx", "rx"; 1720 1721 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1722 dma-names = "tx", "rx"; 1723 1724 clocks = <&k3_clks 180 1>; 1725 clock-names = "fck"; 1726 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1727 status = "disabled"; 1728 }; 1729 1730 mcasp7: mcasp@2b70000 { 1731 compatible = "ti,am33xx-mcasp-audio"; 1732 reg = <0x0 0x02b70000 0x0 0x2000>, 1733 <0x0 0x02b78000 0x0 0x1000>; 1734 reg-names = "mpu","dat"; 1735 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1737 interrupt-names = "tx", "rx"; 1738 1739 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1740 dma-names = "tx", "rx"; 1741 1742 clocks = <&k3_clks 181 1>; 1743 clock-names = "fck"; 1744 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1745 status = "disabled"; 1746 }; 1747 1748 mcasp8: mcasp@2b80000 { 1749 compatible = "ti,am33xx-mcasp-audio"; 1750 reg = <0x0 0x02b80000 0x0 0x2000>, 1751 <0x0 0x02b88000 0x0 0x1000>; 1752 reg-names = "mpu","dat"; 1753 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1755 interrupt-names = "tx", "rx"; 1756 1757 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1758 dma-names = "tx", "rx"; 1759 1760 clocks = <&k3_clks 182 1>; 1761 clock-names = "fck"; 1762 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1763 status = "disabled"; 1764 }; 1765 1766 mcasp9: mcasp@2b90000 { 1767 compatible = "ti,am33xx-mcasp-audio"; 1768 reg = <0x0 0x02b90000 0x0 0x2000>, 1769 <0x0 0x02b98000 0x0 0x1000>; 1770 reg-names = "mpu","dat"; 1771 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1773 interrupt-names = "tx", "rx"; 1774 1775 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1776 dma-names = "tx", "rx"; 1777 1778 clocks = <&k3_clks 183 1>; 1779 clock-names = "fck"; 1780 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1781 status = "disabled"; 1782 }; 1783 1784 mcasp10: mcasp@2ba0000 { 1785 compatible = "ti,am33xx-mcasp-audio"; 1786 reg = <0x0 0x02ba0000 0x0 0x2000>, 1787 <0x0 0x02ba8000 0x0 0x1000>; 1788 reg-names = "mpu","dat"; 1789 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1791 interrupt-names = "tx", "rx"; 1792 1793 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1794 dma-names = "tx", "rx"; 1795 1796 clocks = <&k3_clks 184 1>; 1797 clock-names = "fck"; 1798 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1799 status = "disabled"; 1800 }; 1801 1802 mcasp11: mcasp@2bb0000 { 1803 compatible = "ti,am33xx-mcasp-audio"; 1804 reg = <0x0 0x02bb0000 0x0 0x2000>, 1805 <0x0 0x02bb8000 0x0 0x1000>; 1806 reg-names = "mpu","dat"; 1807 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1809 interrupt-names = "tx", "rx"; 1810 1811 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1812 dma-names = "tx", "rx"; 1813 1814 clocks = <&k3_clks 185 1>; 1815 clock-names = "fck"; 1816 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1817 status = "disabled"; 1818 }; 1819 1820 watchdog0: watchdog@2200000 { 1821 compatible = "ti,j7-rti-wdt"; 1822 reg = <0x0 0x2200000 0x0 0x100>; 1823 clocks = <&k3_clks 252 1>; 1824 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1825 assigned-clocks = <&k3_clks 252 1>; 1826 assigned-clock-parents = <&k3_clks 252 5>; 1827 }; 1828 1829 watchdog1: watchdog@2210000 { 1830 compatible = "ti,j7-rti-wdt"; 1831 reg = <0x0 0x2210000 0x0 0x100>; 1832 clocks = <&k3_clks 253 1>; 1833 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1834 assigned-clocks = <&k3_clks 253 1>; 1835 assigned-clock-parents = <&k3_clks 253 5>; 1836 }; 1837 1838 main_r5fss0: r5fss@5c00000 { 1839 compatible = "ti,j721e-r5fss"; 1840 ti,cluster-mode = <1>; 1841 #address-cells = <1>; 1842 #size-cells = <1>; 1843 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1844 <0x5d00000 0x00 0x5d00000 0x20000>; 1845 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1846 1847 main_r5fss0_core0: r5f@5c00000 { 1848 compatible = "ti,j721e-r5f"; 1849 reg = <0x5c00000 0x00008000>, 1850 <0x5c10000 0x00008000>; 1851 reg-names = "atcm", "btcm"; 1852 ti,sci = <&dmsc>; 1853 ti,sci-dev-id = <245>; 1854 ti,sci-proc-ids = <0x06 0xff>; 1855 resets = <&k3_reset 245 1>; 1856 firmware-name = "j7-main-r5f0_0-fw"; 1857 ti,atcm-enable = <1>; 1858 ti,btcm-enable = <1>; 1859 ti,loczrama = <1>; 1860 }; 1861 1862 main_r5fss0_core1: r5f@5d00000 { 1863 compatible = "ti,j721e-r5f"; 1864 reg = <0x5d00000 0x00008000>, 1865 <0x5d10000 0x00008000>; 1866 reg-names = "atcm", "btcm"; 1867 ti,sci = <&dmsc>; 1868 ti,sci-dev-id = <246>; 1869 ti,sci-proc-ids = <0x07 0xff>; 1870 resets = <&k3_reset 246 1>; 1871 firmware-name = "j7-main-r5f0_1-fw"; 1872 ti,atcm-enable = <1>; 1873 ti,btcm-enable = <1>; 1874 ti,loczrama = <1>; 1875 }; 1876 }; 1877 1878 main_r5fss1: r5fss@5e00000 { 1879 compatible = "ti,j721e-r5fss"; 1880 ti,cluster-mode = <1>; 1881 #address-cells = <1>; 1882 #size-cells = <1>; 1883 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1884 <0x5f00000 0x00 0x5f00000 0x20000>; 1885 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1886 1887 main_r5fss1_core0: r5f@5e00000 { 1888 compatible = "ti,j721e-r5f"; 1889 reg = <0x5e00000 0x00008000>, 1890 <0x5e10000 0x00008000>; 1891 reg-names = "atcm", "btcm"; 1892 ti,sci = <&dmsc>; 1893 ti,sci-dev-id = <247>; 1894 ti,sci-proc-ids = <0x08 0xff>; 1895 resets = <&k3_reset 247 1>; 1896 firmware-name = "j7-main-r5f1_0-fw"; 1897 ti,atcm-enable = <1>; 1898 ti,btcm-enable = <1>; 1899 ti,loczrama = <1>; 1900 }; 1901 1902 main_r5fss1_core1: r5f@5f00000 { 1903 compatible = "ti,j721e-r5f"; 1904 reg = <0x5f00000 0x00008000>, 1905 <0x5f10000 0x00008000>; 1906 reg-names = "atcm", "btcm"; 1907 ti,sci = <&dmsc>; 1908 ti,sci-dev-id = <248>; 1909 ti,sci-proc-ids = <0x09 0xff>; 1910 resets = <&k3_reset 248 1>; 1911 firmware-name = "j7-main-r5f1_1-fw"; 1912 ti,atcm-enable = <1>; 1913 ti,btcm-enable = <1>; 1914 ti,loczrama = <1>; 1915 }; 1916 }; 1917 1918 c66_0: dsp@4d80800000 { 1919 compatible = "ti,j721e-c66-dsp"; 1920 reg = <0x4d 0x80800000 0x00 0x00048000>, 1921 <0x4d 0x80e00000 0x00 0x00008000>, 1922 <0x4d 0x80f00000 0x00 0x00008000>; 1923 reg-names = "l2sram", "l1pram", "l1dram"; 1924 ti,sci = <&dmsc>; 1925 ti,sci-dev-id = <142>; 1926 ti,sci-proc-ids = <0x03 0xff>; 1927 resets = <&k3_reset 142 1>; 1928 firmware-name = "j7-c66_0-fw"; 1929 }; 1930 1931 c66_1: dsp@4d81800000 { 1932 compatible = "ti,j721e-c66-dsp"; 1933 reg = <0x4d 0x81800000 0x00 0x00048000>, 1934 <0x4d 0x81e00000 0x00 0x00008000>, 1935 <0x4d 0x81f00000 0x00 0x00008000>; 1936 reg-names = "l2sram", "l1pram", "l1dram"; 1937 ti,sci = <&dmsc>; 1938 ti,sci-dev-id = <143>; 1939 ti,sci-proc-ids = <0x04 0xff>; 1940 resets = <&k3_reset 143 1>; 1941 firmware-name = "j7-c66_1-fw"; 1942 }; 1943 1944 c71_0: dsp@64800000 { 1945 compatible = "ti,j721e-c71-dsp"; 1946 reg = <0x00 0x64800000 0x00 0x00080000>, 1947 <0x00 0x64e00000 0x00 0x0000c000>; 1948 reg-names = "l2sram", "l1dram"; 1949 ti,sci = <&dmsc>; 1950 ti,sci-dev-id = <15>; 1951 ti,sci-proc-ids = <0x30 0xff>; 1952 resets = <&k3_reset 15 1>; 1953 firmware-name = "j7-c71_0-fw"; 1954 }; 1955 1956 icssg0: icssg@b000000 { 1957 compatible = "ti,j721e-icssg"; 1958 reg = <0x00 0xb000000 0x00 0x80000>; 1959 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 1960 #address-cells = <1>; 1961 #size-cells = <1>; 1962 ranges = <0x0 0x00 0x0b000000 0x100000>; 1963 1964 icssg0_mem: memories@0 { 1965 reg = <0x0 0x2000>, 1966 <0x2000 0x2000>, 1967 <0x10000 0x10000>; 1968 reg-names = "dram0", "dram1", 1969 "shrdram2"; 1970 }; 1971 1972 icssg0_cfg: cfg@26000 { 1973 compatible = "ti,pruss-cfg", "syscon"; 1974 reg = <0x26000 0x200>; 1975 #address-cells = <1>; 1976 #size-cells = <1>; 1977 ranges = <0x0 0x26000 0x2000>; 1978 1979 clocks { 1980 #address-cells = <1>; 1981 #size-cells = <0>; 1982 1983 icssg0_coreclk_mux: coreclk-mux@3c { 1984 reg = <0x3c>; 1985 #clock-cells = <0>; 1986 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 1987 <&k3_clks 119 1>; /* icssg0_iclk */ 1988 assigned-clocks = <&icssg0_coreclk_mux>; 1989 assigned-clock-parents = <&k3_clks 119 1>; 1990 }; 1991 1992 icssg0_iepclk_mux: iepclk-mux@30 { 1993 reg = <0x30>; 1994 #clock-cells = <0>; 1995 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 1996 <&icssg0_coreclk_mux>; /* core_clk */ 1997 assigned-clocks = <&icssg0_iepclk_mux>; 1998 assigned-clock-parents = <&icssg0_coreclk_mux>; 1999 }; 2000 }; 2001 }; 2002 2003 icssg0_mii_rt: mii-rt@32000 { 2004 compatible = "ti,pruss-mii", "syscon"; 2005 reg = <0x32000 0x100>; 2006 }; 2007 2008 icssg0_mii_g_rt: mii-g-rt@33000 { 2009 compatible = "ti,pruss-mii-g", "syscon"; 2010 reg = <0x33000 0x1000>; 2011 }; 2012 2013 icssg0_intc: interrupt-controller@20000 { 2014 compatible = "ti,icssg-intc"; 2015 reg = <0x20000 0x2000>; 2016 interrupt-controller; 2017 #interrupt-cells = <3>; 2018 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 2026 interrupt-names = "host_intr0", "host_intr1", 2027 "host_intr2", "host_intr3", 2028 "host_intr4", "host_intr5", 2029 "host_intr6", "host_intr7"; 2030 }; 2031 2032 pru0_0: pru@34000 { 2033 compatible = "ti,j721e-pru"; 2034 reg = <0x34000 0x3000>, 2035 <0x22000 0x100>, 2036 <0x22400 0x100>; 2037 reg-names = "iram", "control", "debug"; 2038 firmware-name = "j7-pru0_0-fw"; 2039 }; 2040 2041 rtu0_0: rtu@4000 { 2042 compatible = "ti,j721e-rtu"; 2043 reg = <0x4000 0x2000>, 2044 <0x23000 0x100>, 2045 <0x23400 0x100>; 2046 reg-names = "iram", "control", "debug"; 2047 firmware-name = "j7-rtu0_0-fw"; 2048 }; 2049 2050 tx_pru0_0: txpru@a000 { 2051 compatible = "ti,j721e-tx-pru"; 2052 reg = <0xa000 0x1800>, 2053 <0x25000 0x100>, 2054 <0x25400 0x100>; 2055 reg-names = "iram", "control", "debug"; 2056 firmware-name = "j7-txpru0_0-fw"; 2057 }; 2058 2059 pru0_1: pru@38000 { 2060 compatible = "ti,j721e-pru"; 2061 reg = <0x38000 0x3000>, 2062 <0x24000 0x100>, 2063 <0x24400 0x100>; 2064 reg-names = "iram", "control", "debug"; 2065 firmware-name = "j7-pru0_1-fw"; 2066 }; 2067 2068 rtu0_1: rtu@6000 { 2069 compatible = "ti,j721e-rtu"; 2070 reg = <0x6000 0x2000>, 2071 <0x23800 0x100>, 2072 <0x23c00 0x100>; 2073 reg-names = "iram", "control", "debug"; 2074 firmware-name = "j7-rtu0_1-fw"; 2075 }; 2076 2077 tx_pru0_1: txpru@c000 { 2078 compatible = "ti,j721e-tx-pru"; 2079 reg = <0xc000 0x1800>, 2080 <0x25800 0x100>, 2081 <0x25c00 0x100>; 2082 reg-names = "iram", "control", "debug"; 2083 firmware-name = "j7-txpru0_1-fw"; 2084 }; 2085 2086 icssg0_mdio: mdio@32400 { 2087 compatible = "ti,davinci_mdio"; 2088 reg = <0x32400 0x100>; 2089 clocks = <&k3_clks 119 1>; 2090 clock-names = "fck"; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 bus_freq = <1000000>; 2094 }; 2095 }; 2096 2097 icssg1: icssg@b100000 { 2098 compatible = "ti,j721e-icssg"; 2099 reg = <0x00 0xb100000 0x00 0x80000>; 2100 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2101 #address-cells = <1>; 2102 #size-cells = <1>; 2103 ranges = <0x0 0x00 0x0b100000 0x100000>; 2104 2105 icssg1_mem: memories@b100000 { 2106 reg = <0x0 0x2000>, 2107 <0x2000 0x2000>, 2108 <0x10000 0x10000>; 2109 reg-names = "dram0", "dram1", 2110 "shrdram2"; 2111 }; 2112 2113 icssg1_cfg: cfg@26000 { 2114 compatible = "ti,pruss-cfg", "syscon"; 2115 reg = <0x26000 0x200>; 2116 #address-cells = <1>; 2117 #size-cells = <1>; 2118 ranges = <0x0 0x26000 0x2000>; 2119 2120 clocks { 2121 #address-cells = <1>; 2122 #size-cells = <0>; 2123 2124 icssg1_coreclk_mux: coreclk-mux@3c { 2125 reg = <0x3c>; 2126 #clock-cells = <0>; 2127 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2128 <&k3_clks 120 4>; /* icssg1_iclk */ 2129 assigned-clocks = <&icssg1_coreclk_mux>; 2130 assigned-clock-parents = <&k3_clks 120 4>; 2131 }; 2132 2133 icssg1_iepclk_mux: iepclk-mux@30 { 2134 reg = <0x30>; 2135 #clock-cells = <0>; 2136 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2137 <&icssg1_coreclk_mux>; /* core_clk */ 2138 assigned-clocks = <&icssg1_iepclk_mux>; 2139 assigned-clock-parents = <&icssg1_coreclk_mux>; 2140 }; 2141 }; 2142 }; 2143 2144 icssg1_mii_rt: mii-rt@32000 { 2145 compatible = "ti,pruss-mii", "syscon"; 2146 reg = <0x32000 0x100>; 2147 }; 2148 2149 icssg1_mii_g_rt: mii-g-rt@33000 { 2150 compatible = "ti,pruss-mii-g", "syscon"; 2151 reg = <0x33000 0x1000>; 2152 }; 2153 2154 icssg1_intc: interrupt-controller@20000 { 2155 compatible = "ti,icssg-intc"; 2156 reg = <0x20000 0x2000>; 2157 interrupt-controller; 2158 #interrupt-cells = <3>; 2159 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2167 interrupt-names = "host_intr0", "host_intr1", 2168 "host_intr2", "host_intr3", 2169 "host_intr4", "host_intr5", 2170 "host_intr6", "host_intr7"; 2171 }; 2172 2173 pru1_0: pru@34000 { 2174 compatible = "ti,j721e-pru"; 2175 reg = <0x34000 0x4000>, 2176 <0x22000 0x100>, 2177 <0x22400 0x100>; 2178 reg-names = "iram", "control", "debug"; 2179 firmware-name = "j7-pru1_0-fw"; 2180 }; 2181 2182 rtu1_0: rtu@4000 { 2183 compatible = "ti,j721e-rtu"; 2184 reg = <0x4000 0x2000>, 2185 <0x23000 0x100>, 2186 <0x23400 0x100>; 2187 reg-names = "iram", "control", "debug"; 2188 firmware-name = "j7-rtu1_0-fw"; 2189 }; 2190 2191 tx_pru1_0: txpru@a000 { 2192 compatible = "ti,j721e-tx-pru"; 2193 reg = <0xa000 0x1800>, 2194 <0x25000 0x100>, 2195 <0x25400 0x100>; 2196 reg-names = "iram", "control", "debug"; 2197 firmware-name = "j7-txpru1_0-fw"; 2198 }; 2199 2200 pru1_1: pru@38000 { 2201 compatible = "ti,j721e-pru"; 2202 reg = <0x38000 0x4000>, 2203 <0x24000 0x100>, 2204 <0x24400 0x100>; 2205 reg-names = "iram", "control", "debug"; 2206 firmware-name = "j7-pru1_1-fw"; 2207 }; 2208 2209 rtu1_1: rtu@6000 { 2210 compatible = "ti,j721e-rtu"; 2211 reg = <0x6000 0x2000>, 2212 <0x23800 0x100>, 2213 <0x23c00 0x100>; 2214 reg-names = "iram", "control", "debug"; 2215 firmware-name = "j7-rtu1_1-fw"; 2216 }; 2217 2218 tx_pru1_1: txpru@c000 { 2219 compatible = "ti,j721e-tx-pru"; 2220 reg = <0xc000 0x1800>, 2221 <0x25800 0x100>, 2222 <0x25c00 0x100>; 2223 reg-names = "iram", "control", "debug"; 2224 firmware-name = "j7-txpru1_1-fw"; 2225 }; 2226 2227 icssg1_mdio: mdio@32400 { 2228 compatible = "ti,davinci_mdio"; 2229 reg = <0x32400 0x100>; 2230 clocks = <&k3_clks 120 4>; 2231 clock-names = "fck"; 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 bus_freq = <1000000>; 2235 }; 2236 }; 2237 2238 main_mcan0: can@2701000 { 2239 compatible = "bosch,m_can"; 2240 reg = <0x00 0x02701000 0x00 0x200>, 2241 <0x00 0x02708000 0x00 0x8000>; 2242 reg-names = "m_can", "message_ram"; 2243 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2244 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2245 clock-names = "hclk", "cclk"; 2246 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2248 interrupt-names = "int0", "int1"; 2249 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2250 status = "disabled"; 2251 }; 2252 2253 main_mcan1: can@2711000 { 2254 compatible = "bosch,m_can"; 2255 reg = <0x00 0x02711000 0x00 0x200>, 2256 <0x00 0x02718000 0x00 0x8000>; 2257 reg-names = "m_can", "message_ram"; 2258 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2259 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2260 clock-names = "hclk", "cclk"; 2261 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2263 interrupt-names = "int0", "int1"; 2264 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2265 status = "disabled"; 2266 }; 2267 2268 main_mcan2: can@2721000 { 2269 compatible = "bosch,m_can"; 2270 reg = <0x00 0x02721000 0x00 0x200>, 2271 <0x00 0x02728000 0x00 0x8000>; 2272 reg-names = "m_can", "message_ram"; 2273 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2274 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2275 clock-names = "hclk", "cclk"; 2276 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2278 interrupt-names = "int0", "int1"; 2279 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2280 status = "disabled"; 2281 }; 2282 2283 main_mcan3: can@2731000 { 2284 compatible = "bosch,m_can"; 2285 reg = <0x00 0x02731000 0x00 0x200>, 2286 <0x00 0x02738000 0x00 0x8000>; 2287 reg-names = "m_can", "message_ram"; 2288 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2289 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2290 clock-names = "hclk", "cclk"; 2291 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2293 interrupt-names = "int0", "int1"; 2294 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2295 status = "disabled"; 2296 }; 2297 2298 main_mcan4: can@2741000 { 2299 compatible = "bosch,m_can"; 2300 reg = <0x00 0x02741000 0x00 0x200>, 2301 <0x00 0x02748000 0x00 0x8000>; 2302 reg-names = "m_can", "message_ram"; 2303 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2304 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2305 clock-names = "hclk", "cclk"; 2306 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2308 interrupt-names = "int0", "int1"; 2309 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2310 status = "disabled"; 2311 }; 2312 2313 main_mcan5: can@2751000 { 2314 compatible = "bosch,m_can"; 2315 reg = <0x00 0x02751000 0x00 0x200>, 2316 <0x00 0x02758000 0x00 0x8000>; 2317 reg-names = "m_can", "message_ram"; 2318 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2319 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2320 clock-names = "hclk", "cclk"; 2321 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2322 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2323 interrupt-names = "int0", "int1"; 2324 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2325 status = "disabled"; 2326 }; 2327 2328 main_mcan6: can@2761000 { 2329 compatible = "bosch,m_can"; 2330 reg = <0x00 0x02761000 0x00 0x200>, 2331 <0x00 0x02768000 0x00 0x8000>; 2332 reg-names = "m_can", "message_ram"; 2333 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2334 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2335 clock-names = "hclk", "cclk"; 2336 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2338 interrupt-names = "int0", "int1"; 2339 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2340 status = "disabled"; 2341 }; 2342 2343 main_mcan7: can@2771000 { 2344 compatible = "bosch,m_can"; 2345 reg = <0x00 0x02771000 0x00 0x200>, 2346 <0x00 0x02778000 0x00 0x8000>; 2347 reg-names = "m_can", "message_ram"; 2348 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2349 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2350 clock-names = "hclk", "cclk"; 2351 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2353 interrupt-names = "int0", "int1"; 2354 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2355 status = "disabled"; 2356 }; 2357 2358 main_mcan8: can@2781000 { 2359 compatible = "bosch,m_can"; 2360 reg = <0x00 0x02781000 0x00 0x200>, 2361 <0x00 0x02788000 0x00 0x8000>; 2362 reg-names = "m_can", "message_ram"; 2363 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2364 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2365 clock-names = "hclk", "cclk"; 2366 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2368 interrupt-names = "int0", "int1"; 2369 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2370 status = "disabled"; 2371 }; 2372 2373 main_mcan9: can@2791000 { 2374 compatible = "bosch,m_can"; 2375 reg = <0x00 0x02791000 0x00 0x200>, 2376 <0x00 0x02798000 0x00 0x8000>; 2377 reg-names = "m_can", "message_ram"; 2378 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2379 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2380 clock-names = "hclk", "cclk"; 2381 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2383 interrupt-names = "int0", "int1"; 2384 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2385 status = "disabled"; 2386 }; 2387 2388 main_mcan10: can@27a1000 { 2389 compatible = "bosch,m_can"; 2390 reg = <0x00 0x027a1000 0x00 0x200>, 2391 <0x00 0x027a8000 0x00 0x8000>; 2392 reg-names = "m_can", "message_ram"; 2393 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2394 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2395 clock-names = "hclk", "cclk"; 2396 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2398 interrupt-names = "int0", "int1"; 2399 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2400 status = "disabled"; 2401 }; 2402 2403 main_mcan11: can@27b1000 { 2404 compatible = "bosch,m_can"; 2405 reg = <0x00 0x027b1000 0x00 0x200>, 2406 <0x00 0x027b8000 0x00 0x8000>; 2407 reg-names = "m_can", "message_ram"; 2408 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2409 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2410 clock-names = "hclk", "cclk"; 2411 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2412 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2413 interrupt-names = "int0", "int1"; 2414 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2415 status = "disabled"; 2416 }; 2417 2418 main_mcan12: can@27c1000 { 2419 compatible = "bosch,m_can"; 2420 reg = <0x00 0x027c1000 0x00 0x200>, 2421 <0x00 0x027c8000 0x00 0x8000>; 2422 reg-names = "m_can", "message_ram"; 2423 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2424 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2425 clock-names = "hclk", "cclk"; 2426 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2428 interrupt-names = "int0", "int1"; 2429 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2430 status = "disabled"; 2431 }; 2432 2433 main_mcan13: can@27d1000 { 2434 compatible = "bosch,m_can"; 2435 reg = <0x00 0x027d1000 0x00 0x200>, 2436 <0x00 0x027d8000 0x00 0x8000>; 2437 reg-names = "m_can", "message_ram"; 2438 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2439 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2440 clock-names = "hclk", "cclk"; 2441 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2443 interrupt-names = "int0", "int1"; 2444 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2445 status = "disabled"; 2446 }; 2447 2448 main_spi0: spi@2100000 { 2449 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2450 reg = <0x00 0x02100000 0x00 0x400>; 2451 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2452 #address-cells = <1>; 2453 #size-cells = <0>; 2454 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2455 clocks = <&k3_clks 266 1>; 2456 status = "disabled"; 2457 }; 2458 2459 main_spi1: spi@2110000 { 2460 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2461 reg = <0x00 0x02110000 0x00 0x400>; 2462 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2463 #address-cells = <1>; 2464 #size-cells = <0>; 2465 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2466 clocks = <&k3_clks 267 1>; 2467 status = "disabled"; 2468 }; 2469 2470 main_spi2: spi@2120000 { 2471 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2472 reg = <0x00 0x02120000 0x00 0x400>; 2473 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2474 #address-cells = <1>; 2475 #size-cells = <0>; 2476 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2477 clocks = <&k3_clks 268 1>; 2478 status = "disabled"; 2479 }; 2480 2481 main_spi3: spi@2130000 { 2482 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2483 reg = <0x00 0x02130000 0x00 0x400>; 2484 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2485 #address-cells = <1>; 2486 #size-cells = <0>; 2487 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2488 clocks = <&k3_clks 269 1>; 2489 status = "disabled"; 2490 }; 2491 2492 main_spi4: spi@2140000 { 2493 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2494 reg = <0x00 0x02140000 0x00 0x400>; 2495 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2496 #address-cells = <1>; 2497 #size-cells = <0>; 2498 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2499 clocks = <&k3_clks 270 1>; 2500 status = "disabled"; 2501 }; 2502 2503 main_spi5: spi@2150000 { 2504 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2505 reg = <0x00 0x02150000 0x00 0x400>; 2506 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2507 #address-cells = <1>; 2508 #size-cells = <0>; 2509 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2510 clocks = <&k3_clks 271 1>; 2511 status = "disabled"; 2512 }; 2513 2514 main_spi6: spi@2160000 { 2515 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2516 reg = <0x00 0x02160000 0x00 0x400>; 2517 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2518 #address-cells = <1>; 2519 #size-cells = <0>; 2520 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2521 clocks = <&k3_clks 272 1>; 2522 status = "disabled"; 2523 }; 2524 2525 main_spi7: spi@2170000 { 2526 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2527 reg = <0x00 0x02170000 0x00 0x400>; 2528 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2529 #address-cells = <1>; 2530 #size-cells = <0>; 2531 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2532 clocks = <&k3_clks 273 1>; 2533 status = "disabled"; 2534 }; 2535}; 2536