1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7#include <dt-bindings/phy/phy.h>
8#include <dt-bindings/phy/phy-ti.h>
9#include <dt-bindings/mux/mux.h>
10#include <dt-bindings/mux/ti-serdes.h>
11
12/ {
13	cmn_refclk: clock-cmnrefclk {
14		#clock-cells = <0>;
15		compatible = "fixed-clock";
16		clock-frequency = <0>;
17	};
18
19	cmn_refclk1: clock-cmnrefclk1 {
20		#clock-cells = <0>;
21		compatible = "fixed-clock";
22		clock-frequency = <0>;
23	};
24};
25
26&cbass_main {
27	msmc_ram: sram@70000000 {
28		compatible = "mmio-sram";
29		reg = <0x0 0x70000000 0x0 0x800000>;
30		#address-cells = <1>;
31		#size-cells = <1>;
32		ranges = <0x0 0x0 0x70000000 0x800000>;
33
34		atf-sram@0 {
35			reg = <0x0 0x20000>;
36		};
37	};
38
39	scm_conf: scm-conf@100000 {
40		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
41		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
42		#address-cells = <1>;
43		#size-cells = <1>;
44		ranges = <0x0 0x0 0x00100000 0x1c000>;
45
46		serdes_ln_ctrl: mux-controller@4080 {
47			compatible = "mmio-mux";
48			reg = <0x00004080 0x50>;
49			#mux-control-cells = <1>;
50			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
51					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
52					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
53					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
54					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
55					/* SERDES4 lane0/1/2/3 select */
56			idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
57				      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
58				      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
59				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
60				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
61				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
62		};
63
64		usb_serdes_mux: mux-controller@4000 {
65			compatible = "mmio-mux";
66			#mux-control-cells = <1>;
67			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
68					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
69	    };
70	};
71
72	gic500: interrupt-controller@1800000 {
73		compatible = "arm,gic-v3";
74		#address-cells = <2>;
75		#size-cells = <2>;
76		ranges;
77		#interrupt-cells = <3>;
78		interrupt-controller;
79		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
80		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */
81		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
82		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
83		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */
84
85		/* vcpumntirq: virtual CPU interface maintenance interrupt */
86		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
87
88		gic_its: msi-controller@1820000 {
89			compatible = "arm,gic-v3-its";
90			reg = <0x00 0x01820000 0x00 0x10000>;
91			socionext,synquacer-pre-its = <0x1000000 0x400000>;
92			msi-controller;
93			#msi-cells = <1>;
94		};
95	};
96
97	main_gpio_intr: interrupt-controller@a00000 {
98		compatible = "ti,sci-intr";
99		reg = <0x00 0x00a00000 0x00 0x800>;
100		ti,intr-trigger-type = <1>;
101		interrupt-controller;
102		interrupt-parent = <&gic500>;
103		#interrupt-cells = <1>;
104		ti,sci = <&dmsc>;
105		ti,sci-dev-id = <131>;
106		ti,interrupt-ranges = <8 392 56>;
107	};
108
109	main_navss: bus@30000000 {
110		compatible = "simple-mfd";
111		#address-cells = <2>;
112		#size-cells = <2>;
113		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
114		dma-coherent;
115		dma-ranges;
116
117		ti,sci-dev-id = <199>;
118
119		main_navss_intr: interrupt-controller@310e0000 {
120			compatible = "ti,sci-intr";
121			reg = <0x0 0x310e0000 0x0 0x4000>;
122			ti,intr-trigger-type = <4>;
123			interrupt-controller;
124			interrupt-parent = <&gic500>;
125			#interrupt-cells = <1>;
126			ti,sci = <&dmsc>;
127			ti,sci-dev-id = <213>;
128			ti,interrupt-ranges = <0 64 64>,
129					      <64 448 64>,
130					      <128 672 64>;
131		};
132
133		main_udmass_inta: interrupt-controller@33d00000 {
134			compatible = "ti,sci-inta";
135			reg = <0x0 0x33d00000 0x0 0x100000>;
136			interrupt-controller;
137			interrupt-parent = <&main_navss_intr>;
138			msi-controller;
139			#interrupt-cells = <0>;
140			ti,sci = <&dmsc>;
141			ti,sci-dev-id = <209>;
142			ti,interrupt-ranges = <0 0 256>;
143		};
144
145		secure_proxy_main: mailbox@32c00000 {
146			compatible = "ti,am654-secure-proxy";
147			#mbox-cells = <1>;
148			reg-names = "target_data", "rt", "scfg";
149			reg = <0x00 0x32c00000 0x00 0x100000>,
150			      <0x00 0x32400000 0x00 0x100000>,
151			      <0x00 0x32800000 0x00 0x100000>;
152			interrupt-names = "rx_011";
153			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
154		};
155
156		smmu0: iommu@36600000 {
157			compatible = "arm,smmu-v3";
158			reg = <0x0 0x36600000 0x0 0x100000>;
159			interrupt-parent = <&gic500>;
160			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
161				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
162			interrupt-names = "eventq", "gerror";
163			#iommu-cells = <1>;
164		};
165
166		hwspinlock: spinlock@30e00000 {
167			compatible = "ti,am654-hwspinlock";
168			reg = <0x00 0x30e00000 0x00 0x1000>;
169			#hwlock-cells = <1>;
170		};
171
172		mailbox0_cluster0: mailbox@31f80000 {
173			compatible = "ti,am654-mailbox";
174			reg = <0x00 0x31f80000 0x00 0x200>;
175			#mbox-cells = <1>;
176			ti,mbox-num-users = <4>;
177			ti,mbox-num-fifos = <16>;
178			interrupt-parent = <&main_navss_intr>;
179		};
180
181		mailbox0_cluster1: mailbox@31f81000 {
182			compatible = "ti,am654-mailbox";
183			reg = <0x00 0x31f81000 0x00 0x200>;
184			#mbox-cells = <1>;
185			ti,mbox-num-users = <4>;
186			ti,mbox-num-fifos = <16>;
187			interrupt-parent = <&main_navss_intr>;
188		};
189
190		mailbox0_cluster2: mailbox@31f82000 {
191			compatible = "ti,am654-mailbox";
192			reg = <0x00 0x31f82000 0x00 0x200>;
193			#mbox-cells = <1>;
194			ti,mbox-num-users = <4>;
195			ti,mbox-num-fifos = <16>;
196			interrupt-parent = <&main_navss_intr>;
197		};
198
199		mailbox0_cluster3: mailbox@31f83000 {
200			compatible = "ti,am654-mailbox";
201			reg = <0x00 0x31f83000 0x00 0x200>;
202			#mbox-cells = <1>;
203			ti,mbox-num-users = <4>;
204			ti,mbox-num-fifos = <16>;
205			interrupt-parent = <&main_navss_intr>;
206		};
207
208		mailbox0_cluster4: mailbox@31f84000 {
209			compatible = "ti,am654-mailbox";
210			reg = <0x00 0x31f84000 0x00 0x200>;
211			#mbox-cells = <1>;
212			ti,mbox-num-users = <4>;
213			ti,mbox-num-fifos = <16>;
214			interrupt-parent = <&main_navss_intr>;
215		};
216
217		mailbox0_cluster5: mailbox@31f85000 {
218			compatible = "ti,am654-mailbox";
219			reg = <0x00 0x31f85000 0x00 0x200>;
220			#mbox-cells = <1>;
221			ti,mbox-num-users = <4>;
222			ti,mbox-num-fifos = <16>;
223			interrupt-parent = <&main_navss_intr>;
224		};
225
226		mailbox0_cluster6: mailbox@31f86000 {
227			compatible = "ti,am654-mailbox";
228			reg = <0x00 0x31f86000 0x00 0x200>;
229			#mbox-cells = <1>;
230			ti,mbox-num-users = <4>;
231			ti,mbox-num-fifos = <16>;
232			interrupt-parent = <&main_navss_intr>;
233		};
234
235		mailbox0_cluster7: mailbox@31f87000 {
236			compatible = "ti,am654-mailbox";
237			reg = <0x00 0x31f87000 0x00 0x200>;
238			#mbox-cells = <1>;
239			ti,mbox-num-users = <4>;
240			ti,mbox-num-fifos = <16>;
241			interrupt-parent = <&main_navss_intr>;
242		};
243
244		mailbox0_cluster8: mailbox@31f88000 {
245			compatible = "ti,am654-mailbox";
246			reg = <0x00 0x31f88000 0x00 0x200>;
247			#mbox-cells = <1>;
248			ti,mbox-num-users = <4>;
249			ti,mbox-num-fifos = <16>;
250			interrupt-parent = <&main_navss_intr>;
251		};
252
253		mailbox0_cluster9: mailbox@31f89000 {
254			compatible = "ti,am654-mailbox";
255			reg = <0x00 0x31f89000 0x00 0x200>;
256			#mbox-cells = <1>;
257			ti,mbox-num-users = <4>;
258			ti,mbox-num-fifos = <16>;
259			interrupt-parent = <&main_navss_intr>;
260		};
261
262		mailbox0_cluster10: mailbox@31f8a000 {
263			compatible = "ti,am654-mailbox";
264			reg = <0x00 0x31f8a000 0x00 0x200>;
265			#mbox-cells = <1>;
266			ti,mbox-num-users = <4>;
267			ti,mbox-num-fifos = <16>;
268			interrupt-parent = <&main_navss_intr>;
269		};
270
271		mailbox0_cluster11: mailbox@31f8b000 {
272			compatible = "ti,am654-mailbox";
273			reg = <0x00 0x31f8b000 0x00 0x200>;
274			#mbox-cells = <1>;
275			ti,mbox-num-users = <4>;
276			ti,mbox-num-fifos = <16>;
277			interrupt-parent = <&main_navss_intr>;
278		};
279
280		main_ringacc: ringacc@3c000000 {
281			compatible = "ti,am654-navss-ringacc";
282			reg =	<0x0 0x3c000000 0x0 0x400000>,
283				<0x0 0x38000000 0x0 0x400000>,
284				<0x0 0x31120000 0x0 0x100>,
285				<0x0 0x33000000 0x0 0x40000>;
286			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
287			ti,num-rings = <1024>;
288			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
289			ti,sci = <&dmsc>;
290			ti,sci-dev-id = <211>;
291			msi-parent = <&main_udmass_inta>;
292		};
293
294		main_udmap: dma-controller@31150000 {
295			compatible = "ti,j721e-navss-main-udmap";
296			reg =	<0x0 0x31150000 0x0 0x100>,
297				<0x0 0x34000000 0x0 0x100000>,
298				<0x0 0x35000000 0x0 0x100000>;
299			reg-names = "gcfg", "rchanrt", "tchanrt";
300			msi-parent = <&main_udmass_inta>;
301			#dma-cells = <1>;
302
303			ti,sci = <&dmsc>;
304			ti,sci-dev-id = <212>;
305			ti,ringacc = <&main_ringacc>;
306
307			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
308						<0x0f>, /* TX_HCHAN */
309						<0x10>; /* TX_UHCHAN */
310			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
311						<0x0b>, /* RX_HCHAN */
312						<0x0c>; /* RX_UHCHAN */
313			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
314		};
315
316		cpts@310d0000 {
317			compatible = "ti,j721e-cpts";
318			reg = <0x0 0x310d0000 0x0 0x400>;
319			reg-names = "cpts";
320			clocks = <&k3_clks 201 1>;
321			clock-names = "cpts";
322			interrupts-extended = <&main_navss_intr 391>;
323			interrupt-names = "cpts";
324			ti,cpts-periodic-outputs = <6>;
325			ti,cpts-ext-ts-inputs = <8>;
326		};
327	};
328
329	main_crypto: crypto@4e00000 {
330		compatible = "ti,j721e-sa2ul";
331		reg = <0x0 0x4e00000 0x0 0x1200>;
332		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
333		#address-cells = <2>;
334		#size-cells = <2>;
335		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
336
337		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
338				<&main_udmap 0x4001>;
339		dma-names = "tx", "rx1", "rx2";
340		dma-coherent;
341
342		rng: rng@4e10000 {
343			compatible = "inside-secure,safexcel-eip76";
344			reg = <0x0 0x4e10000 0x0 0x7d>;
345			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
346			clocks = <&k3_clks 264 2>;
347		};
348	};
349
350	main_pmx0: pinctrl@11c000 {
351		compatible = "pinctrl-single";
352		/* Proxy 0 addressing */
353		reg = <0x0 0x11c000 0x0 0x2b4>;
354		#pinctrl-cells = <1>;
355		pinctrl-single,register-width = <32>;
356		pinctrl-single,function-mask = <0xffffffff>;
357	};
358
359	serdes_wiz0: wiz@5000000 {
360		compatible = "ti,j721e-wiz-16g";
361		#address-cells = <1>;
362		#size-cells = <1>;
363		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
364		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
365		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
366		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
367		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
368		num-lanes = <2>;
369		#reset-cells = <1>;
370		ranges = <0x5000000 0x0 0x5000000 0x10000>;
371
372		wiz0_pll0_refclk: pll0-refclk {
373			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
374			#clock-cells = <0>;
375			assigned-clocks = <&wiz0_pll0_refclk>;
376			assigned-clock-parents = <&k3_clks 292 11>;
377		};
378
379		wiz0_pll1_refclk: pll1-refclk {
380			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
381			#clock-cells = <0>;
382			assigned-clocks = <&wiz0_pll1_refclk>;
383			assigned-clock-parents = <&k3_clks 292 0>;
384		};
385
386		wiz0_refclk_dig: refclk-dig {
387			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
388			#clock-cells = <0>;
389			assigned-clocks = <&wiz0_refclk_dig>;
390			assigned-clock-parents = <&k3_clks 292 11>;
391		};
392
393		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
394			clocks = <&wiz0_refclk_dig>;
395			#clock-cells = <0>;
396		};
397
398		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
399			clocks = <&wiz0_pll1_refclk>;
400			#clock-cells = <0>;
401		};
402
403		serdes0: serdes@5000000 {
404			compatible = "ti,sierra-phy-t0";
405			reg-names = "serdes";
406			reg = <0x5000000 0x10000>;
407			#address-cells = <1>;
408			#size-cells = <0>;
409			#clock-cells = <1>;
410			resets = <&serdes_wiz0 0>;
411			reset-names = "sierra_reset";
412			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
413				 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
414			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
415				      "pll0_refclk", "pll1_refclk";
416		};
417	};
418
419	serdes_wiz1: wiz@5010000 {
420		compatible = "ti,j721e-wiz-16g";
421		#address-cells = <1>;
422		#size-cells = <1>;
423		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
424		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
425		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
426		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
427		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
428		num-lanes = <2>;
429		#reset-cells = <1>;
430		ranges = <0x5010000 0x0 0x5010000 0x10000>;
431
432		wiz1_pll0_refclk: pll0-refclk {
433			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
434			#clock-cells = <0>;
435			assigned-clocks = <&wiz1_pll0_refclk>;
436			assigned-clock-parents = <&k3_clks 293 13>;
437		};
438
439		wiz1_pll1_refclk: pll1-refclk {
440			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
441			#clock-cells = <0>;
442			assigned-clocks = <&wiz1_pll1_refclk>;
443			assigned-clock-parents = <&k3_clks 293 0>;
444		};
445
446		wiz1_refclk_dig: refclk-dig {
447			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
448			#clock-cells = <0>;
449			assigned-clocks = <&wiz1_refclk_dig>;
450			assigned-clock-parents = <&k3_clks 293 13>;
451		};
452
453		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
454			clocks = <&wiz1_refclk_dig>;
455			#clock-cells = <0>;
456		};
457
458		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
459			clocks = <&wiz1_pll1_refclk>;
460			#clock-cells = <0>;
461		};
462
463		serdes1: serdes@5010000 {
464			compatible = "ti,sierra-phy-t0";
465			reg-names = "serdes";
466			reg = <0x5010000 0x10000>;
467			#address-cells = <1>;
468			#size-cells = <0>;
469			#clock-cells = <1>;
470			resets = <&serdes_wiz1 0>;
471			reset-names = "sierra_reset";
472			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
473				 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
474			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
475				      "pll0_refclk", "pll1_refclk";
476		};
477	};
478
479	serdes_wiz2: wiz@5020000 {
480		compatible = "ti,j721e-wiz-16g";
481		#address-cells = <1>;
482		#size-cells = <1>;
483		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
484		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
485		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
486		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
487		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
488		num-lanes = <2>;
489		#reset-cells = <1>;
490		ranges = <0x5020000 0x0 0x5020000 0x10000>;
491
492		wiz2_pll0_refclk: pll0-refclk {
493			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
494			#clock-cells = <0>;
495			assigned-clocks = <&wiz2_pll0_refclk>;
496			assigned-clock-parents = <&k3_clks 294 11>;
497		};
498
499		wiz2_pll1_refclk: pll1-refclk {
500			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
501			#clock-cells = <0>;
502			assigned-clocks = <&wiz2_pll1_refclk>;
503			assigned-clock-parents = <&k3_clks 294 0>;
504		};
505
506		wiz2_refclk_dig: refclk-dig {
507			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
508			#clock-cells = <0>;
509			assigned-clocks = <&wiz2_refclk_dig>;
510			assigned-clock-parents = <&k3_clks 294 11>;
511		};
512
513		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
514			clocks = <&wiz2_refclk_dig>;
515			#clock-cells = <0>;
516		};
517
518		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
519			clocks = <&wiz2_pll1_refclk>;
520			#clock-cells = <0>;
521		};
522
523		serdes2: serdes@5020000 {
524			compatible = "ti,sierra-phy-t0";
525			reg-names = "serdes";
526			reg = <0x5020000 0x10000>;
527			#address-cells = <1>;
528			#size-cells = <0>;
529			#clock-cells = <1>;
530			resets = <&serdes_wiz2 0>;
531			reset-names = "sierra_reset";
532			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
533				 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
534			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
535				      "pll0_refclk", "pll1_refclk";
536		};
537	};
538
539	serdes_wiz3: wiz@5030000 {
540		compatible = "ti,j721e-wiz-16g";
541		#address-cells = <1>;
542		#size-cells = <1>;
543		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
544		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
545		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
546		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
547		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
548		num-lanes = <2>;
549		#reset-cells = <1>;
550		ranges = <0x5030000 0x0 0x5030000 0x10000>;
551
552		wiz3_pll0_refclk: pll0-refclk {
553			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
554			#clock-cells = <0>;
555			assigned-clocks = <&wiz3_pll0_refclk>;
556			assigned-clock-parents = <&k3_clks 295 9>;
557		};
558
559		wiz3_pll1_refclk: pll1-refclk {
560			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
561			#clock-cells = <0>;
562			assigned-clocks = <&wiz3_pll1_refclk>;
563			assigned-clock-parents = <&k3_clks 295 0>;
564		};
565
566		wiz3_refclk_dig: refclk-dig {
567			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
568			#clock-cells = <0>;
569			assigned-clocks = <&wiz3_refclk_dig>;
570			assigned-clock-parents = <&k3_clks 295 9>;
571		};
572
573		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
574			clocks = <&wiz3_refclk_dig>;
575			#clock-cells = <0>;
576		};
577
578		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
579			clocks = <&wiz3_pll1_refclk>;
580			#clock-cells = <0>;
581		};
582
583		serdes3: serdes@5030000 {
584			compatible = "ti,sierra-phy-t0";
585			reg-names = "serdes";
586			reg = <0x5030000 0x10000>;
587			#address-cells = <1>;
588			#size-cells = <0>;
589			#clock-cells = <1>;
590			resets = <&serdes_wiz3 0>;
591			reset-names = "sierra_reset";
592			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
593				 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
594			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
595				      "pll0_refclk", "pll1_refclk";
596		};
597	};
598
599	pcie0_rc: pcie@2900000 {
600		compatible = "ti,j721e-pcie-host";
601		reg = <0x00 0x02900000 0x00 0x1000>,
602		      <0x00 0x02907000 0x00 0x400>,
603		      <0x00 0x0d000000 0x00 0x00800000>,
604		      <0x00 0x10000000 0x00 0x00001000>;
605		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
606		interrupt-names = "link_state";
607		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
608		device_type = "pci";
609		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
610		max-link-speed = <3>;
611		num-lanes = <2>;
612		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
613		clocks = <&k3_clks 239 1>;
614		clock-names = "fck";
615		#address-cells = <3>;
616		#size-cells = <2>;
617		bus-range = <0x0 0xff>;
618		vendor-id = <0x104c>;
619		device-id = <0xb00d>;
620		msi-map = <0x0 &gic_its 0x0 0x10000>;
621		dma-coherent;
622		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
623			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
624		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
625	};
626
627	pcie0_ep: pcie-ep@2900000 {
628		compatible = "ti,j721e-pcie-ep";
629		reg = <0x00 0x02900000 0x00 0x1000>,
630		      <0x00 0x02907000 0x00 0x400>,
631		      <0x00 0x0d000000 0x00 0x00800000>,
632		      <0x00 0x10000000 0x00 0x08000000>;
633		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
634		interrupt-names = "link_state";
635		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
636		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
637		max-link-speed = <3>;
638		num-lanes = <2>;
639		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
640		clocks = <&k3_clks 239 1>;
641		clock-names = "fck";
642		max-functions = /bits/ 8 <6>;
643		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
644		dma-coherent;
645	};
646
647	pcie1_rc: pcie@2910000 {
648		compatible = "ti,j721e-pcie-host";
649		reg = <0x00 0x02910000 0x00 0x1000>,
650		      <0x00 0x02917000 0x00 0x400>,
651		      <0x00 0x0d800000 0x00 0x00800000>,
652		      <0x00 0x18000000 0x00 0x00001000>;
653		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
654		interrupt-names = "link_state";
655		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
656		device_type = "pci";
657		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
658		max-link-speed = <3>;
659		num-lanes = <2>;
660		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
661		clocks = <&k3_clks 240 1>;
662		clock-names = "fck";
663		#address-cells = <3>;
664		#size-cells = <2>;
665		bus-range = <0x0 0xff>;
666		vendor-id = <0x104c>;
667		device-id = <0xb00d>;
668		msi-map = <0x0 &gic_its 0x10000 0x10000>;
669		dma-coherent;
670		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
671			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
672		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
673	};
674
675	pcie1_ep: pcie-ep@2910000 {
676		compatible = "ti,j721e-pcie-ep";
677		reg = <0x00 0x02910000 0x00 0x1000>,
678		      <0x00 0x02917000 0x00 0x400>,
679		      <0x00 0x0d800000 0x00 0x00800000>,
680		      <0x00 0x18000000 0x00 0x08000000>;
681		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
682		interrupt-names = "link_state";
683		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
684		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
685		max-link-speed = <3>;
686		num-lanes = <2>;
687		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
688		clocks = <&k3_clks 240 1>;
689		clock-names = "fck";
690		max-functions = /bits/ 8 <6>;
691		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
692		dma-coherent;
693	};
694
695	pcie2_rc: pcie@2920000 {
696		compatible = "ti,j721e-pcie-host";
697		reg = <0x00 0x02920000 0x00 0x1000>,
698		      <0x00 0x02927000 0x00 0x400>,
699		      <0x00 0x0e000000 0x00 0x00800000>,
700		      <0x44 0x00000000 0x00 0x00001000>;
701		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
702		interrupt-names = "link_state";
703		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
704		device_type = "pci";
705		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
706		max-link-speed = <3>;
707		num-lanes = <2>;
708		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
709		clocks = <&k3_clks 241 1>;
710		clock-names = "fck";
711		#address-cells = <3>;
712		#size-cells = <2>;
713		bus-range = <0x0 0xff>;
714		vendor-id = <0x104c>;
715		device-id = <0xb00d>;
716		msi-map = <0x0 &gic_its 0x20000 0x10000>;
717		dma-coherent;
718		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
719			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
720		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
721	};
722
723	pcie2_ep: pcie-ep@2920000 {
724		compatible = "ti,j721e-pcie-ep";
725		reg = <0x00 0x02920000 0x00 0x1000>,
726		      <0x00 0x02927000 0x00 0x400>,
727		      <0x00 0x0e000000 0x00 0x00800000>,
728		      <0x44 0x00000000 0x00 0x08000000>;
729		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
730		interrupt-names = "link_state";
731		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
732		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
733		max-link-speed = <3>;
734		num-lanes = <2>;
735		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
736		clocks = <&k3_clks 241 1>;
737		clock-names = "fck";
738		max-functions = /bits/ 8 <6>;
739		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
740		dma-coherent;
741	};
742
743	pcie3_rc: pcie@2930000 {
744		compatible = "ti,j721e-pcie-host";
745		reg = <0x00 0x02930000 0x00 0x1000>,
746		      <0x00 0x02937000 0x00 0x400>,
747		      <0x00 0x0e800000 0x00 0x00800000>,
748		      <0x44 0x10000000 0x00 0x00001000>;
749		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
750		interrupt-names = "link_state";
751		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
752		device_type = "pci";
753		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
754		max-link-speed = <3>;
755		num-lanes = <2>;
756		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
757		clocks = <&k3_clks 242 1>;
758		clock-names = "fck";
759		#address-cells = <3>;
760		#size-cells = <2>;
761		bus-range = <0x0 0xff>;
762		vendor-id = <0x104c>;
763		device-id = <0xb00d>;
764		msi-map = <0x0 &gic_its 0x30000 0x10000>;
765		dma-coherent;
766		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
767			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
768		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
769	};
770
771	pcie3_ep: pcie-ep@2930000 {
772		compatible = "ti,j721e-pcie-ep";
773		reg = <0x00 0x02930000 0x00 0x1000>,
774		      <0x00 0x02937000 0x00 0x400>,
775		      <0x00 0x0e800000 0x00 0x00800000>,
776		      <0x44 0x10000000 0x00 0x08000000>;
777		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
778		interrupt-names = "link_state";
779		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
780		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
781		max-link-speed = <3>;
782		num-lanes = <2>;
783		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
784		clocks = <&k3_clks 242 1>;
785		clock-names = "fck";
786		max-functions = /bits/ 8 <6>;
787		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
788		dma-coherent;
789		#address-cells = <2>;
790		#size-cells = <2>;
791	};
792
793	serdes_wiz4: wiz@5050000 {
794		compatible = "ti,am64-wiz-10g";
795		#address-cells = <1>;
796		#size-cells = <1>;
797		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
798		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
799		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
800		assigned-clocks = <&k3_clks 297 9>;
801		assigned-clock-parents = <&k3_clks 297 10>;
802		assigned-clock-rates = <19200000>;
803		num-lanes = <4>;
804		#reset-cells = <1>;
805		#clock-cells = <1>;
806		ranges = <0x05050000 0x00 0x05050000 0x010000>,
807			<0x0a030a00 0x00 0x0a030a00 0x40>;
808
809		serdes4: serdes@5050000 {
810			/*
811			 * Note: we also map DPTX PHY registers as the Torrent
812			 * needs to manage those.
813			 */
814			compatible = "ti,j721e-serdes-10g";
815			reg = <0x05050000 0x010000>,
816			      <0x0a030a00 0x40>; /* DPTX PHY */
817			reg-names = "torrent_phy", "dptx_phy";
818
819			resets = <&serdes_wiz4 0>;
820			reset-names = "torrent_reset";
821			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
822			clock-names = "refclk";
823			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
824					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
825					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
826			assigned-clock-parents = <&k3_clks 297 9>,
827						 <&k3_clks 297 9>,
828						 <&k3_clks 297 9>;
829			#address-cells = <1>;
830			#size-cells = <0>;
831		};
832	};
833
834	main_uart0: serial@2800000 {
835		compatible = "ti,j721e-uart", "ti,am654-uart";
836		reg = <0x00 0x02800000 0x00 0x100>;
837		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
838		clock-frequency = <48000000>;
839		current-speed = <115200>;
840		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
841		clocks = <&k3_clks 146 0>;
842		clock-names = "fclk";
843	};
844
845	main_uart1: serial@2810000 {
846		compatible = "ti,j721e-uart", "ti,am654-uart";
847		reg = <0x00 0x02810000 0x00 0x100>;
848		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
849		clock-frequency = <48000000>;
850		current-speed = <115200>;
851		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
852		clocks = <&k3_clks 278 0>;
853		clock-names = "fclk";
854	};
855
856	main_uart2: serial@2820000 {
857		compatible = "ti,j721e-uart", "ti,am654-uart";
858		reg = <0x00 0x02820000 0x00 0x100>;
859		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
860		clock-frequency = <48000000>;
861		current-speed = <115200>;
862		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
863		clocks = <&k3_clks 279 0>;
864		clock-names = "fclk";
865	};
866
867	main_uart3: serial@2830000 {
868		compatible = "ti,j721e-uart", "ti,am654-uart";
869		reg = <0x00 0x02830000 0x00 0x100>;
870		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
871		clock-frequency = <48000000>;
872		current-speed = <115200>;
873		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
874		clocks = <&k3_clks 280 0>;
875		clock-names = "fclk";
876	};
877
878	main_uart4: serial@2840000 {
879		compatible = "ti,j721e-uart", "ti,am654-uart";
880		reg = <0x00 0x02840000 0x00 0x100>;
881		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
882		clock-frequency = <48000000>;
883		current-speed = <115200>;
884		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
885		clocks = <&k3_clks 281 0>;
886		clock-names = "fclk";
887	};
888
889	main_uart5: serial@2850000 {
890		compatible = "ti,j721e-uart", "ti,am654-uart";
891		reg = <0x00 0x02850000 0x00 0x100>;
892		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
893		clock-frequency = <48000000>;
894		current-speed = <115200>;
895		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
896		clocks = <&k3_clks 282 0>;
897		clock-names = "fclk";
898	};
899
900	main_uart6: serial@2860000 {
901		compatible = "ti,j721e-uart", "ti,am654-uart";
902		reg = <0x00 0x02860000 0x00 0x100>;
903		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
904		clock-frequency = <48000000>;
905		current-speed = <115200>;
906		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
907		clocks = <&k3_clks 283 0>;
908		clock-names = "fclk";
909	};
910
911	main_uart7: serial@2870000 {
912		compatible = "ti,j721e-uart", "ti,am654-uart";
913		reg = <0x00 0x02870000 0x00 0x100>;
914		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
915		clock-frequency = <48000000>;
916		current-speed = <115200>;
917		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
918		clocks = <&k3_clks 284 0>;
919		clock-names = "fclk";
920	};
921
922	main_uart8: serial@2880000 {
923		compatible = "ti,j721e-uart", "ti,am654-uart";
924		reg = <0x00 0x02880000 0x00 0x100>;
925		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
926		clock-frequency = <48000000>;
927		current-speed = <115200>;
928		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
929		clocks = <&k3_clks 285 0>;
930		clock-names = "fclk";
931	};
932
933	main_uart9: serial@2890000 {
934		compatible = "ti,j721e-uart", "ti,am654-uart";
935		reg = <0x00 0x02890000 0x00 0x100>;
936		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
937		clock-frequency = <48000000>;
938		current-speed = <115200>;
939		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
940		clocks = <&k3_clks 286 0>;
941		clock-names = "fclk";
942	};
943
944	main_gpio0: gpio@600000 {
945		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
946		reg = <0x0 0x00600000 0x0 0x100>;
947		gpio-controller;
948		#gpio-cells = <2>;
949		interrupt-parent = <&main_gpio_intr>;
950		interrupts = <256>, <257>, <258>, <259>,
951			     <260>, <261>, <262>, <263>;
952		interrupt-controller;
953		#interrupt-cells = <2>;
954		ti,ngpio = <128>;
955		ti,davinci-gpio-unbanked = <0>;
956		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
957		clocks = <&k3_clks 105 0>;
958		clock-names = "gpio";
959	};
960
961	main_gpio1: gpio@601000 {
962		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
963		reg = <0x0 0x00601000 0x0 0x100>;
964		gpio-controller;
965		#gpio-cells = <2>;
966		interrupt-parent = <&main_gpio_intr>;
967		interrupts = <288>, <289>, <290>;
968		interrupt-controller;
969		#interrupt-cells = <2>;
970		ti,ngpio = <36>;
971		ti,davinci-gpio-unbanked = <0>;
972		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
973		clocks = <&k3_clks 106 0>;
974		clock-names = "gpio";
975	};
976
977	main_gpio2: gpio@610000 {
978		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
979		reg = <0x0 0x00610000 0x0 0x100>;
980		gpio-controller;
981		#gpio-cells = <2>;
982		interrupt-parent = <&main_gpio_intr>;
983		interrupts = <264>, <265>, <266>, <267>,
984			     <268>, <269>, <270>, <271>;
985		interrupt-controller;
986		#interrupt-cells = <2>;
987		ti,ngpio = <128>;
988		ti,davinci-gpio-unbanked = <0>;
989		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
990		clocks = <&k3_clks 107 0>;
991		clock-names = "gpio";
992	};
993
994	main_gpio3: gpio@611000 {
995		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
996		reg = <0x0 0x00611000 0x0 0x100>;
997		gpio-controller;
998		#gpio-cells = <2>;
999		interrupt-parent = <&main_gpio_intr>;
1000		interrupts = <292>, <293>, <294>;
1001		interrupt-controller;
1002		#interrupt-cells = <2>;
1003		ti,ngpio = <36>;
1004		ti,davinci-gpio-unbanked = <0>;
1005		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1006		clocks = <&k3_clks 108 0>;
1007		clock-names = "gpio";
1008	};
1009
1010	main_gpio4: gpio@620000 {
1011		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1012		reg = <0x0 0x00620000 0x0 0x100>;
1013		gpio-controller;
1014		#gpio-cells = <2>;
1015		interrupt-parent = <&main_gpio_intr>;
1016		interrupts = <272>, <273>, <274>, <275>,
1017			     <276>, <277>, <278>, <279>;
1018		interrupt-controller;
1019		#interrupt-cells = <2>;
1020		ti,ngpio = <128>;
1021		ti,davinci-gpio-unbanked = <0>;
1022		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1023		clocks = <&k3_clks 109 0>;
1024		clock-names = "gpio";
1025	};
1026
1027	main_gpio5: gpio@621000 {
1028		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1029		reg = <0x0 0x00621000 0x0 0x100>;
1030		gpio-controller;
1031		#gpio-cells = <2>;
1032		interrupt-parent = <&main_gpio_intr>;
1033		interrupts = <296>, <297>, <298>;
1034		interrupt-controller;
1035		#interrupt-cells = <2>;
1036		ti,ngpio = <36>;
1037		ti,davinci-gpio-unbanked = <0>;
1038		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1039		clocks = <&k3_clks 110 0>;
1040		clock-names = "gpio";
1041	};
1042
1043	main_gpio6: gpio@630000 {
1044		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1045		reg = <0x0 0x00630000 0x0 0x100>;
1046		gpio-controller;
1047		#gpio-cells = <2>;
1048		interrupt-parent = <&main_gpio_intr>;
1049		interrupts = <280>, <281>, <282>, <283>,
1050			     <284>, <285>, <286>, <287>;
1051		interrupt-controller;
1052		#interrupt-cells = <2>;
1053		ti,ngpio = <128>;
1054		ti,davinci-gpio-unbanked = <0>;
1055		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1056		clocks = <&k3_clks 111 0>;
1057		clock-names = "gpio";
1058	};
1059
1060	main_gpio7: gpio@631000 {
1061		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1062		reg = <0x0 0x00631000 0x0 0x100>;
1063		gpio-controller;
1064		#gpio-cells = <2>;
1065		interrupt-parent = <&main_gpio_intr>;
1066		interrupts = <300>, <301>, <302>;
1067		interrupt-controller;
1068		#interrupt-cells = <2>;
1069		ti,ngpio = <36>;
1070		ti,davinci-gpio-unbanked = <0>;
1071		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1072		clocks = <&k3_clks 112 0>;
1073		clock-names = "gpio";
1074	};
1075
1076	main_sdhci0: mmc@4f80000 {
1077		compatible = "ti,j721e-sdhci-8bit";
1078		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1079		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1080		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1081		clock-names = "clk_ahb", "clk_xin";
1082		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1083		assigned-clocks = <&k3_clks 91 1>;
1084		assigned-clock-parents = <&k3_clks 91 2>;
1085		bus-width = <8>;
1086		mmc-hs200-1_8v;
1087		mmc-ddr-1_8v;
1088		ti,otap-del-sel-legacy = <0xf>;
1089		ti,otap-del-sel-mmc-hs = <0xf>;
1090		ti,otap-del-sel-ddr52 = <0x5>;
1091		ti,otap-del-sel-hs200 = <0x6>;
1092		ti,otap-del-sel-hs400 = <0x0>;
1093		ti,itap-del-sel-legacy = <0x10>;
1094		ti,itap-del-sel-mmc-hs = <0xa>;
1095		ti,itap-del-sel-ddr52 = <0x3>;
1096		ti,trm-icp = <0x8>;
1097		ti,strobe-sel = <0x77>;
1098		dma-coherent;
1099	};
1100
1101	main_sdhci1: mmc@4fb0000 {
1102		compatible = "ti,j721e-sdhci-4bit";
1103		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1104		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1105		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1106		clock-names = "clk_ahb", "clk_xin";
1107		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1108		assigned-clocks = <&k3_clks 92 0>;
1109		assigned-clock-parents = <&k3_clks 92 1>;
1110		ti,otap-del-sel-legacy = <0x0>;
1111		ti,otap-del-sel-sd-hs = <0xf>;
1112		ti,otap-del-sel-sdr12 = <0xf>;
1113		ti,otap-del-sel-sdr25 = <0xf>;
1114		ti,otap-del-sel-sdr50 = <0xc>;
1115		ti,otap-del-sel-ddr50 = <0xc>;
1116		ti,itap-del-sel-legacy = <0x0>;
1117		ti,itap-del-sel-sd-hs = <0x0>;
1118		ti,itap-del-sel-sdr12 = <0x0>;
1119		ti,itap-del-sel-sdr25 = <0x0>;
1120		ti,itap-del-sel-ddr50 = <0x2>;
1121		ti,trm-icp = <0x8>;
1122		ti,clkbuf-sel = <0x7>;
1123		dma-coherent;
1124		sdhci-caps-mask = <0x2 0x0>;
1125	};
1126
1127	main_sdhci2: mmc@4f98000 {
1128		compatible = "ti,j721e-sdhci-4bit";
1129		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1130		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1131		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1132		clock-names = "clk_ahb", "clk_xin";
1133		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1134		assigned-clocks = <&k3_clks 93 0>;
1135		assigned-clock-parents = <&k3_clks 93 1>;
1136		ti,otap-del-sel-legacy = <0x0>;
1137		ti,otap-del-sel-sd-hs = <0xf>;
1138		ti,otap-del-sel-sdr12 = <0xf>;
1139		ti,otap-del-sel-sdr25 = <0xf>;
1140		ti,otap-del-sel-sdr50 = <0xc>;
1141		ti,otap-del-sel-ddr50 = <0xc>;
1142		ti,itap-del-sel-legacy = <0x0>;
1143		ti,itap-del-sel-sd-hs = <0x0>;
1144		ti,itap-del-sel-sdr12 = <0x0>;
1145		ti,itap-del-sel-sdr25 = <0x0>;
1146		ti,itap-del-sel-ddr50 = <0x2>;
1147		ti,trm-icp = <0x8>;
1148		ti,clkbuf-sel = <0x7>;
1149		dma-coherent;
1150		sdhci-caps-mask = <0x2 0x0>;
1151	};
1152
1153	usbss0: cdns-usb@4104000 {
1154		compatible = "ti,j721e-usb";
1155		reg = <0x00 0x4104000 0x00 0x100>;
1156		dma-coherent;
1157		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1158		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1159		clock-names = "ref", "lpm";
1160		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
1161		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1162		#address-cells = <2>;
1163		#size-cells = <2>;
1164		ranges;
1165
1166		usb0: usb@6000000 {
1167			compatible = "cdns,usb3";
1168			reg = <0x00 0x6000000 0x00 0x10000>,
1169			      <0x00 0x6010000 0x00 0x10000>,
1170			      <0x00 0x6020000 0x00 0x10000>;
1171			reg-names = "otg", "xhci", "dev";
1172			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1173				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
1174				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1175			interrupt-names = "host",
1176					  "peripheral",
1177					  "otg";
1178			maximum-speed = "super-speed";
1179			dr_mode = "otg";
1180		};
1181	};
1182
1183	usbss1: cdns-usb@4114000 {
1184		compatible = "ti,j721e-usb";
1185		reg = <0x00 0x4114000 0x00 0x100>;
1186		dma-coherent;
1187		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1188		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1189		clock-names = "ref", "lpm";
1190		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
1191		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1192		#address-cells = <2>;
1193		#size-cells = <2>;
1194		ranges;
1195
1196		usb1: usb@6400000 {
1197			compatible = "cdns,usb3";
1198			reg = <0x00 0x6400000 0x00 0x10000>,
1199			      <0x00 0x6410000 0x00 0x10000>,
1200			      <0x00 0x6420000 0x00 0x10000>;
1201			reg-names = "otg", "xhci", "dev";
1202			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1203				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
1204				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1205			interrupt-names = "host",
1206					  "peripheral",
1207					  "otg";
1208			maximum-speed = "super-speed";
1209			dr_mode = "otg";
1210		};
1211	};
1212
1213	main_i2c0: i2c@2000000 {
1214		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1215		reg = <0x0 0x2000000 0x0 0x100>;
1216		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1217		#address-cells = <1>;
1218		#size-cells = <0>;
1219		clock-names = "fck";
1220		clocks = <&k3_clks 187 0>;
1221		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1222	};
1223
1224	main_i2c1: i2c@2010000 {
1225		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1226		reg = <0x0 0x2010000 0x0 0x100>;
1227		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1228		#address-cells = <1>;
1229		#size-cells = <0>;
1230		clock-names = "fck";
1231		clocks = <&k3_clks 188 0>;
1232		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1233	};
1234
1235	main_i2c2: i2c@2020000 {
1236		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1237		reg = <0x0 0x2020000 0x0 0x100>;
1238		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1239		#address-cells = <1>;
1240		#size-cells = <0>;
1241		clock-names = "fck";
1242		clocks = <&k3_clks 189 0>;
1243		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1244	};
1245
1246	main_i2c3: i2c@2030000 {
1247		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1248		reg = <0x0 0x2030000 0x0 0x100>;
1249		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1250		#address-cells = <1>;
1251		#size-cells = <0>;
1252		clock-names = "fck";
1253		clocks = <&k3_clks 190 0>;
1254		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1255	};
1256
1257	main_i2c4: i2c@2040000 {
1258		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1259		reg = <0x0 0x2040000 0x0 0x100>;
1260		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1261		#address-cells = <1>;
1262		#size-cells = <0>;
1263		clock-names = "fck";
1264		clocks = <&k3_clks 191 0>;
1265		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1266	};
1267
1268	main_i2c5: i2c@2050000 {
1269		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1270		reg = <0x0 0x2050000 0x0 0x100>;
1271		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1272		#address-cells = <1>;
1273		#size-cells = <0>;
1274		clock-names = "fck";
1275		clocks = <&k3_clks 192 0>;
1276		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1277	};
1278
1279	main_i2c6: i2c@2060000 {
1280		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1281		reg = <0x0 0x2060000 0x0 0x100>;
1282		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1283		#address-cells = <1>;
1284		#size-cells = <0>;
1285		clock-names = "fck";
1286		clocks = <&k3_clks 193 0>;
1287		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1288	};
1289
1290	ufs_wrapper: ufs-wrapper@4e80000 {
1291		compatible = "ti,j721e-ufs";
1292		reg = <0x0 0x4e80000 0x0 0x100>;
1293		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1294		clocks = <&k3_clks 277 1>;
1295		assigned-clocks = <&k3_clks 277 1>;
1296		assigned-clock-parents = <&k3_clks 277 4>;
1297		ranges;
1298		#address-cells = <2>;
1299		#size-cells = <2>;
1300
1301		ufs@4e84000 {
1302			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1303			reg = <0x0 0x4e84000 0x0 0x10000>;
1304			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1305			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1306			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1307			clock-names = "core_clk", "phy_clk", "ref_clk";
1308			dma-coherent;
1309		};
1310	};
1311
1312	mhdp: dp-bridge@a000000 {
1313		compatible = "ti,j721e-mhdp8546";
1314		/*
1315		 * Note: we do not map DPTX PHY area, as that is handled by
1316		 * the PHY driver.
1317		 */
1318		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1319		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
1320		reg-names = "mhdptx", "j721e-intg";
1321
1322		clocks = <&k3_clks 151 36>;
1323
1324		interrupt-parent = <&gic500>;
1325		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
1326
1327		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1328
1329		dp0_ports: ports {
1330			#address-cells = <1>;
1331			#size-cells = <0>;
1332
1333			port@0 {
1334			    reg = <0>;
1335			};
1336
1337			port@4 {
1338			    reg = <4>;
1339			};
1340		};
1341	};
1342
1343	dss: dss@4a00000 {
1344		compatible = "ti,j721e-dss";
1345		reg =
1346			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
1347			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1348			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1349			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1350
1351			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1352			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1353			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1354			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1355
1356			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1357			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1358			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1359			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1360
1361			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1362			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1363			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1364			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1365			<0x00 0x04af0000 0x00 0x10000>; /* wb */
1366
1367		reg-names = "common_m", "common_s0",
1368			"common_s1", "common_s2",
1369			"vidl1", "vidl2","vid1","vid2",
1370			"ovr1", "ovr2", "ovr3", "ovr4",
1371			"vp1", "vp2", "vp3", "vp4",
1372			"wb";
1373
1374		clocks =	<&k3_clks 152 0>,
1375				<&k3_clks 152 1>,
1376				<&k3_clks 152 4>,
1377				<&k3_clks 152 9>,
1378				<&k3_clks 152 13>;
1379		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1380
1381		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1382
1383		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1384			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1385			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1386			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1387		interrupt-names = "common_m",
1388				  "common_s0",
1389				  "common_s1",
1390				  "common_s2";
1391
1392		dss_ports: ports {
1393		};
1394	};
1395
1396	mcasp0: mcasp@2b00000 {
1397		compatible = "ti,am33xx-mcasp-audio";
1398		reg = <0x0 0x02b00000 0x0 0x2000>,
1399			<0x0 0x02b08000 0x0 0x1000>;
1400		reg-names = "mpu","dat";
1401		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1402				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1403		interrupt-names = "tx", "rx";
1404
1405		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1406		dma-names = "tx", "rx";
1407
1408		clocks = <&k3_clks 174 1>;
1409		clock-names = "fck";
1410		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1411	};
1412
1413	mcasp1: mcasp@2b10000 {
1414		compatible = "ti,am33xx-mcasp-audio";
1415		reg = <0x0 0x02b10000 0x0 0x2000>,
1416			<0x0 0x02b18000 0x0 0x1000>;
1417		reg-names = "mpu","dat";
1418		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1419				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1420		interrupt-names = "tx", "rx";
1421
1422		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1423		dma-names = "tx", "rx";
1424
1425		clocks = <&k3_clks 175 1>;
1426		clock-names = "fck";
1427		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1428	};
1429
1430	mcasp2: mcasp@2b20000 {
1431		compatible = "ti,am33xx-mcasp-audio";
1432		reg = <0x0 0x02b20000 0x0 0x2000>,
1433			<0x0 0x02b28000 0x0 0x1000>;
1434		reg-names = "mpu","dat";
1435		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1436				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1437		interrupt-names = "tx", "rx";
1438
1439		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1440		dma-names = "tx", "rx";
1441
1442		clocks = <&k3_clks 176 1>;
1443		clock-names = "fck";
1444		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1445	};
1446
1447	mcasp3: mcasp@2b30000 {
1448		compatible = "ti,am33xx-mcasp-audio";
1449		reg = <0x0 0x02b30000 0x0 0x2000>,
1450			<0x0 0x02b38000 0x0 0x1000>;
1451		reg-names = "mpu","dat";
1452		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1453				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1454		interrupt-names = "tx", "rx";
1455
1456		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1457		dma-names = "tx", "rx";
1458
1459		clocks = <&k3_clks 177 1>;
1460		clock-names = "fck";
1461		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1462	};
1463
1464	mcasp4: mcasp@2b40000 {
1465		compatible = "ti,am33xx-mcasp-audio";
1466		reg = <0x0 0x02b40000 0x0 0x2000>,
1467			<0x0 0x02b48000 0x0 0x1000>;
1468		reg-names = "mpu","dat";
1469		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1470				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1471		interrupt-names = "tx", "rx";
1472
1473		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1474		dma-names = "tx", "rx";
1475
1476		clocks = <&k3_clks 178 1>;
1477		clock-names = "fck";
1478		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1479	};
1480
1481	mcasp5: mcasp@2b50000 {
1482		compatible = "ti,am33xx-mcasp-audio";
1483		reg = <0x0 0x02b50000 0x0 0x2000>,
1484			<0x0 0x02b58000 0x0 0x1000>;
1485		reg-names = "mpu","dat";
1486		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1487				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1488		interrupt-names = "tx", "rx";
1489
1490		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1491		dma-names = "tx", "rx";
1492
1493		clocks = <&k3_clks 179 1>;
1494		clock-names = "fck";
1495		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1496	};
1497
1498	mcasp6: mcasp@2b60000 {
1499		compatible = "ti,am33xx-mcasp-audio";
1500		reg = <0x0 0x02b60000 0x0 0x2000>,
1501			<0x0 0x02b68000 0x0 0x1000>;
1502		reg-names = "mpu","dat";
1503		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1504				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1505		interrupt-names = "tx", "rx";
1506
1507		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1508		dma-names = "tx", "rx";
1509
1510		clocks = <&k3_clks 180 1>;
1511		clock-names = "fck";
1512		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1513	};
1514
1515	mcasp7: mcasp@2b70000 {
1516		compatible = "ti,am33xx-mcasp-audio";
1517		reg = <0x0 0x02b70000 0x0 0x2000>,
1518			<0x0 0x02b78000 0x0 0x1000>;
1519		reg-names = "mpu","dat";
1520		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1521				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1522		interrupt-names = "tx", "rx";
1523
1524		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1525		dma-names = "tx", "rx";
1526
1527		clocks = <&k3_clks 181 1>;
1528		clock-names = "fck";
1529		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1530	};
1531
1532	mcasp8: mcasp@2b80000 {
1533		compatible = "ti,am33xx-mcasp-audio";
1534		reg = <0x0 0x02b80000 0x0 0x2000>,
1535			<0x0 0x02b88000 0x0 0x1000>;
1536		reg-names = "mpu","dat";
1537		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1538				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1539		interrupt-names = "tx", "rx";
1540
1541		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1542		dma-names = "tx", "rx";
1543
1544		clocks = <&k3_clks 182 1>;
1545		clock-names = "fck";
1546		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1547	};
1548
1549	mcasp9: mcasp@2b90000 {
1550		compatible = "ti,am33xx-mcasp-audio";
1551		reg = <0x0 0x02b90000 0x0 0x2000>,
1552			<0x0 0x02b98000 0x0 0x1000>;
1553		reg-names = "mpu","dat";
1554		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1555				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1556		interrupt-names = "tx", "rx";
1557
1558		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1559		dma-names = "tx", "rx";
1560
1561		clocks = <&k3_clks 183 1>;
1562		clock-names = "fck";
1563		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1564	};
1565
1566	mcasp10: mcasp@2ba0000 {
1567		compatible = "ti,am33xx-mcasp-audio";
1568		reg = <0x0 0x02ba0000 0x0 0x2000>,
1569			<0x0 0x02ba8000 0x0 0x1000>;
1570		reg-names = "mpu","dat";
1571		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1572				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1573		interrupt-names = "tx", "rx";
1574
1575		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1576		dma-names = "tx", "rx";
1577
1578		clocks = <&k3_clks 184 1>;
1579		clock-names = "fck";
1580		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1581	};
1582
1583	mcasp11: mcasp@2bb0000 {
1584		compatible = "ti,am33xx-mcasp-audio";
1585		reg = <0x0 0x02bb0000 0x0 0x2000>,
1586			<0x0 0x02bb8000 0x0 0x1000>;
1587		reg-names = "mpu","dat";
1588		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1589				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1590		interrupt-names = "tx", "rx";
1591
1592		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1593		dma-names = "tx", "rx";
1594
1595		clocks = <&k3_clks 185 1>;
1596		clock-names = "fck";
1597		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1598	};
1599
1600	watchdog0: watchdog@2200000 {
1601		compatible = "ti,j7-rti-wdt";
1602		reg = <0x0 0x2200000 0x0 0x100>;
1603		clocks = <&k3_clks 252 1>;
1604		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1605		assigned-clocks = <&k3_clks 252 1>;
1606		assigned-clock-parents = <&k3_clks 252 5>;
1607	};
1608
1609	watchdog1: watchdog@2210000 {
1610		compatible = "ti,j7-rti-wdt";
1611		reg = <0x0 0x2210000 0x0 0x100>;
1612		clocks = <&k3_clks 253 1>;
1613		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1614		assigned-clocks = <&k3_clks 253 1>;
1615		assigned-clock-parents = <&k3_clks 253 5>;
1616	};
1617
1618	main_r5fss0: r5fss@5c00000 {
1619		compatible = "ti,j721e-r5fss";
1620		ti,cluster-mode = <1>;
1621		#address-cells = <1>;
1622		#size-cells = <1>;
1623		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1624			 <0x5d00000 0x00 0x5d00000 0x20000>;
1625		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1626
1627		main_r5fss0_core0: r5f@5c00000 {
1628			compatible = "ti,j721e-r5f";
1629			reg = <0x5c00000 0x00008000>,
1630			      <0x5c10000 0x00008000>;
1631			reg-names = "atcm", "btcm";
1632			ti,sci = <&dmsc>;
1633			ti,sci-dev-id = <245>;
1634			ti,sci-proc-ids = <0x06 0xff>;
1635			resets = <&k3_reset 245 1>;
1636			firmware-name = "j7-main-r5f0_0-fw";
1637			ti,atcm-enable = <1>;
1638			ti,btcm-enable = <1>;
1639			ti,loczrama = <1>;
1640		};
1641
1642		main_r5fss0_core1: r5f@5d00000 {
1643			compatible = "ti,j721e-r5f";
1644			reg = <0x5d00000 0x00008000>,
1645			      <0x5d10000 0x00008000>;
1646			reg-names = "atcm", "btcm";
1647			ti,sci = <&dmsc>;
1648			ti,sci-dev-id = <246>;
1649			ti,sci-proc-ids = <0x07 0xff>;
1650			resets = <&k3_reset 246 1>;
1651			firmware-name = "j7-main-r5f0_1-fw";
1652			ti,atcm-enable = <1>;
1653			ti,btcm-enable = <1>;
1654			ti,loczrama = <1>;
1655		};
1656	};
1657
1658	main_r5fss1: r5fss@5e00000 {
1659		compatible = "ti,j721e-r5fss";
1660		ti,cluster-mode = <1>;
1661		#address-cells = <1>;
1662		#size-cells = <1>;
1663		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1664			 <0x5f00000 0x00 0x5f00000 0x20000>;
1665		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1666
1667		main_r5fss1_core0: r5f@5e00000 {
1668			compatible = "ti,j721e-r5f";
1669			reg = <0x5e00000 0x00008000>,
1670			      <0x5e10000 0x00008000>;
1671			reg-names = "atcm", "btcm";
1672			ti,sci = <&dmsc>;
1673			ti,sci-dev-id = <247>;
1674			ti,sci-proc-ids = <0x08 0xff>;
1675			resets = <&k3_reset 247 1>;
1676			firmware-name = "j7-main-r5f1_0-fw";
1677			ti,atcm-enable = <1>;
1678			ti,btcm-enable = <1>;
1679			ti,loczrama = <1>;
1680		};
1681
1682		main_r5fss1_core1: r5f@5f00000 {
1683			compatible = "ti,j721e-r5f";
1684			reg = <0x5f00000 0x00008000>,
1685			      <0x5f10000 0x00008000>;
1686			reg-names = "atcm", "btcm";
1687			ti,sci = <&dmsc>;
1688			ti,sci-dev-id = <248>;
1689			ti,sci-proc-ids = <0x09 0xff>;
1690			resets = <&k3_reset 248 1>;
1691			firmware-name = "j7-main-r5f1_1-fw";
1692			ti,atcm-enable = <1>;
1693			ti,btcm-enable = <1>;
1694			ti,loczrama = <1>;
1695		};
1696	};
1697
1698	c66_0: dsp@4d80800000 {
1699		compatible = "ti,j721e-c66-dsp";
1700		reg = <0x4d 0x80800000 0x00 0x00048000>,
1701		      <0x4d 0x80e00000 0x00 0x00008000>,
1702		      <0x4d 0x80f00000 0x00 0x00008000>;
1703		reg-names = "l2sram", "l1pram", "l1dram";
1704		ti,sci = <&dmsc>;
1705		ti,sci-dev-id = <142>;
1706		ti,sci-proc-ids = <0x03 0xff>;
1707		resets = <&k3_reset 142 1>;
1708		firmware-name = "j7-c66_0-fw";
1709	};
1710
1711	c66_1: dsp@4d81800000 {
1712		compatible = "ti,j721e-c66-dsp";
1713		reg = <0x4d 0x81800000 0x00 0x00048000>,
1714		      <0x4d 0x81e00000 0x00 0x00008000>,
1715		      <0x4d 0x81f00000 0x00 0x00008000>;
1716		reg-names = "l2sram", "l1pram", "l1dram";
1717		ti,sci = <&dmsc>;
1718		ti,sci-dev-id = <143>;
1719		ti,sci-proc-ids = <0x04 0xff>;
1720		resets = <&k3_reset 143 1>;
1721		firmware-name = "j7-c66_1-fw";
1722	};
1723
1724	c71_0: dsp@64800000 {
1725		compatible = "ti,j721e-c71-dsp";
1726		reg = <0x00 0x64800000 0x00 0x00080000>,
1727		      <0x00 0x64e00000 0x00 0x0000c000>;
1728		reg-names = "l2sram", "l1dram";
1729		ti,sci = <&dmsc>;
1730		ti,sci-dev-id = <15>;
1731		ti,sci-proc-ids = <0x30 0xff>;
1732		resets = <&k3_reset 15 1>;
1733		firmware-name = "j7-c71_0-fw";
1734	};
1735
1736	icssg0: icssg@b000000 {
1737		compatible = "ti,j721e-icssg";
1738		reg = <0x00 0xb000000 0x00 0x80000>;
1739		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1740		#address-cells = <1>;
1741		#size-cells = <1>;
1742		ranges = <0x0 0x00 0x0b000000 0x100000>;
1743
1744		icssg0_mem: memories@0 {
1745			reg = <0x0 0x2000>,
1746			      <0x2000 0x2000>,
1747			      <0x10000 0x10000>;
1748			reg-names = "dram0", "dram1",
1749				    "shrdram2";
1750		};
1751
1752		icssg0_cfg: cfg@26000 {
1753			compatible = "ti,pruss-cfg", "syscon";
1754			reg = <0x26000 0x200>;
1755			#address-cells = <1>;
1756			#size-cells = <1>;
1757			ranges = <0x0 0x26000 0x2000>;
1758
1759			clocks {
1760				#address-cells = <1>;
1761				#size-cells = <0>;
1762
1763				icssg0_coreclk_mux: coreclk-mux@3c {
1764					reg = <0x3c>;
1765					#clock-cells = <0>;
1766					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
1767						 <&k3_clks 119 1>;  /* icssg0_iclk */
1768					assigned-clocks = <&icssg0_coreclk_mux>;
1769					assigned-clock-parents = <&k3_clks 119 1>;
1770				};
1771
1772				icssg0_iepclk_mux: iepclk-mux@30 {
1773					reg = <0x30>;
1774					#clock-cells = <0>;
1775					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
1776						 <&icssg0_coreclk_mux>;	/* core_clk */
1777					assigned-clocks = <&icssg0_iepclk_mux>;
1778					assigned-clock-parents = <&icssg0_coreclk_mux>;
1779				};
1780			};
1781		};
1782
1783		icssg0_mii_rt: mii-rt@32000 {
1784			compatible = "ti,pruss-mii", "syscon";
1785			reg = <0x32000 0x100>;
1786		};
1787
1788		icssg0_mii_g_rt: mii-g-rt@33000 {
1789			compatible = "ti,pruss-mii-g", "syscon";
1790			reg = <0x33000 0x1000>;
1791		};
1792
1793		icssg0_intc: interrupt-controller@20000 {
1794			compatible = "ti,icssg-intc";
1795			reg = <0x20000 0x2000>;
1796			interrupt-controller;
1797			#interrupt-cells = <3>;
1798			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1799				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1800				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1801				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1802				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1803				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1804				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1805				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1806			interrupt-names = "host_intr0", "host_intr1",
1807					  "host_intr2", "host_intr3",
1808					  "host_intr4", "host_intr5",
1809					  "host_intr6", "host_intr7";
1810		};
1811
1812		pru0_0: pru@34000 {
1813			compatible = "ti,j721e-pru";
1814			reg = <0x34000 0x3000>,
1815			      <0x22000 0x100>,
1816			      <0x22400 0x100>;
1817			reg-names = "iram", "control", "debug";
1818			firmware-name = "j7-pru0_0-fw";
1819		};
1820
1821		rtu0_0: rtu@4000 {
1822			compatible = "ti,j721e-rtu";
1823			reg = <0x4000 0x2000>,
1824			      <0x23000 0x100>,
1825			      <0x23400 0x100>;
1826			reg-names = "iram", "control", "debug";
1827			firmware-name = "j7-rtu0_0-fw";
1828		};
1829
1830		tx_pru0_0: txpru@a000 {
1831			compatible = "ti,j721e-tx-pru";
1832			reg = <0xa000 0x1800>,
1833			      <0x25000 0x100>,
1834			      <0x25400 0x100>;
1835			reg-names = "iram", "control", "debug";
1836			firmware-name = "j7-txpru0_0-fw";
1837		};
1838
1839		pru0_1: pru@38000 {
1840			compatible = "ti,j721e-pru";
1841			reg = <0x38000 0x3000>,
1842			      <0x24000 0x100>,
1843			      <0x24400 0x100>;
1844			reg-names = "iram", "control", "debug";
1845			firmware-name = "j7-pru0_1-fw";
1846		};
1847
1848		rtu0_1: rtu@6000 {
1849			compatible = "ti,j721e-rtu";
1850			reg = <0x6000 0x2000>,
1851			      <0x23800 0x100>,
1852			      <0x23c00 0x100>;
1853			reg-names = "iram", "control", "debug";
1854			firmware-name = "j7-rtu0_1-fw";
1855		};
1856
1857		tx_pru0_1: txpru@c000 {
1858			compatible = "ti,j721e-tx-pru";
1859			reg = <0xc000 0x1800>,
1860			      <0x25800 0x100>,
1861			      <0x25c00 0x100>;
1862			reg-names = "iram", "control", "debug";
1863			firmware-name = "j7-txpru0_1-fw";
1864		};
1865
1866		icssg0_mdio: mdio@32400 {
1867			compatible = "ti,davinci_mdio";
1868			reg = <0x32400 0x100>;
1869			clocks = <&k3_clks 119 1>;
1870			clock-names = "fck";
1871			#address-cells = <1>;
1872			#size-cells = <0>;
1873			bus_freq = <1000000>;
1874		};
1875	};
1876
1877	icssg1: icssg@b100000 {
1878		compatible = "ti,j721e-icssg";
1879		reg = <0x00 0xb100000 0x00 0x80000>;
1880		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1881		#address-cells = <1>;
1882		#size-cells = <1>;
1883		ranges = <0x0 0x00 0x0b100000 0x100000>;
1884
1885		icssg1_mem: memories@b100000 {
1886			reg = <0x0 0x2000>,
1887			      <0x2000 0x2000>,
1888			      <0x10000 0x10000>;
1889			reg-names = "dram0", "dram1",
1890				    "shrdram2";
1891		};
1892
1893		icssg1_cfg: cfg@26000 {
1894			compatible = "ti,pruss-cfg", "syscon";
1895			reg = <0x26000 0x200>;
1896			#address-cells = <1>;
1897			#size-cells = <1>;
1898			ranges = <0x0 0x26000 0x2000>;
1899
1900			clocks {
1901				#address-cells = <1>;
1902				#size-cells = <0>;
1903
1904				icssg1_coreclk_mux: coreclk-mux@3c {
1905					reg = <0x3c>;
1906					#clock-cells = <0>;
1907					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
1908						 <&k3_clks 120 4>;  /* icssg1_iclk */
1909					assigned-clocks = <&icssg1_coreclk_mux>;
1910					assigned-clock-parents = <&k3_clks 120 4>;
1911				};
1912
1913				icssg1_iepclk_mux: iepclk-mux@30 {
1914					reg = <0x30>;
1915					#clock-cells = <0>;
1916					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
1917						 <&icssg1_coreclk_mux>;	/* core_clk */
1918					assigned-clocks = <&icssg1_iepclk_mux>;
1919					assigned-clock-parents = <&icssg1_coreclk_mux>;
1920				};
1921			};
1922		};
1923
1924		icssg1_mii_rt: mii-rt@32000 {
1925			compatible = "ti,pruss-mii", "syscon";
1926			reg = <0x32000 0x100>;
1927		};
1928
1929		icssg1_mii_g_rt: mii-g-rt@33000 {
1930			compatible = "ti,pruss-mii-g", "syscon";
1931			reg = <0x33000 0x1000>;
1932		};
1933
1934		icssg1_intc: interrupt-controller@20000 {
1935			compatible = "ti,icssg-intc";
1936			reg = <0x20000 0x2000>;
1937			interrupt-controller;
1938			#interrupt-cells = <3>;
1939			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1940				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1941				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1942				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1943				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1944				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1945				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1946				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1947			interrupt-names = "host_intr0", "host_intr1",
1948					  "host_intr2", "host_intr3",
1949					  "host_intr4", "host_intr5",
1950					  "host_intr6", "host_intr7";
1951		};
1952
1953		pru1_0: pru@34000 {
1954			compatible = "ti,j721e-pru";
1955			reg = <0x34000 0x4000>,
1956			      <0x22000 0x100>,
1957			      <0x22400 0x100>;
1958			reg-names = "iram", "control", "debug";
1959			firmware-name = "j7-pru1_0-fw";
1960		};
1961
1962		rtu1_0: rtu@4000 {
1963			compatible = "ti,j721e-rtu";
1964			reg = <0x4000 0x2000>,
1965			      <0x23000 0x100>,
1966			      <0x23400 0x100>;
1967			reg-names = "iram", "control", "debug";
1968			firmware-name = "j7-rtu1_0-fw";
1969		};
1970
1971		tx_pru1_0: txpru@a000 {
1972			compatible = "ti,j721e-tx-pru";
1973			reg = <0xa000 0x1800>,
1974			      <0x25000 0x100>,
1975			      <0x25400 0x100>;
1976			reg-names = "iram", "control", "debug";
1977			firmware-name = "j7-txpru1_0-fw";
1978		};
1979
1980		pru1_1: pru@38000 {
1981			compatible = "ti,j721e-pru";
1982			reg = <0x38000 0x4000>,
1983			      <0x24000 0x100>,
1984			      <0x24400 0x100>;
1985			reg-names = "iram", "control", "debug";
1986			firmware-name = "j7-pru1_1-fw";
1987		};
1988
1989		rtu1_1: rtu@6000 {
1990			compatible = "ti,j721e-rtu";
1991			reg = <0x6000 0x2000>,
1992			      <0x23800 0x100>,
1993			      <0x23c00 0x100>;
1994			reg-names = "iram", "control", "debug";
1995			firmware-name = "j7-rtu1_1-fw";
1996		};
1997
1998		tx_pru1_1: txpru@c000 {
1999			compatible = "ti,j721e-tx-pru";
2000			reg = <0xc000 0x1800>,
2001			      <0x25800 0x100>,
2002			      <0x25c00 0x100>;
2003			reg-names = "iram", "control", "debug";
2004			firmware-name = "j7-txpru1_1-fw";
2005		};
2006
2007		icssg1_mdio: mdio@32400 {
2008			compatible = "ti,davinci_mdio";
2009			reg = <0x32400 0x100>;
2010			clocks = <&k3_clks 120 4>;
2011			clock-names = "fck";
2012			#address-cells = <1>;
2013			#size-cells = <0>;
2014			bus_freq = <1000000>;
2015		};
2016	};
2017
2018	main_mcan0: can@2701000 {
2019		compatible = "bosch,m_can";
2020		reg = <0x00 0x02701000 0x00 0x200>,
2021		      <0x00 0x02708000 0x00 0x8000>;
2022		reg-names = "m_can", "message_ram";
2023		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2024		clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2025		clock-names = "hclk", "cclk";
2026		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2027			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2028		interrupt-names = "int0", "int1";
2029		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2030	};
2031
2032	main_mcan1: can@2711000 {
2033		compatible = "bosch,m_can";
2034		reg = <0x00 0x02711000 0x00 0x200>,
2035		      <0x00 0x02718000 0x00 0x8000>;
2036		reg-names = "m_can", "message_ram";
2037		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2038		clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2039		clock-names = "hclk", "cclk";
2040		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2041			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
2042		interrupt-names = "int0", "int1";
2043		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2044	};
2045
2046	main_mcan2: can@2721000 {
2047		compatible = "bosch,m_can";
2048		reg = <0x00 0x02721000 0x00 0x200>,
2049		      <0x00 0x02728000 0x00 0x8000>;
2050		reg-names = "m_can", "message_ram";
2051		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2052		clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2053		clock-names = "hclk", "cclk";
2054		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2055			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2056		interrupt-names = "int0", "int1";
2057		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2058	};
2059
2060	main_mcan3: can@2731000 {
2061		compatible = "bosch,m_can";
2062		reg = <0x00 0x02731000 0x00 0x200>,
2063		      <0x00 0x02738000 0x00 0x8000>;
2064		reg-names = "m_can", "message_ram";
2065		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2066		clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2067		clock-names = "hclk", "cclk";
2068		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2069			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2070		interrupt-names = "int0", "int1";
2071		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2072	};
2073
2074	main_mcan4: can@2741000 {
2075		compatible = "bosch,m_can";
2076		reg = <0x00 0x02741000 0x00 0x200>,
2077		      <0x00 0x02748000 0x00 0x8000>;
2078		reg-names = "m_can", "message_ram";
2079		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2080		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2081		clock-names = "hclk", "cclk";
2082		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2083			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2084		interrupt-names = "int0", "int1";
2085		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2086	};
2087
2088	main_mcan5: can@2751000 {
2089		compatible = "bosch,m_can";
2090		reg = <0x00 0x02751000 0x00 0x200>,
2091		      <0x00 0x02758000 0x00 0x8000>;
2092		reg-names = "m_can", "message_ram";
2093		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2094		clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2095		clock-names = "hclk", "cclk";
2096		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2097			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2098		interrupt-names = "int0", "int1";
2099		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2100	};
2101
2102	main_mcan6: can@2761000 {
2103		compatible = "bosch,m_can";
2104		reg = <0x00 0x02761000 0x00 0x200>,
2105		      <0x00 0x02768000 0x00 0x8000>;
2106		reg-names = "m_can", "message_ram";
2107		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2108		clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2109		clock-names = "hclk", "cclk";
2110		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2111			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2112		interrupt-names = "int0", "int1";
2113		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2114	};
2115
2116	main_mcan7: can@2771000 {
2117		compatible = "bosch,m_can";
2118		reg = <0x00 0x02771000 0x00 0x200>,
2119		      <0x00 0x02778000 0x00 0x8000>;
2120		reg-names = "m_can", "message_ram";
2121		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2122		clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2123		clock-names = "hclk", "cclk";
2124		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2125			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2126		interrupt-names = "int0", "int1";
2127		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2128	};
2129
2130	main_mcan8: can@2781000 {
2131		compatible = "bosch,m_can";
2132		reg = <0x00 0x02781000 0x00 0x200>,
2133		      <0x00 0x02788000 0x00 0x8000>;
2134		reg-names = "m_can", "message_ram";
2135		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2136		clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2137		clock-names = "hclk", "cclk";
2138		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2139			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
2140		interrupt-names = "int0", "int1";
2141		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2142	};
2143
2144	main_mcan9: can@2791000 {
2145		compatible = "bosch,m_can";
2146		reg = <0x00 0x02791000 0x00 0x200>,
2147		      <0x00 0x02798000 0x00 0x8000>;
2148		reg-names = "m_can", "message_ram";
2149		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2150		clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2151		clock-names = "hclk", "cclk";
2152		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
2153			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2154		interrupt-names = "int0", "int1";
2155		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2156	};
2157
2158	main_mcan10: can@27a1000 {
2159		compatible = "bosch,m_can";
2160		reg = <0x00 0x027a1000 0x00 0x200>,
2161		      <0x00 0x027a8000 0x00 0x8000>;
2162		reg-names = "m_can", "message_ram";
2163		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2164		clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2165		clock-names = "hclk", "cclk";
2166		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
2167			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2168		interrupt-names = "int0", "int1";
2169		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2170	};
2171
2172	main_mcan11: can@27b1000 {
2173		compatible = "bosch,m_can";
2174		reg = <0x00 0x027b1000 0x00 0x200>,
2175		      <0x00 0x027b8000 0x00 0x8000>;
2176		reg-names = "m_can", "message_ram";
2177		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2178		clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2179		clock-names = "hclk", "cclk";
2180		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
2181			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2182		interrupt-names = "int0", "int1";
2183		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2184	};
2185
2186	main_mcan12: can@27c1000 {
2187		compatible = "bosch,m_can";
2188		reg = <0x00 0x027c1000 0x00 0x200>,
2189		      <0x00 0x027c8000 0x00 0x8000>;
2190		reg-names = "m_can", "message_ram";
2191		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2192		clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2193		clock-names = "hclk", "cclk";
2194		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2195			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
2196		interrupt-names = "int0", "int1";
2197		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2198	};
2199
2200	main_mcan13: can@27d1000 {
2201		compatible = "bosch,m_can";
2202		reg = <0x00 0x027d1000 0x00 0x200>,
2203		      <0x00 0x027d8000 0x00 0x8000>;
2204		reg-names = "m_can", "message_ram";
2205		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2206		clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2207		clock-names = "hclk", "cclk";
2208		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2209			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
2210		interrupt-names = "int0", "int1";
2211		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2212	};
2213};
2214