1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7#include <dt-bindings/phy/phy.h>
8#include <dt-bindings/phy/phy-ti.h>
9#include <dt-bindings/mux/mux.h>
10#include <dt-bindings/mux/ti-serdes.h>
11
12/ {
13	cmn_refclk: clock-cmnrefclk {
14		#clock-cells = <0>;
15		compatible = "fixed-clock";
16		clock-frequency = <0>;
17	};
18
19	cmn_refclk1: clock-cmnrefclk1 {
20		#clock-cells = <0>;
21		compatible = "fixed-clock";
22		clock-frequency = <0>;
23	};
24};
25
26&cbass_main {
27	msmc_ram: sram@70000000 {
28		compatible = "mmio-sram";
29		reg = <0x0 0x70000000 0x0 0x800000>;
30		#address-cells = <1>;
31		#size-cells = <1>;
32		ranges = <0x0 0x0 0x70000000 0x800000>;
33
34		atf-sram@0 {
35			reg = <0x0 0x20000>;
36		};
37	};
38
39	scm_conf: scm-conf@100000 {
40		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
41		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
42		#address-cells = <1>;
43		#size-cells = <1>;
44		ranges = <0x0 0x0 0x00100000 0x1c000>;
45
46		serdes_ln_ctrl: mux-controller@4080 {
47			compatible = "mmio-mux";
48			reg = <0x00004080 0x50>;
49			#mux-control-cells = <1>;
50			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
51					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
52					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
53					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
54					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
55					/* SERDES4 lane0/1/2/3 select */
56			idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
57				      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
58				      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
59				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
60				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
61				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
62		};
63
64		usb_serdes_mux: mux-controller@4000 {
65			compatible = "mmio-mux";
66			#mux-control-cells = <1>;
67			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
68					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
69		};
70
71		ehrpwm_tbclk: clock-controller@4140 {
72			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
73			reg = <0x4140 0x18>;
74			#clock-cells = <1>;
75		};
76	};
77
78	main_ehrpwm0: pwm@3000000 {
79		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
80		#pwm-cells = <3>;
81		reg = <0x00 0x3000000 0x00 0x100>;
82		power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
83		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
84		clock-names = "tbclk", "fck";
85		status = "disabled";
86	};
87
88	main_ehrpwm1: pwm@3010000 {
89		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
90		#pwm-cells = <3>;
91		reg = <0x00 0x3010000 0x00 0x100>;
92		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
93		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
94		clock-names = "tbclk", "fck";
95		status = "disabled";
96	};
97
98	main_ehrpwm2: pwm@3020000 {
99		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
100		#pwm-cells = <3>;
101		reg = <0x00 0x3020000 0x00 0x100>;
102		power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
103		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
104		clock-names = "tbclk", "fck";
105		status = "disabled";
106	};
107
108	main_ehrpwm3: pwm@3030000 {
109		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
110		#pwm-cells = <3>;
111		reg = <0x00 0x3030000 0x00 0x100>;
112		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
113		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
114		clock-names = "tbclk", "fck";
115		status = "disabled";
116	};
117
118	main_ehrpwm4: pwm@3040000 {
119		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
120		#pwm-cells = <3>;
121		reg = <0x00 0x3040000 0x00 0x100>;
122		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
123		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
124		clock-names = "tbclk", "fck";
125		status = "disabled";
126	};
127
128	main_ehrpwm5: pwm@3050000 {
129		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
130		#pwm-cells = <3>;
131		reg = <0x00 0x3050000 0x00 0x100>;
132		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
133		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
134		clock-names = "tbclk", "fck";
135		status = "disabled";
136	};
137
138	gic500: interrupt-controller@1800000 {
139		compatible = "arm,gic-v3";
140		#address-cells = <2>;
141		#size-cells = <2>;
142		ranges;
143		#interrupt-cells = <3>;
144		interrupt-controller;
145		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
146		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */
147		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
148		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
149		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */
150
151		/* vcpumntirq: virtual CPU interface maintenance interrupt */
152		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
153
154		gic_its: msi-controller@1820000 {
155			compatible = "arm,gic-v3-its";
156			reg = <0x00 0x01820000 0x00 0x10000>;
157			socionext,synquacer-pre-its = <0x1000000 0x400000>;
158			msi-controller;
159			#msi-cells = <1>;
160		};
161	};
162
163	main_gpio_intr: interrupt-controller@a00000 {
164		compatible = "ti,sci-intr";
165		reg = <0x00 0x00a00000 0x00 0x800>;
166		ti,intr-trigger-type = <1>;
167		interrupt-controller;
168		interrupt-parent = <&gic500>;
169		#interrupt-cells = <1>;
170		ti,sci = <&dmsc>;
171		ti,sci-dev-id = <131>;
172		ti,interrupt-ranges = <8 392 56>;
173	};
174
175	main_navss: bus@30000000 {
176		compatible = "simple-mfd";
177		#address-cells = <2>;
178		#size-cells = <2>;
179		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
180		dma-coherent;
181		dma-ranges;
182
183		ti,sci-dev-id = <199>;
184
185		main_navss_intr: interrupt-controller@310e0000 {
186			compatible = "ti,sci-intr";
187			reg = <0x0 0x310e0000 0x0 0x4000>;
188			ti,intr-trigger-type = <4>;
189			interrupt-controller;
190			interrupt-parent = <&gic500>;
191			#interrupt-cells = <1>;
192			ti,sci = <&dmsc>;
193			ti,sci-dev-id = <213>;
194			ti,interrupt-ranges = <0 64 64>,
195					      <64 448 64>,
196					      <128 672 64>;
197		};
198
199		main_udmass_inta: interrupt-controller@33d00000 {
200			compatible = "ti,sci-inta";
201			reg = <0x0 0x33d00000 0x0 0x100000>;
202			interrupt-controller;
203			interrupt-parent = <&main_navss_intr>;
204			msi-controller;
205			#interrupt-cells = <0>;
206			ti,sci = <&dmsc>;
207			ti,sci-dev-id = <209>;
208			ti,interrupt-ranges = <0 0 256>;
209		};
210
211		secure_proxy_main: mailbox@32c00000 {
212			compatible = "ti,am654-secure-proxy";
213			#mbox-cells = <1>;
214			reg-names = "target_data", "rt", "scfg";
215			reg = <0x00 0x32c00000 0x00 0x100000>,
216			      <0x00 0x32400000 0x00 0x100000>,
217			      <0x00 0x32800000 0x00 0x100000>;
218			interrupt-names = "rx_011";
219			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
220		};
221
222		smmu0: iommu@36600000 {
223			compatible = "arm,smmu-v3";
224			reg = <0x0 0x36600000 0x0 0x100000>;
225			interrupt-parent = <&gic500>;
226			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
227				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
228			interrupt-names = "eventq", "gerror";
229			#iommu-cells = <1>;
230		};
231
232		hwspinlock: spinlock@30e00000 {
233			compatible = "ti,am654-hwspinlock";
234			reg = <0x00 0x30e00000 0x00 0x1000>;
235			#hwlock-cells = <1>;
236		};
237
238		mailbox0_cluster0: mailbox@31f80000 {
239			compatible = "ti,am654-mailbox";
240			reg = <0x00 0x31f80000 0x00 0x200>;
241			#mbox-cells = <1>;
242			ti,mbox-num-users = <4>;
243			ti,mbox-num-fifos = <16>;
244			interrupt-parent = <&main_navss_intr>;
245			status = "disabled";
246		};
247
248		mailbox0_cluster1: mailbox@31f81000 {
249			compatible = "ti,am654-mailbox";
250			reg = <0x00 0x31f81000 0x00 0x200>;
251			#mbox-cells = <1>;
252			ti,mbox-num-users = <4>;
253			ti,mbox-num-fifos = <16>;
254			interrupt-parent = <&main_navss_intr>;
255			status = "disabled";
256		};
257
258		mailbox0_cluster2: mailbox@31f82000 {
259			compatible = "ti,am654-mailbox";
260			reg = <0x00 0x31f82000 0x00 0x200>;
261			#mbox-cells = <1>;
262			ti,mbox-num-users = <4>;
263			ti,mbox-num-fifos = <16>;
264			interrupt-parent = <&main_navss_intr>;
265			status = "disabled";
266		};
267
268		mailbox0_cluster3: mailbox@31f83000 {
269			compatible = "ti,am654-mailbox";
270			reg = <0x00 0x31f83000 0x00 0x200>;
271			#mbox-cells = <1>;
272			ti,mbox-num-users = <4>;
273			ti,mbox-num-fifos = <16>;
274			interrupt-parent = <&main_navss_intr>;
275			status = "disabled";
276		};
277
278		mailbox0_cluster4: mailbox@31f84000 {
279			compatible = "ti,am654-mailbox";
280			reg = <0x00 0x31f84000 0x00 0x200>;
281			#mbox-cells = <1>;
282			ti,mbox-num-users = <4>;
283			ti,mbox-num-fifos = <16>;
284			interrupt-parent = <&main_navss_intr>;
285			status = "disabled";
286		};
287
288		mailbox0_cluster5: mailbox@31f85000 {
289			compatible = "ti,am654-mailbox";
290			reg = <0x00 0x31f85000 0x00 0x200>;
291			#mbox-cells = <1>;
292			ti,mbox-num-users = <4>;
293			ti,mbox-num-fifos = <16>;
294			interrupt-parent = <&main_navss_intr>;
295			status = "disabled";
296		};
297
298		mailbox0_cluster6: mailbox@31f86000 {
299			compatible = "ti,am654-mailbox";
300			reg = <0x00 0x31f86000 0x00 0x200>;
301			#mbox-cells = <1>;
302			ti,mbox-num-users = <4>;
303			ti,mbox-num-fifos = <16>;
304			interrupt-parent = <&main_navss_intr>;
305			status = "disabled";
306		};
307
308		mailbox0_cluster7: mailbox@31f87000 {
309			compatible = "ti,am654-mailbox";
310			reg = <0x00 0x31f87000 0x00 0x200>;
311			#mbox-cells = <1>;
312			ti,mbox-num-users = <4>;
313			ti,mbox-num-fifos = <16>;
314			interrupt-parent = <&main_navss_intr>;
315			status = "disabled";
316		};
317
318		mailbox0_cluster8: mailbox@31f88000 {
319			compatible = "ti,am654-mailbox";
320			reg = <0x00 0x31f88000 0x00 0x200>;
321			#mbox-cells = <1>;
322			ti,mbox-num-users = <4>;
323			ti,mbox-num-fifos = <16>;
324			interrupt-parent = <&main_navss_intr>;
325			status = "disabled";
326		};
327
328		mailbox0_cluster9: mailbox@31f89000 {
329			compatible = "ti,am654-mailbox";
330			reg = <0x00 0x31f89000 0x00 0x200>;
331			#mbox-cells = <1>;
332			ti,mbox-num-users = <4>;
333			ti,mbox-num-fifos = <16>;
334			interrupt-parent = <&main_navss_intr>;
335			status = "disabled";
336		};
337
338		mailbox0_cluster10: mailbox@31f8a000 {
339			compatible = "ti,am654-mailbox";
340			reg = <0x00 0x31f8a000 0x00 0x200>;
341			#mbox-cells = <1>;
342			ti,mbox-num-users = <4>;
343			ti,mbox-num-fifos = <16>;
344			interrupt-parent = <&main_navss_intr>;
345			status = "disabled";
346		};
347
348		mailbox0_cluster11: mailbox@31f8b000 {
349			compatible = "ti,am654-mailbox";
350			reg = <0x00 0x31f8b000 0x00 0x200>;
351			#mbox-cells = <1>;
352			ti,mbox-num-users = <4>;
353			ti,mbox-num-fifos = <16>;
354			interrupt-parent = <&main_navss_intr>;
355			status = "disabled";
356		};
357
358		main_ringacc: ringacc@3c000000 {
359			compatible = "ti,am654-navss-ringacc";
360			reg =	<0x0 0x3c000000 0x0 0x400000>,
361				<0x0 0x38000000 0x0 0x400000>,
362				<0x0 0x31120000 0x0 0x100>,
363				<0x0 0x33000000 0x0 0x40000>;
364			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
365			ti,num-rings = <1024>;
366			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
367			ti,sci = <&dmsc>;
368			ti,sci-dev-id = <211>;
369			msi-parent = <&main_udmass_inta>;
370		};
371
372		main_udmap: dma-controller@31150000 {
373			compatible = "ti,j721e-navss-main-udmap";
374			reg =	<0x0 0x31150000 0x0 0x100>,
375				<0x0 0x34000000 0x0 0x100000>,
376				<0x0 0x35000000 0x0 0x100000>;
377			reg-names = "gcfg", "rchanrt", "tchanrt";
378			msi-parent = <&main_udmass_inta>;
379			#dma-cells = <1>;
380
381			ti,sci = <&dmsc>;
382			ti,sci-dev-id = <212>;
383			ti,ringacc = <&main_ringacc>;
384
385			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
386						<0x0f>, /* TX_HCHAN */
387						<0x10>; /* TX_UHCHAN */
388			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
389						<0x0b>, /* RX_HCHAN */
390						<0x0c>; /* RX_UHCHAN */
391			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
392		};
393
394		cpts@310d0000 {
395			compatible = "ti,j721e-cpts";
396			reg = <0x0 0x310d0000 0x0 0x400>;
397			reg-names = "cpts";
398			clocks = <&k3_clks 201 1>;
399			clock-names = "cpts";
400			interrupts-extended = <&main_navss_intr 391>;
401			interrupt-names = "cpts";
402			ti,cpts-periodic-outputs = <6>;
403			ti,cpts-ext-ts-inputs = <8>;
404		};
405	};
406
407	main_crypto: crypto@4e00000 {
408		compatible = "ti,j721e-sa2ul";
409		reg = <0x0 0x4e00000 0x0 0x1200>;
410		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
411		#address-cells = <2>;
412		#size-cells = <2>;
413		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
414
415		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
416				<&main_udmap 0x4001>;
417		dma-names = "tx", "rx1", "rx2";
418
419		rng: rng@4e10000 {
420			compatible = "inside-secure,safexcel-eip76";
421			reg = <0x0 0x4e10000 0x0 0x7d>;
422			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
423		};
424	};
425
426	main_pmx0: pinctrl@11c000 {
427		compatible = "pinctrl-single";
428		/* Proxy 0 addressing */
429		reg = <0x0 0x11c000 0x0 0x2b4>;
430		#pinctrl-cells = <1>;
431		pinctrl-single,register-width = <32>;
432		pinctrl-single,function-mask = <0xffffffff>;
433	};
434
435	serdes_wiz0: wiz@5000000 {
436		compatible = "ti,j721e-wiz-16g";
437		#address-cells = <1>;
438		#size-cells = <1>;
439		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
440		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
441		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
442		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
443		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
444		num-lanes = <2>;
445		#reset-cells = <1>;
446		ranges = <0x5000000 0x0 0x5000000 0x10000>;
447
448		wiz0_pll0_refclk: pll0-refclk {
449			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
450			#clock-cells = <0>;
451			assigned-clocks = <&wiz0_pll0_refclk>;
452			assigned-clock-parents = <&k3_clks 292 11>;
453		};
454
455		wiz0_pll1_refclk: pll1-refclk {
456			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
457			#clock-cells = <0>;
458			assigned-clocks = <&wiz0_pll1_refclk>;
459			assigned-clock-parents = <&k3_clks 292 0>;
460		};
461
462		wiz0_refclk_dig: refclk-dig {
463			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
464			#clock-cells = <0>;
465			assigned-clocks = <&wiz0_refclk_dig>;
466			assigned-clock-parents = <&k3_clks 292 11>;
467		};
468
469		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
470			clocks = <&wiz0_refclk_dig>;
471			#clock-cells = <0>;
472		};
473
474		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
475			clocks = <&wiz0_pll1_refclk>;
476			#clock-cells = <0>;
477		};
478
479		serdes0: serdes@5000000 {
480			compatible = "ti,sierra-phy-t0";
481			reg-names = "serdes";
482			reg = <0x5000000 0x10000>;
483			#address-cells = <1>;
484			#size-cells = <0>;
485			#clock-cells = <1>;
486			resets = <&serdes_wiz0 0>;
487			reset-names = "sierra_reset";
488			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
489				 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
490			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
491				      "pll0_refclk", "pll1_refclk";
492		};
493	};
494
495	serdes_wiz1: wiz@5010000 {
496		compatible = "ti,j721e-wiz-16g";
497		#address-cells = <1>;
498		#size-cells = <1>;
499		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
500		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
501		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
502		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
503		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
504		num-lanes = <2>;
505		#reset-cells = <1>;
506		ranges = <0x5010000 0x0 0x5010000 0x10000>;
507
508		wiz1_pll0_refclk: pll0-refclk {
509			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
510			#clock-cells = <0>;
511			assigned-clocks = <&wiz1_pll0_refclk>;
512			assigned-clock-parents = <&k3_clks 293 13>;
513		};
514
515		wiz1_pll1_refclk: pll1-refclk {
516			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
517			#clock-cells = <0>;
518			assigned-clocks = <&wiz1_pll1_refclk>;
519			assigned-clock-parents = <&k3_clks 293 0>;
520		};
521
522		wiz1_refclk_dig: refclk-dig {
523			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
524			#clock-cells = <0>;
525			assigned-clocks = <&wiz1_refclk_dig>;
526			assigned-clock-parents = <&k3_clks 293 13>;
527		};
528
529		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
530			clocks = <&wiz1_refclk_dig>;
531			#clock-cells = <0>;
532		};
533
534		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
535			clocks = <&wiz1_pll1_refclk>;
536			#clock-cells = <0>;
537		};
538
539		serdes1: serdes@5010000 {
540			compatible = "ti,sierra-phy-t0";
541			reg-names = "serdes";
542			reg = <0x5010000 0x10000>;
543			#address-cells = <1>;
544			#size-cells = <0>;
545			#clock-cells = <1>;
546			resets = <&serdes_wiz1 0>;
547			reset-names = "sierra_reset";
548			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
549				 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
550			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
551				      "pll0_refclk", "pll1_refclk";
552		};
553	};
554
555	serdes_wiz2: wiz@5020000 {
556		compatible = "ti,j721e-wiz-16g";
557		#address-cells = <1>;
558		#size-cells = <1>;
559		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
560		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
561		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
562		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
563		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
564		num-lanes = <2>;
565		#reset-cells = <1>;
566		ranges = <0x5020000 0x0 0x5020000 0x10000>;
567
568		wiz2_pll0_refclk: pll0-refclk {
569			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
570			#clock-cells = <0>;
571			assigned-clocks = <&wiz2_pll0_refclk>;
572			assigned-clock-parents = <&k3_clks 294 11>;
573		};
574
575		wiz2_pll1_refclk: pll1-refclk {
576			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
577			#clock-cells = <0>;
578			assigned-clocks = <&wiz2_pll1_refclk>;
579			assigned-clock-parents = <&k3_clks 294 0>;
580		};
581
582		wiz2_refclk_dig: refclk-dig {
583			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
584			#clock-cells = <0>;
585			assigned-clocks = <&wiz2_refclk_dig>;
586			assigned-clock-parents = <&k3_clks 294 11>;
587		};
588
589		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
590			clocks = <&wiz2_refclk_dig>;
591			#clock-cells = <0>;
592		};
593
594		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
595			clocks = <&wiz2_pll1_refclk>;
596			#clock-cells = <0>;
597		};
598
599		serdes2: serdes@5020000 {
600			compatible = "ti,sierra-phy-t0";
601			reg-names = "serdes";
602			reg = <0x5020000 0x10000>;
603			#address-cells = <1>;
604			#size-cells = <0>;
605			#clock-cells = <1>;
606			resets = <&serdes_wiz2 0>;
607			reset-names = "sierra_reset";
608			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
609				 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
610			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
611				      "pll0_refclk", "pll1_refclk";
612		};
613	};
614
615	serdes_wiz3: wiz@5030000 {
616		compatible = "ti,j721e-wiz-16g";
617		#address-cells = <1>;
618		#size-cells = <1>;
619		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
620		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
621		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
622		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
623		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
624		num-lanes = <2>;
625		#reset-cells = <1>;
626		ranges = <0x5030000 0x0 0x5030000 0x10000>;
627
628		wiz3_pll0_refclk: pll0-refclk {
629			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
630			#clock-cells = <0>;
631			assigned-clocks = <&wiz3_pll0_refclk>;
632			assigned-clock-parents = <&k3_clks 295 9>;
633		};
634
635		wiz3_pll1_refclk: pll1-refclk {
636			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
637			#clock-cells = <0>;
638			assigned-clocks = <&wiz3_pll1_refclk>;
639			assigned-clock-parents = <&k3_clks 295 0>;
640		};
641
642		wiz3_refclk_dig: refclk-dig {
643			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
644			#clock-cells = <0>;
645			assigned-clocks = <&wiz3_refclk_dig>;
646			assigned-clock-parents = <&k3_clks 295 9>;
647		};
648
649		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
650			clocks = <&wiz3_refclk_dig>;
651			#clock-cells = <0>;
652		};
653
654		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
655			clocks = <&wiz3_pll1_refclk>;
656			#clock-cells = <0>;
657		};
658
659		serdes3: serdes@5030000 {
660			compatible = "ti,sierra-phy-t0";
661			reg-names = "serdes";
662			reg = <0x5030000 0x10000>;
663			#address-cells = <1>;
664			#size-cells = <0>;
665			#clock-cells = <1>;
666			resets = <&serdes_wiz3 0>;
667			reset-names = "sierra_reset";
668			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
669				 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
670			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
671				      "pll0_refclk", "pll1_refclk";
672		};
673	};
674
675	pcie0_rc: pcie@2900000 {
676		compatible = "ti,j721e-pcie-host";
677		reg = <0x00 0x02900000 0x00 0x1000>,
678		      <0x00 0x02907000 0x00 0x400>,
679		      <0x00 0x0d000000 0x00 0x00800000>,
680		      <0x00 0x10000000 0x00 0x00001000>;
681		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
682		interrupt-names = "link_state";
683		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
684		device_type = "pci";
685		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
686		max-link-speed = <3>;
687		num-lanes = <2>;
688		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
689		clocks = <&k3_clks 239 1>;
690		clock-names = "fck";
691		#address-cells = <3>;
692		#size-cells = <2>;
693		bus-range = <0x0 0xff>;
694		vendor-id = <0x104c>;
695		device-id = <0xb00d>;
696		msi-map = <0x0 &gic_its 0x0 0x10000>;
697		dma-coherent;
698		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
699			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
700		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
701	};
702
703	pcie0_ep: pcie-ep@2900000 {
704		compatible = "ti,j721e-pcie-ep";
705		reg = <0x00 0x02900000 0x00 0x1000>,
706		      <0x00 0x02907000 0x00 0x400>,
707		      <0x00 0x0d000000 0x00 0x00800000>,
708		      <0x00 0x10000000 0x00 0x08000000>;
709		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
710		interrupt-names = "link_state";
711		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
712		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
713		max-link-speed = <3>;
714		num-lanes = <2>;
715		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
716		clocks = <&k3_clks 239 1>;
717		clock-names = "fck";
718		max-functions = /bits/ 8 <6>;
719		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
720		dma-coherent;
721	};
722
723	pcie1_rc: pcie@2910000 {
724		compatible = "ti,j721e-pcie-host";
725		reg = <0x00 0x02910000 0x00 0x1000>,
726		      <0x00 0x02917000 0x00 0x400>,
727		      <0x00 0x0d800000 0x00 0x00800000>,
728		      <0x00 0x18000000 0x00 0x00001000>;
729		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
730		interrupt-names = "link_state";
731		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
732		device_type = "pci";
733		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
734		max-link-speed = <3>;
735		num-lanes = <2>;
736		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
737		clocks = <&k3_clks 240 1>;
738		clock-names = "fck";
739		#address-cells = <3>;
740		#size-cells = <2>;
741		bus-range = <0x0 0xff>;
742		vendor-id = <0x104c>;
743		device-id = <0xb00d>;
744		msi-map = <0x0 &gic_its 0x10000 0x10000>;
745		dma-coherent;
746		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
747			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
748		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
749	};
750
751	pcie1_ep: pcie-ep@2910000 {
752		compatible = "ti,j721e-pcie-ep";
753		reg = <0x00 0x02910000 0x00 0x1000>,
754		      <0x00 0x02917000 0x00 0x400>,
755		      <0x00 0x0d800000 0x00 0x00800000>,
756		      <0x00 0x18000000 0x00 0x08000000>;
757		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
758		interrupt-names = "link_state";
759		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
760		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
761		max-link-speed = <3>;
762		num-lanes = <2>;
763		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
764		clocks = <&k3_clks 240 1>;
765		clock-names = "fck";
766		max-functions = /bits/ 8 <6>;
767		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
768		dma-coherent;
769	};
770
771	pcie2_rc: pcie@2920000 {
772		compatible = "ti,j721e-pcie-host";
773		reg = <0x00 0x02920000 0x00 0x1000>,
774		      <0x00 0x02927000 0x00 0x400>,
775		      <0x00 0x0e000000 0x00 0x00800000>,
776		      <0x44 0x00000000 0x00 0x00001000>;
777		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
778		interrupt-names = "link_state";
779		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
780		device_type = "pci";
781		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
782		max-link-speed = <3>;
783		num-lanes = <2>;
784		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
785		clocks = <&k3_clks 241 1>;
786		clock-names = "fck";
787		#address-cells = <3>;
788		#size-cells = <2>;
789		bus-range = <0x0 0xff>;
790		vendor-id = <0x104c>;
791		device-id = <0xb00d>;
792		msi-map = <0x0 &gic_its 0x20000 0x10000>;
793		dma-coherent;
794		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
795			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
796		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
797	};
798
799	pcie2_ep: pcie-ep@2920000 {
800		compatible = "ti,j721e-pcie-ep";
801		reg = <0x00 0x02920000 0x00 0x1000>,
802		      <0x00 0x02927000 0x00 0x400>,
803		      <0x00 0x0e000000 0x00 0x00800000>,
804		      <0x44 0x00000000 0x00 0x08000000>;
805		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
806		interrupt-names = "link_state";
807		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
808		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
809		max-link-speed = <3>;
810		num-lanes = <2>;
811		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
812		clocks = <&k3_clks 241 1>;
813		clock-names = "fck";
814		max-functions = /bits/ 8 <6>;
815		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
816		dma-coherent;
817	};
818
819	pcie3_rc: pcie@2930000 {
820		compatible = "ti,j721e-pcie-host";
821		reg = <0x00 0x02930000 0x00 0x1000>,
822		      <0x00 0x02937000 0x00 0x400>,
823		      <0x00 0x0e800000 0x00 0x00800000>,
824		      <0x44 0x10000000 0x00 0x00001000>;
825		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
826		interrupt-names = "link_state";
827		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
828		device_type = "pci";
829		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
830		max-link-speed = <3>;
831		num-lanes = <2>;
832		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
833		clocks = <&k3_clks 242 1>;
834		clock-names = "fck";
835		#address-cells = <3>;
836		#size-cells = <2>;
837		bus-range = <0x0 0xff>;
838		vendor-id = <0x104c>;
839		device-id = <0xb00d>;
840		msi-map = <0x0 &gic_its 0x30000 0x10000>;
841		dma-coherent;
842		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
843			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
844		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
845	};
846
847	pcie3_ep: pcie-ep@2930000 {
848		compatible = "ti,j721e-pcie-ep";
849		reg = <0x00 0x02930000 0x00 0x1000>,
850		      <0x00 0x02937000 0x00 0x400>,
851		      <0x00 0x0e800000 0x00 0x00800000>,
852		      <0x44 0x10000000 0x00 0x08000000>;
853		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
854		interrupt-names = "link_state";
855		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
856		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
857		max-link-speed = <3>;
858		num-lanes = <2>;
859		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
860		clocks = <&k3_clks 242 1>;
861		clock-names = "fck";
862		max-functions = /bits/ 8 <6>;
863		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
864		dma-coherent;
865		#address-cells = <2>;
866		#size-cells = <2>;
867	};
868
869	serdes_wiz4: wiz@5050000 {
870		compatible = "ti,am64-wiz-10g";
871		#address-cells = <1>;
872		#size-cells = <1>;
873		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
874		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
875		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
876		assigned-clocks = <&k3_clks 297 9>;
877		assigned-clock-parents = <&k3_clks 297 10>;
878		assigned-clock-rates = <19200000>;
879		num-lanes = <4>;
880		#reset-cells = <1>;
881		#clock-cells = <1>;
882		ranges = <0x05050000 0x00 0x05050000 0x010000>,
883			<0x0a030a00 0x00 0x0a030a00 0x40>;
884
885		serdes4: serdes@5050000 {
886			/*
887			 * Note: we also map DPTX PHY registers as the Torrent
888			 * needs to manage those.
889			 */
890			compatible = "ti,j721e-serdes-10g";
891			reg = <0x05050000 0x010000>,
892			      <0x0a030a00 0x40>; /* DPTX PHY */
893			reg-names = "torrent_phy", "dptx_phy";
894
895			resets = <&serdes_wiz4 0>;
896			reset-names = "torrent_reset";
897			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
898			clock-names = "refclk";
899			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
900					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
901					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
902			assigned-clock-parents = <&k3_clks 297 9>,
903						 <&k3_clks 297 9>,
904						 <&k3_clks 297 9>;
905			#address-cells = <1>;
906			#size-cells = <0>;
907		};
908	};
909
910	main_uart0: serial@2800000 {
911		compatible = "ti,j721e-uart", "ti,am654-uart";
912		reg = <0x00 0x02800000 0x00 0x100>;
913		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
914		clock-frequency = <48000000>;
915		current-speed = <115200>;
916		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
917		clocks = <&k3_clks 146 0>;
918		clock-names = "fclk";
919		status = "disabled";
920	};
921
922	main_uart1: serial@2810000 {
923		compatible = "ti,j721e-uart", "ti,am654-uart";
924		reg = <0x00 0x02810000 0x00 0x100>;
925		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
926		clock-frequency = <48000000>;
927		current-speed = <115200>;
928		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
929		clocks = <&k3_clks 278 0>;
930		clock-names = "fclk";
931		status = "disabled";
932	};
933
934	main_uart2: serial@2820000 {
935		compatible = "ti,j721e-uart", "ti,am654-uart";
936		reg = <0x00 0x02820000 0x00 0x100>;
937		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
938		clock-frequency = <48000000>;
939		current-speed = <115200>;
940		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
941		clocks = <&k3_clks 279 0>;
942		clock-names = "fclk";
943		status = "disabled";
944	};
945
946	main_uart3: serial@2830000 {
947		compatible = "ti,j721e-uart", "ti,am654-uart";
948		reg = <0x00 0x02830000 0x00 0x100>;
949		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
950		clock-frequency = <48000000>;
951		current-speed = <115200>;
952		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
953		clocks = <&k3_clks 280 0>;
954		clock-names = "fclk";
955		status = "disabled";
956	};
957
958	main_uart4: serial@2840000 {
959		compatible = "ti,j721e-uart", "ti,am654-uart";
960		reg = <0x00 0x02840000 0x00 0x100>;
961		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
962		clock-frequency = <48000000>;
963		current-speed = <115200>;
964		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
965		clocks = <&k3_clks 281 0>;
966		clock-names = "fclk";
967		status = "disabled";
968	};
969
970	main_uart5: serial@2850000 {
971		compatible = "ti,j721e-uart", "ti,am654-uart";
972		reg = <0x00 0x02850000 0x00 0x100>;
973		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
974		clock-frequency = <48000000>;
975		current-speed = <115200>;
976		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
977		clocks = <&k3_clks 282 0>;
978		clock-names = "fclk";
979		status = "disabled";
980	};
981
982	main_uart6: serial@2860000 {
983		compatible = "ti,j721e-uart", "ti,am654-uart";
984		reg = <0x00 0x02860000 0x00 0x100>;
985		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
986		clock-frequency = <48000000>;
987		current-speed = <115200>;
988		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
989		clocks = <&k3_clks 283 0>;
990		clock-names = "fclk";
991		status = "disabled";
992	};
993
994	main_uart7: serial@2870000 {
995		compatible = "ti,j721e-uart", "ti,am654-uart";
996		reg = <0x00 0x02870000 0x00 0x100>;
997		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
998		clock-frequency = <48000000>;
999		current-speed = <115200>;
1000		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1001		clocks = <&k3_clks 284 0>;
1002		clock-names = "fclk";
1003		status = "disabled";
1004	};
1005
1006	main_uart8: serial@2880000 {
1007		compatible = "ti,j721e-uart", "ti,am654-uart";
1008		reg = <0x00 0x02880000 0x00 0x100>;
1009		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
1010		clock-frequency = <48000000>;
1011		current-speed = <115200>;
1012		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1013		clocks = <&k3_clks 285 0>;
1014		clock-names = "fclk";
1015		status = "disabled";
1016	};
1017
1018	main_uart9: serial@2890000 {
1019		compatible = "ti,j721e-uart", "ti,am654-uart";
1020		reg = <0x00 0x02890000 0x00 0x100>;
1021		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
1022		clock-frequency = <48000000>;
1023		current-speed = <115200>;
1024		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1025		clocks = <&k3_clks 286 0>;
1026		clock-names = "fclk";
1027		status = "disabled";
1028	};
1029
1030	main_gpio0: gpio@600000 {
1031		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1032		reg = <0x0 0x00600000 0x0 0x100>;
1033		gpio-controller;
1034		#gpio-cells = <2>;
1035		interrupt-parent = <&main_gpio_intr>;
1036		interrupts = <256>, <257>, <258>, <259>,
1037			     <260>, <261>, <262>, <263>;
1038		interrupt-controller;
1039		#interrupt-cells = <2>;
1040		ti,ngpio = <128>;
1041		ti,davinci-gpio-unbanked = <0>;
1042		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1043		clocks = <&k3_clks 105 0>;
1044		clock-names = "gpio";
1045	};
1046
1047	main_gpio1: gpio@601000 {
1048		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1049		reg = <0x0 0x00601000 0x0 0x100>;
1050		gpio-controller;
1051		#gpio-cells = <2>;
1052		interrupt-parent = <&main_gpio_intr>;
1053		interrupts = <288>, <289>, <290>;
1054		interrupt-controller;
1055		#interrupt-cells = <2>;
1056		ti,ngpio = <36>;
1057		ti,davinci-gpio-unbanked = <0>;
1058		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1059		clocks = <&k3_clks 106 0>;
1060		clock-names = "gpio";
1061	};
1062
1063	main_gpio2: gpio@610000 {
1064		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1065		reg = <0x0 0x00610000 0x0 0x100>;
1066		gpio-controller;
1067		#gpio-cells = <2>;
1068		interrupt-parent = <&main_gpio_intr>;
1069		interrupts = <264>, <265>, <266>, <267>,
1070			     <268>, <269>, <270>, <271>;
1071		interrupt-controller;
1072		#interrupt-cells = <2>;
1073		ti,ngpio = <128>;
1074		ti,davinci-gpio-unbanked = <0>;
1075		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1076		clocks = <&k3_clks 107 0>;
1077		clock-names = "gpio";
1078	};
1079
1080	main_gpio3: gpio@611000 {
1081		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1082		reg = <0x0 0x00611000 0x0 0x100>;
1083		gpio-controller;
1084		#gpio-cells = <2>;
1085		interrupt-parent = <&main_gpio_intr>;
1086		interrupts = <292>, <293>, <294>;
1087		interrupt-controller;
1088		#interrupt-cells = <2>;
1089		ti,ngpio = <36>;
1090		ti,davinci-gpio-unbanked = <0>;
1091		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1092		clocks = <&k3_clks 108 0>;
1093		clock-names = "gpio";
1094	};
1095
1096	main_gpio4: gpio@620000 {
1097		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1098		reg = <0x0 0x00620000 0x0 0x100>;
1099		gpio-controller;
1100		#gpio-cells = <2>;
1101		interrupt-parent = <&main_gpio_intr>;
1102		interrupts = <272>, <273>, <274>, <275>,
1103			     <276>, <277>, <278>, <279>;
1104		interrupt-controller;
1105		#interrupt-cells = <2>;
1106		ti,ngpio = <128>;
1107		ti,davinci-gpio-unbanked = <0>;
1108		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1109		clocks = <&k3_clks 109 0>;
1110		clock-names = "gpio";
1111	};
1112
1113	main_gpio5: gpio@621000 {
1114		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1115		reg = <0x0 0x00621000 0x0 0x100>;
1116		gpio-controller;
1117		#gpio-cells = <2>;
1118		interrupt-parent = <&main_gpio_intr>;
1119		interrupts = <296>, <297>, <298>;
1120		interrupt-controller;
1121		#interrupt-cells = <2>;
1122		ti,ngpio = <36>;
1123		ti,davinci-gpio-unbanked = <0>;
1124		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1125		clocks = <&k3_clks 110 0>;
1126		clock-names = "gpio";
1127	};
1128
1129	main_gpio6: gpio@630000 {
1130		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1131		reg = <0x0 0x00630000 0x0 0x100>;
1132		gpio-controller;
1133		#gpio-cells = <2>;
1134		interrupt-parent = <&main_gpio_intr>;
1135		interrupts = <280>, <281>, <282>, <283>,
1136			     <284>, <285>, <286>, <287>;
1137		interrupt-controller;
1138		#interrupt-cells = <2>;
1139		ti,ngpio = <128>;
1140		ti,davinci-gpio-unbanked = <0>;
1141		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1142		clocks = <&k3_clks 111 0>;
1143		clock-names = "gpio";
1144	};
1145
1146	main_gpio7: gpio@631000 {
1147		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1148		reg = <0x0 0x00631000 0x0 0x100>;
1149		gpio-controller;
1150		#gpio-cells = <2>;
1151		interrupt-parent = <&main_gpio_intr>;
1152		interrupts = <300>, <301>, <302>;
1153		interrupt-controller;
1154		#interrupt-cells = <2>;
1155		ti,ngpio = <36>;
1156		ti,davinci-gpio-unbanked = <0>;
1157		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1158		clocks = <&k3_clks 112 0>;
1159		clock-names = "gpio";
1160	};
1161
1162	main_sdhci0: mmc@4f80000 {
1163		compatible = "ti,j721e-sdhci-8bit";
1164		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1165		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1166		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1167		clock-names = "clk_ahb", "clk_xin";
1168		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1169		assigned-clocks = <&k3_clks 91 1>;
1170		assigned-clock-parents = <&k3_clks 91 2>;
1171		bus-width = <8>;
1172		mmc-hs200-1_8v;
1173		mmc-ddr-1_8v;
1174		ti,otap-del-sel-legacy = <0xf>;
1175		ti,otap-del-sel-mmc-hs = <0xf>;
1176		ti,otap-del-sel-ddr52 = <0x5>;
1177		ti,otap-del-sel-hs200 = <0x6>;
1178		ti,otap-del-sel-hs400 = <0x0>;
1179		ti,itap-del-sel-legacy = <0x10>;
1180		ti,itap-del-sel-mmc-hs = <0xa>;
1181		ti,itap-del-sel-ddr52 = <0x3>;
1182		ti,trm-icp = <0x8>;
1183		ti,strobe-sel = <0x77>;
1184		dma-coherent;
1185	};
1186
1187	main_sdhci1: mmc@4fb0000 {
1188		compatible = "ti,j721e-sdhci-4bit";
1189		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1190		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1191		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1192		clock-names = "clk_ahb", "clk_xin";
1193		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1194		assigned-clocks = <&k3_clks 92 0>;
1195		assigned-clock-parents = <&k3_clks 92 1>;
1196		ti,otap-del-sel-legacy = <0x0>;
1197		ti,otap-del-sel-sd-hs = <0xf>;
1198		ti,otap-del-sel-sdr12 = <0xf>;
1199		ti,otap-del-sel-sdr25 = <0xf>;
1200		ti,otap-del-sel-sdr50 = <0xc>;
1201		ti,otap-del-sel-ddr50 = <0xc>;
1202		ti,itap-del-sel-legacy = <0x0>;
1203		ti,itap-del-sel-sd-hs = <0x0>;
1204		ti,itap-del-sel-sdr12 = <0x0>;
1205		ti,itap-del-sel-sdr25 = <0x0>;
1206		ti,itap-del-sel-ddr50 = <0x2>;
1207		ti,trm-icp = <0x8>;
1208		ti,clkbuf-sel = <0x7>;
1209		dma-coherent;
1210		sdhci-caps-mask = <0x2 0x0>;
1211	};
1212
1213	main_sdhci2: mmc@4f98000 {
1214		compatible = "ti,j721e-sdhci-4bit";
1215		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1216		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1217		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1218		clock-names = "clk_ahb", "clk_xin";
1219		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1220		assigned-clocks = <&k3_clks 93 0>;
1221		assigned-clock-parents = <&k3_clks 93 1>;
1222		ti,otap-del-sel-legacy = <0x0>;
1223		ti,otap-del-sel-sd-hs = <0xf>;
1224		ti,otap-del-sel-sdr12 = <0xf>;
1225		ti,otap-del-sel-sdr25 = <0xf>;
1226		ti,otap-del-sel-sdr50 = <0xc>;
1227		ti,otap-del-sel-ddr50 = <0xc>;
1228		ti,itap-del-sel-legacy = <0x0>;
1229		ti,itap-del-sel-sd-hs = <0x0>;
1230		ti,itap-del-sel-sdr12 = <0x0>;
1231		ti,itap-del-sel-sdr25 = <0x0>;
1232		ti,itap-del-sel-ddr50 = <0x2>;
1233		ti,trm-icp = <0x8>;
1234		ti,clkbuf-sel = <0x7>;
1235		dma-coherent;
1236		sdhci-caps-mask = <0x2 0x0>;
1237	};
1238
1239	usbss0: cdns-usb@4104000 {
1240		compatible = "ti,j721e-usb";
1241		reg = <0x00 0x4104000 0x00 0x100>;
1242		dma-coherent;
1243		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1244		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1245		clock-names = "ref", "lpm";
1246		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
1247		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1248		#address-cells = <2>;
1249		#size-cells = <2>;
1250		ranges;
1251
1252		usb0: usb@6000000 {
1253			compatible = "cdns,usb3";
1254			reg = <0x00 0x6000000 0x00 0x10000>,
1255			      <0x00 0x6010000 0x00 0x10000>,
1256			      <0x00 0x6020000 0x00 0x10000>;
1257			reg-names = "otg", "xhci", "dev";
1258			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1259				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
1260				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1261			interrupt-names = "host",
1262					  "peripheral",
1263					  "otg";
1264			maximum-speed = "super-speed";
1265			dr_mode = "otg";
1266		};
1267	};
1268
1269	usbss1: cdns-usb@4114000 {
1270		compatible = "ti,j721e-usb";
1271		reg = <0x00 0x4114000 0x00 0x100>;
1272		dma-coherent;
1273		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1274		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1275		clock-names = "ref", "lpm";
1276		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
1277		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1278		#address-cells = <2>;
1279		#size-cells = <2>;
1280		ranges;
1281
1282		usb1: usb@6400000 {
1283			compatible = "cdns,usb3";
1284			reg = <0x00 0x6400000 0x00 0x10000>,
1285			      <0x00 0x6410000 0x00 0x10000>,
1286			      <0x00 0x6420000 0x00 0x10000>;
1287			reg-names = "otg", "xhci", "dev";
1288			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1289				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
1290				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1291			interrupt-names = "host",
1292					  "peripheral",
1293					  "otg";
1294			maximum-speed = "super-speed";
1295			dr_mode = "otg";
1296		};
1297	};
1298
1299	main_i2c0: i2c@2000000 {
1300		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1301		reg = <0x0 0x2000000 0x0 0x100>;
1302		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1303		#address-cells = <1>;
1304		#size-cells = <0>;
1305		clock-names = "fck";
1306		clocks = <&k3_clks 187 0>;
1307		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1308		status = "disabled";
1309	};
1310
1311	main_i2c1: i2c@2010000 {
1312		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1313		reg = <0x0 0x2010000 0x0 0x100>;
1314		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1315		#address-cells = <1>;
1316		#size-cells = <0>;
1317		clock-names = "fck";
1318		clocks = <&k3_clks 188 0>;
1319		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1320		status = "disabled";
1321	};
1322
1323	main_i2c2: i2c@2020000 {
1324		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1325		reg = <0x0 0x2020000 0x0 0x100>;
1326		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1327		#address-cells = <1>;
1328		#size-cells = <0>;
1329		clock-names = "fck";
1330		clocks = <&k3_clks 189 0>;
1331		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1332		status = "disabled";
1333	};
1334
1335	main_i2c3: i2c@2030000 {
1336		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1337		reg = <0x0 0x2030000 0x0 0x100>;
1338		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1339		#address-cells = <1>;
1340		#size-cells = <0>;
1341		clock-names = "fck";
1342		clocks = <&k3_clks 190 0>;
1343		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1344		status = "disabled";
1345	};
1346
1347	main_i2c4: i2c@2040000 {
1348		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1349		reg = <0x0 0x2040000 0x0 0x100>;
1350		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1351		#address-cells = <1>;
1352		#size-cells = <0>;
1353		clock-names = "fck";
1354		clocks = <&k3_clks 191 0>;
1355		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1356		status = "disabled";
1357	};
1358
1359	main_i2c5: i2c@2050000 {
1360		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1361		reg = <0x0 0x2050000 0x0 0x100>;
1362		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1363		#address-cells = <1>;
1364		#size-cells = <0>;
1365		clock-names = "fck";
1366		clocks = <&k3_clks 192 0>;
1367		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1368		status = "disabled";
1369	};
1370
1371	main_i2c6: i2c@2060000 {
1372		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1373		reg = <0x0 0x2060000 0x0 0x100>;
1374		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1375		#address-cells = <1>;
1376		#size-cells = <0>;
1377		clock-names = "fck";
1378		clocks = <&k3_clks 193 0>;
1379		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1380		status = "disabled";
1381	};
1382
1383	ufs_wrapper: ufs-wrapper@4e80000 {
1384		compatible = "ti,j721e-ufs";
1385		reg = <0x0 0x4e80000 0x0 0x100>;
1386		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1387		clocks = <&k3_clks 277 1>;
1388		assigned-clocks = <&k3_clks 277 1>;
1389		assigned-clock-parents = <&k3_clks 277 4>;
1390		ranges;
1391		#address-cells = <2>;
1392		#size-cells = <2>;
1393
1394		ufs@4e84000 {
1395			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1396			reg = <0x0 0x4e84000 0x0 0x10000>;
1397			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1398			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1399			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1400			clock-names = "core_clk", "phy_clk", "ref_clk";
1401			dma-coherent;
1402		};
1403	};
1404
1405	mhdp: dp-bridge@a000000 {
1406		compatible = "ti,j721e-mhdp8546";
1407		/*
1408		 * Note: we do not map DPTX PHY area, as that is handled by
1409		 * the PHY driver.
1410		 */
1411		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1412		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
1413		reg-names = "mhdptx", "j721e-intg";
1414
1415		clocks = <&k3_clks 151 36>;
1416
1417		interrupt-parent = <&gic500>;
1418		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
1419
1420		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1421
1422		dp0_ports: ports {
1423			#address-cells = <1>;
1424			#size-cells = <0>;
1425
1426			port@0 {
1427			    reg = <0>;
1428			};
1429
1430			port@4 {
1431			    reg = <4>;
1432			};
1433		};
1434	};
1435
1436	dss: dss@4a00000 {
1437		compatible = "ti,j721e-dss";
1438		reg =
1439			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
1440			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1441			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1442			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1443
1444			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1445			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1446			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1447			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1448
1449			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1450			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1451			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1452			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1453
1454			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1455			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1456			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1457			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1458			<0x00 0x04af0000 0x00 0x10000>; /* wb */
1459
1460		reg-names = "common_m", "common_s0",
1461			"common_s1", "common_s2",
1462			"vidl1", "vidl2","vid1","vid2",
1463			"ovr1", "ovr2", "ovr3", "ovr4",
1464			"vp1", "vp2", "vp3", "vp4",
1465			"wb";
1466
1467		clocks =	<&k3_clks 152 0>,
1468				<&k3_clks 152 1>,
1469				<&k3_clks 152 4>,
1470				<&k3_clks 152 9>,
1471				<&k3_clks 152 13>;
1472		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1473
1474		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1475
1476		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1477			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1478			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1479			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1480		interrupt-names = "common_m",
1481				  "common_s0",
1482				  "common_s1",
1483				  "common_s2";
1484
1485		dss_ports: ports {
1486		};
1487	};
1488
1489	mcasp0: mcasp@2b00000 {
1490		compatible = "ti,am33xx-mcasp-audio";
1491		reg = <0x0 0x02b00000 0x0 0x2000>,
1492			<0x0 0x02b08000 0x0 0x1000>;
1493		reg-names = "mpu","dat";
1494		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1495				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1496		interrupt-names = "tx", "rx";
1497
1498		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1499		dma-names = "tx", "rx";
1500
1501		clocks = <&k3_clks 174 1>;
1502		clock-names = "fck";
1503		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1504		status = "disabled";
1505	};
1506
1507	mcasp1: mcasp@2b10000 {
1508		compatible = "ti,am33xx-mcasp-audio";
1509		reg = <0x0 0x02b10000 0x0 0x2000>,
1510			<0x0 0x02b18000 0x0 0x1000>;
1511		reg-names = "mpu","dat";
1512		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1513				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1514		interrupt-names = "tx", "rx";
1515
1516		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1517		dma-names = "tx", "rx";
1518
1519		clocks = <&k3_clks 175 1>;
1520		clock-names = "fck";
1521		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1522		status = "disabled";
1523	};
1524
1525	mcasp2: mcasp@2b20000 {
1526		compatible = "ti,am33xx-mcasp-audio";
1527		reg = <0x0 0x02b20000 0x0 0x2000>,
1528			<0x0 0x02b28000 0x0 0x1000>;
1529		reg-names = "mpu","dat";
1530		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1531				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1532		interrupt-names = "tx", "rx";
1533
1534		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1535		dma-names = "tx", "rx";
1536
1537		clocks = <&k3_clks 176 1>;
1538		clock-names = "fck";
1539		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1540		status = "disabled";
1541	};
1542
1543	mcasp3: mcasp@2b30000 {
1544		compatible = "ti,am33xx-mcasp-audio";
1545		reg = <0x0 0x02b30000 0x0 0x2000>,
1546			<0x0 0x02b38000 0x0 0x1000>;
1547		reg-names = "mpu","dat";
1548		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1549				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1550		interrupt-names = "tx", "rx";
1551
1552		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1553		dma-names = "tx", "rx";
1554
1555		clocks = <&k3_clks 177 1>;
1556		clock-names = "fck";
1557		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1558		status = "disabled";
1559	};
1560
1561	mcasp4: mcasp@2b40000 {
1562		compatible = "ti,am33xx-mcasp-audio";
1563		reg = <0x0 0x02b40000 0x0 0x2000>,
1564			<0x0 0x02b48000 0x0 0x1000>;
1565		reg-names = "mpu","dat";
1566		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1567				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1568		interrupt-names = "tx", "rx";
1569
1570		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1571		dma-names = "tx", "rx";
1572
1573		clocks = <&k3_clks 178 1>;
1574		clock-names = "fck";
1575		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1576		status = "disabled";
1577	};
1578
1579	mcasp5: mcasp@2b50000 {
1580		compatible = "ti,am33xx-mcasp-audio";
1581		reg = <0x0 0x02b50000 0x0 0x2000>,
1582			<0x0 0x02b58000 0x0 0x1000>;
1583		reg-names = "mpu","dat";
1584		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1585				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1586		interrupt-names = "tx", "rx";
1587
1588		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1589		dma-names = "tx", "rx";
1590
1591		clocks = <&k3_clks 179 1>;
1592		clock-names = "fck";
1593		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1594		status = "disabled";
1595	};
1596
1597	mcasp6: mcasp@2b60000 {
1598		compatible = "ti,am33xx-mcasp-audio";
1599		reg = <0x0 0x02b60000 0x0 0x2000>,
1600			<0x0 0x02b68000 0x0 0x1000>;
1601		reg-names = "mpu","dat";
1602		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1603				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1604		interrupt-names = "tx", "rx";
1605
1606		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1607		dma-names = "tx", "rx";
1608
1609		clocks = <&k3_clks 180 1>;
1610		clock-names = "fck";
1611		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1612		status = "disabled";
1613	};
1614
1615	mcasp7: mcasp@2b70000 {
1616		compatible = "ti,am33xx-mcasp-audio";
1617		reg = <0x0 0x02b70000 0x0 0x2000>,
1618			<0x0 0x02b78000 0x0 0x1000>;
1619		reg-names = "mpu","dat";
1620		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1621				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1622		interrupt-names = "tx", "rx";
1623
1624		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1625		dma-names = "tx", "rx";
1626
1627		clocks = <&k3_clks 181 1>;
1628		clock-names = "fck";
1629		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1630		status = "disabled";
1631	};
1632
1633	mcasp8: mcasp@2b80000 {
1634		compatible = "ti,am33xx-mcasp-audio";
1635		reg = <0x0 0x02b80000 0x0 0x2000>,
1636			<0x0 0x02b88000 0x0 0x1000>;
1637		reg-names = "mpu","dat";
1638		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1639				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1640		interrupt-names = "tx", "rx";
1641
1642		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1643		dma-names = "tx", "rx";
1644
1645		clocks = <&k3_clks 182 1>;
1646		clock-names = "fck";
1647		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1648		status = "disabled";
1649	};
1650
1651	mcasp9: mcasp@2b90000 {
1652		compatible = "ti,am33xx-mcasp-audio";
1653		reg = <0x0 0x02b90000 0x0 0x2000>,
1654			<0x0 0x02b98000 0x0 0x1000>;
1655		reg-names = "mpu","dat";
1656		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1657				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1658		interrupt-names = "tx", "rx";
1659
1660		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1661		dma-names = "tx", "rx";
1662
1663		clocks = <&k3_clks 183 1>;
1664		clock-names = "fck";
1665		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1666		status = "disabled";
1667	};
1668
1669	mcasp10: mcasp@2ba0000 {
1670		compatible = "ti,am33xx-mcasp-audio";
1671		reg = <0x0 0x02ba0000 0x0 0x2000>,
1672			<0x0 0x02ba8000 0x0 0x1000>;
1673		reg-names = "mpu","dat";
1674		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1675				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1676		interrupt-names = "tx", "rx";
1677
1678		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1679		dma-names = "tx", "rx";
1680
1681		clocks = <&k3_clks 184 1>;
1682		clock-names = "fck";
1683		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1684		status = "disabled";
1685	};
1686
1687	mcasp11: mcasp@2bb0000 {
1688		compatible = "ti,am33xx-mcasp-audio";
1689		reg = <0x0 0x02bb0000 0x0 0x2000>,
1690			<0x0 0x02bb8000 0x0 0x1000>;
1691		reg-names = "mpu","dat";
1692		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1693				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1694		interrupt-names = "tx", "rx";
1695
1696		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1697		dma-names = "tx", "rx";
1698
1699		clocks = <&k3_clks 185 1>;
1700		clock-names = "fck";
1701		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1702		status = "disabled";
1703	};
1704
1705	watchdog0: watchdog@2200000 {
1706		compatible = "ti,j7-rti-wdt";
1707		reg = <0x0 0x2200000 0x0 0x100>;
1708		clocks = <&k3_clks 252 1>;
1709		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1710		assigned-clocks = <&k3_clks 252 1>;
1711		assigned-clock-parents = <&k3_clks 252 5>;
1712	};
1713
1714	watchdog1: watchdog@2210000 {
1715		compatible = "ti,j7-rti-wdt";
1716		reg = <0x0 0x2210000 0x0 0x100>;
1717		clocks = <&k3_clks 253 1>;
1718		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1719		assigned-clocks = <&k3_clks 253 1>;
1720		assigned-clock-parents = <&k3_clks 253 5>;
1721	};
1722
1723	main_r5fss0: r5fss@5c00000 {
1724		compatible = "ti,j721e-r5fss";
1725		ti,cluster-mode = <1>;
1726		#address-cells = <1>;
1727		#size-cells = <1>;
1728		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1729			 <0x5d00000 0x00 0x5d00000 0x20000>;
1730		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1731
1732		main_r5fss0_core0: r5f@5c00000 {
1733			compatible = "ti,j721e-r5f";
1734			reg = <0x5c00000 0x00008000>,
1735			      <0x5c10000 0x00008000>;
1736			reg-names = "atcm", "btcm";
1737			ti,sci = <&dmsc>;
1738			ti,sci-dev-id = <245>;
1739			ti,sci-proc-ids = <0x06 0xff>;
1740			resets = <&k3_reset 245 1>;
1741			firmware-name = "j7-main-r5f0_0-fw";
1742			ti,atcm-enable = <1>;
1743			ti,btcm-enable = <1>;
1744			ti,loczrama = <1>;
1745		};
1746
1747		main_r5fss0_core1: r5f@5d00000 {
1748			compatible = "ti,j721e-r5f";
1749			reg = <0x5d00000 0x00008000>,
1750			      <0x5d10000 0x00008000>;
1751			reg-names = "atcm", "btcm";
1752			ti,sci = <&dmsc>;
1753			ti,sci-dev-id = <246>;
1754			ti,sci-proc-ids = <0x07 0xff>;
1755			resets = <&k3_reset 246 1>;
1756			firmware-name = "j7-main-r5f0_1-fw";
1757			ti,atcm-enable = <1>;
1758			ti,btcm-enable = <1>;
1759			ti,loczrama = <1>;
1760		};
1761	};
1762
1763	main_r5fss1: r5fss@5e00000 {
1764		compatible = "ti,j721e-r5fss";
1765		ti,cluster-mode = <1>;
1766		#address-cells = <1>;
1767		#size-cells = <1>;
1768		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1769			 <0x5f00000 0x00 0x5f00000 0x20000>;
1770		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1771
1772		main_r5fss1_core0: r5f@5e00000 {
1773			compatible = "ti,j721e-r5f";
1774			reg = <0x5e00000 0x00008000>,
1775			      <0x5e10000 0x00008000>;
1776			reg-names = "atcm", "btcm";
1777			ti,sci = <&dmsc>;
1778			ti,sci-dev-id = <247>;
1779			ti,sci-proc-ids = <0x08 0xff>;
1780			resets = <&k3_reset 247 1>;
1781			firmware-name = "j7-main-r5f1_0-fw";
1782			ti,atcm-enable = <1>;
1783			ti,btcm-enable = <1>;
1784			ti,loczrama = <1>;
1785		};
1786
1787		main_r5fss1_core1: r5f@5f00000 {
1788			compatible = "ti,j721e-r5f";
1789			reg = <0x5f00000 0x00008000>,
1790			      <0x5f10000 0x00008000>;
1791			reg-names = "atcm", "btcm";
1792			ti,sci = <&dmsc>;
1793			ti,sci-dev-id = <248>;
1794			ti,sci-proc-ids = <0x09 0xff>;
1795			resets = <&k3_reset 248 1>;
1796			firmware-name = "j7-main-r5f1_1-fw";
1797			ti,atcm-enable = <1>;
1798			ti,btcm-enable = <1>;
1799			ti,loczrama = <1>;
1800		};
1801	};
1802
1803	c66_0: dsp@4d80800000 {
1804		compatible = "ti,j721e-c66-dsp";
1805		reg = <0x4d 0x80800000 0x00 0x00048000>,
1806		      <0x4d 0x80e00000 0x00 0x00008000>,
1807		      <0x4d 0x80f00000 0x00 0x00008000>;
1808		reg-names = "l2sram", "l1pram", "l1dram";
1809		ti,sci = <&dmsc>;
1810		ti,sci-dev-id = <142>;
1811		ti,sci-proc-ids = <0x03 0xff>;
1812		resets = <&k3_reset 142 1>;
1813		firmware-name = "j7-c66_0-fw";
1814	};
1815
1816	c66_1: dsp@4d81800000 {
1817		compatible = "ti,j721e-c66-dsp";
1818		reg = <0x4d 0x81800000 0x00 0x00048000>,
1819		      <0x4d 0x81e00000 0x00 0x00008000>,
1820		      <0x4d 0x81f00000 0x00 0x00008000>;
1821		reg-names = "l2sram", "l1pram", "l1dram";
1822		ti,sci = <&dmsc>;
1823		ti,sci-dev-id = <143>;
1824		ti,sci-proc-ids = <0x04 0xff>;
1825		resets = <&k3_reset 143 1>;
1826		firmware-name = "j7-c66_1-fw";
1827	};
1828
1829	c71_0: dsp@64800000 {
1830		compatible = "ti,j721e-c71-dsp";
1831		reg = <0x00 0x64800000 0x00 0x00080000>,
1832		      <0x00 0x64e00000 0x00 0x0000c000>;
1833		reg-names = "l2sram", "l1dram";
1834		ti,sci = <&dmsc>;
1835		ti,sci-dev-id = <15>;
1836		ti,sci-proc-ids = <0x30 0xff>;
1837		resets = <&k3_reset 15 1>;
1838		firmware-name = "j7-c71_0-fw";
1839	};
1840
1841	icssg0: icssg@b000000 {
1842		compatible = "ti,j721e-icssg";
1843		reg = <0x00 0xb000000 0x00 0x80000>;
1844		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1845		#address-cells = <1>;
1846		#size-cells = <1>;
1847		ranges = <0x0 0x00 0x0b000000 0x100000>;
1848
1849		icssg0_mem: memories@0 {
1850			reg = <0x0 0x2000>,
1851			      <0x2000 0x2000>,
1852			      <0x10000 0x10000>;
1853			reg-names = "dram0", "dram1",
1854				    "shrdram2";
1855		};
1856
1857		icssg0_cfg: cfg@26000 {
1858			compatible = "ti,pruss-cfg", "syscon";
1859			reg = <0x26000 0x200>;
1860			#address-cells = <1>;
1861			#size-cells = <1>;
1862			ranges = <0x0 0x26000 0x2000>;
1863
1864			clocks {
1865				#address-cells = <1>;
1866				#size-cells = <0>;
1867
1868				icssg0_coreclk_mux: coreclk-mux@3c {
1869					reg = <0x3c>;
1870					#clock-cells = <0>;
1871					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
1872						 <&k3_clks 119 1>;  /* icssg0_iclk */
1873					assigned-clocks = <&icssg0_coreclk_mux>;
1874					assigned-clock-parents = <&k3_clks 119 1>;
1875				};
1876
1877				icssg0_iepclk_mux: iepclk-mux@30 {
1878					reg = <0x30>;
1879					#clock-cells = <0>;
1880					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
1881						 <&icssg0_coreclk_mux>;	/* core_clk */
1882					assigned-clocks = <&icssg0_iepclk_mux>;
1883					assigned-clock-parents = <&icssg0_coreclk_mux>;
1884				};
1885			};
1886		};
1887
1888		icssg0_mii_rt: mii-rt@32000 {
1889			compatible = "ti,pruss-mii", "syscon";
1890			reg = <0x32000 0x100>;
1891		};
1892
1893		icssg0_mii_g_rt: mii-g-rt@33000 {
1894			compatible = "ti,pruss-mii-g", "syscon";
1895			reg = <0x33000 0x1000>;
1896		};
1897
1898		icssg0_intc: interrupt-controller@20000 {
1899			compatible = "ti,icssg-intc";
1900			reg = <0x20000 0x2000>;
1901			interrupt-controller;
1902			#interrupt-cells = <3>;
1903			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1904				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1905				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1906				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1907				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1908				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1909				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1910				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1911			interrupt-names = "host_intr0", "host_intr1",
1912					  "host_intr2", "host_intr3",
1913					  "host_intr4", "host_intr5",
1914					  "host_intr6", "host_intr7";
1915		};
1916
1917		pru0_0: pru@34000 {
1918			compatible = "ti,j721e-pru";
1919			reg = <0x34000 0x3000>,
1920			      <0x22000 0x100>,
1921			      <0x22400 0x100>;
1922			reg-names = "iram", "control", "debug";
1923			firmware-name = "j7-pru0_0-fw";
1924		};
1925
1926		rtu0_0: rtu@4000 {
1927			compatible = "ti,j721e-rtu";
1928			reg = <0x4000 0x2000>,
1929			      <0x23000 0x100>,
1930			      <0x23400 0x100>;
1931			reg-names = "iram", "control", "debug";
1932			firmware-name = "j7-rtu0_0-fw";
1933		};
1934
1935		tx_pru0_0: txpru@a000 {
1936			compatible = "ti,j721e-tx-pru";
1937			reg = <0xa000 0x1800>,
1938			      <0x25000 0x100>,
1939			      <0x25400 0x100>;
1940			reg-names = "iram", "control", "debug";
1941			firmware-name = "j7-txpru0_0-fw";
1942		};
1943
1944		pru0_1: pru@38000 {
1945			compatible = "ti,j721e-pru";
1946			reg = <0x38000 0x3000>,
1947			      <0x24000 0x100>,
1948			      <0x24400 0x100>;
1949			reg-names = "iram", "control", "debug";
1950			firmware-name = "j7-pru0_1-fw";
1951		};
1952
1953		rtu0_1: rtu@6000 {
1954			compatible = "ti,j721e-rtu";
1955			reg = <0x6000 0x2000>,
1956			      <0x23800 0x100>,
1957			      <0x23c00 0x100>;
1958			reg-names = "iram", "control", "debug";
1959			firmware-name = "j7-rtu0_1-fw";
1960		};
1961
1962		tx_pru0_1: txpru@c000 {
1963			compatible = "ti,j721e-tx-pru";
1964			reg = <0xc000 0x1800>,
1965			      <0x25800 0x100>,
1966			      <0x25c00 0x100>;
1967			reg-names = "iram", "control", "debug";
1968			firmware-name = "j7-txpru0_1-fw";
1969		};
1970
1971		icssg0_mdio: mdio@32400 {
1972			compatible = "ti,davinci_mdio";
1973			reg = <0x32400 0x100>;
1974			clocks = <&k3_clks 119 1>;
1975			clock-names = "fck";
1976			#address-cells = <1>;
1977			#size-cells = <0>;
1978			bus_freq = <1000000>;
1979		};
1980	};
1981
1982	icssg1: icssg@b100000 {
1983		compatible = "ti,j721e-icssg";
1984		reg = <0x00 0xb100000 0x00 0x80000>;
1985		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1986		#address-cells = <1>;
1987		#size-cells = <1>;
1988		ranges = <0x0 0x00 0x0b100000 0x100000>;
1989
1990		icssg1_mem: memories@b100000 {
1991			reg = <0x0 0x2000>,
1992			      <0x2000 0x2000>,
1993			      <0x10000 0x10000>;
1994			reg-names = "dram0", "dram1",
1995				    "shrdram2";
1996		};
1997
1998		icssg1_cfg: cfg@26000 {
1999			compatible = "ti,pruss-cfg", "syscon";
2000			reg = <0x26000 0x200>;
2001			#address-cells = <1>;
2002			#size-cells = <1>;
2003			ranges = <0x0 0x26000 0x2000>;
2004
2005			clocks {
2006				#address-cells = <1>;
2007				#size-cells = <0>;
2008
2009				icssg1_coreclk_mux: coreclk-mux@3c {
2010					reg = <0x3c>;
2011					#clock-cells = <0>;
2012					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
2013						 <&k3_clks 120 4>;  /* icssg1_iclk */
2014					assigned-clocks = <&icssg1_coreclk_mux>;
2015					assigned-clock-parents = <&k3_clks 120 4>;
2016				};
2017
2018				icssg1_iepclk_mux: iepclk-mux@30 {
2019					reg = <0x30>;
2020					#clock-cells = <0>;
2021					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
2022						 <&icssg1_coreclk_mux>;	/* core_clk */
2023					assigned-clocks = <&icssg1_iepclk_mux>;
2024					assigned-clock-parents = <&icssg1_coreclk_mux>;
2025				};
2026			};
2027		};
2028
2029		icssg1_mii_rt: mii-rt@32000 {
2030			compatible = "ti,pruss-mii", "syscon";
2031			reg = <0x32000 0x100>;
2032		};
2033
2034		icssg1_mii_g_rt: mii-g-rt@33000 {
2035			compatible = "ti,pruss-mii-g", "syscon";
2036			reg = <0x33000 0x1000>;
2037		};
2038
2039		icssg1_intc: interrupt-controller@20000 {
2040			compatible = "ti,icssg-intc";
2041			reg = <0x20000 0x2000>;
2042			interrupt-controller;
2043			#interrupt-cells = <3>;
2044			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2045				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2046				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2047				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
2048				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2049				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2050				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2051				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2052			interrupt-names = "host_intr0", "host_intr1",
2053					  "host_intr2", "host_intr3",
2054					  "host_intr4", "host_intr5",
2055					  "host_intr6", "host_intr7";
2056		};
2057
2058		pru1_0: pru@34000 {
2059			compatible = "ti,j721e-pru";
2060			reg = <0x34000 0x4000>,
2061			      <0x22000 0x100>,
2062			      <0x22400 0x100>;
2063			reg-names = "iram", "control", "debug";
2064			firmware-name = "j7-pru1_0-fw";
2065		};
2066
2067		rtu1_0: rtu@4000 {
2068			compatible = "ti,j721e-rtu";
2069			reg = <0x4000 0x2000>,
2070			      <0x23000 0x100>,
2071			      <0x23400 0x100>;
2072			reg-names = "iram", "control", "debug";
2073			firmware-name = "j7-rtu1_0-fw";
2074		};
2075
2076		tx_pru1_0: txpru@a000 {
2077			compatible = "ti,j721e-tx-pru";
2078			reg = <0xa000 0x1800>,
2079			      <0x25000 0x100>,
2080			      <0x25400 0x100>;
2081			reg-names = "iram", "control", "debug";
2082			firmware-name = "j7-txpru1_0-fw";
2083		};
2084
2085		pru1_1: pru@38000 {
2086			compatible = "ti,j721e-pru";
2087			reg = <0x38000 0x4000>,
2088			      <0x24000 0x100>,
2089			      <0x24400 0x100>;
2090			reg-names = "iram", "control", "debug";
2091			firmware-name = "j7-pru1_1-fw";
2092		};
2093
2094		rtu1_1: rtu@6000 {
2095			compatible = "ti,j721e-rtu";
2096			reg = <0x6000 0x2000>,
2097			      <0x23800 0x100>,
2098			      <0x23c00 0x100>;
2099			reg-names = "iram", "control", "debug";
2100			firmware-name = "j7-rtu1_1-fw";
2101		};
2102
2103		tx_pru1_1: txpru@c000 {
2104			compatible = "ti,j721e-tx-pru";
2105			reg = <0xc000 0x1800>,
2106			      <0x25800 0x100>,
2107			      <0x25c00 0x100>;
2108			reg-names = "iram", "control", "debug";
2109			firmware-name = "j7-txpru1_1-fw";
2110		};
2111
2112		icssg1_mdio: mdio@32400 {
2113			compatible = "ti,davinci_mdio";
2114			reg = <0x32400 0x100>;
2115			clocks = <&k3_clks 120 4>;
2116			clock-names = "fck";
2117			#address-cells = <1>;
2118			#size-cells = <0>;
2119			bus_freq = <1000000>;
2120		};
2121	};
2122
2123	main_mcan0: can@2701000 {
2124		compatible = "bosch,m_can";
2125		reg = <0x00 0x02701000 0x00 0x200>,
2126		      <0x00 0x02708000 0x00 0x8000>;
2127		reg-names = "m_can", "message_ram";
2128		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2129		clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2130		clock-names = "hclk", "cclk";
2131		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2132			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2133		interrupt-names = "int0", "int1";
2134		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2135		status = "disabled";
2136	};
2137
2138	main_mcan1: can@2711000 {
2139		compatible = "bosch,m_can";
2140		reg = <0x00 0x02711000 0x00 0x200>,
2141		      <0x00 0x02718000 0x00 0x8000>;
2142		reg-names = "m_can", "message_ram";
2143		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2144		clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2145		clock-names = "hclk", "cclk";
2146		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2147			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
2148		interrupt-names = "int0", "int1";
2149		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2150		status = "disabled";
2151	};
2152
2153	main_mcan2: can@2721000 {
2154		compatible = "bosch,m_can";
2155		reg = <0x00 0x02721000 0x00 0x200>,
2156		      <0x00 0x02728000 0x00 0x8000>;
2157		reg-names = "m_can", "message_ram";
2158		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2159		clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2160		clock-names = "hclk", "cclk";
2161		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2162			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2163		interrupt-names = "int0", "int1";
2164		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2165		status = "disabled";
2166	};
2167
2168	main_mcan3: can@2731000 {
2169		compatible = "bosch,m_can";
2170		reg = <0x00 0x02731000 0x00 0x200>,
2171		      <0x00 0x02738000 0x00 0x8000>;
2172		reg-names = "m_can", "message_ram";
2173		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2174		clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2175		clock-names = "hclk", "cclk";
2176		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2177			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2178		interrupt-names = "int0", "int1";
2179		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2180		status = "disabled";
2181	};
2182
2183	main_mcan4: can@2741000 {
2184		compatible = "bosch,m_can";
2185		reg = <0x00 0x02741000 0x00 0x200>,
2186		      <0x00 0x02748000 0x00 0x8000>;
2187		reg-names = "m_can", "message_ram";
2188		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2189		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2190		clock-names = "hclk", "cclk";
2191		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2192			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2193		interrupt-names = "int0", "int1";
2194		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2195		status = "disabled";
2196	};
2197
2198	main_mcan5: can@2751000 {
2199		compatible = "bosch,m_can";
2200		reg = <0x00 0x02751000 0x00 0x200>,
2201		      <0x00 0x02758000 0x00 0x8000>;
2202		reg-names = "m_can", "message_ram";
2203		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2204		clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2205		clock-names = "hclk", "cclk";
2206		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2207			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2208		interrupt-names = "int0", "int1";
2209		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2210		status = "disabled";
2211	};
2212
2213	main_mcan6: can@2761000 {
2214		compatible = "bosch,m_can";
2215		reg = <0x00 0x02761000 0x00 0x200>,
2216		      <0x00 0x02768000 0x00 0x8000>;
2217		reg-names = "m_can", "message_ram";
2218		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2219		clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2220		clock-names = "hclk", "cclk";
2221		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2222			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2223		interrupt-names = "int0", "int1";
2224		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2225		status = "disabled";
2226	};
2227
2228	main_mcan7: can@2771000 {
2229		compatible = "bosch,m_can";
2230		reg = <0x00 0x02771000 0x00 0x200>,
2231		      <0x00 0x02778000 0x00 0x8000>;
2232		reg-names = "m_can", "message_ram";
2233		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2234		clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2235		clock-names = "hclk", "cclk";
2236		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2237			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2238		interrupt-names = "int0", "int1";
2239		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2240		status = "disabled";
2241	};
2242
2243	main_mcan8: can@2781000 {
2244		compatible = "bosch,m_can";
2245		reg = <0x00 0x02781000 0x00 0x200>,
2246		      <0x00 0x02788000 0x00 0x8000>;
2247		reg-names = "m_can", "message_ram";
2248		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2249		clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2250		clock-names = "hclk", "cclk";
2251		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2252			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
2253		interrupt-names = "int0", "int1";
2254		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2255		status = "disabled";
2256	};
2257
2258	main_mcan9: can@2791000 {
2259		compatible = "bosch,m_can";
2260		reg = <0x00 0x02791000 0x00 0x200>,
2261		      <0x00 0x02798000 0x00 0x8000>;
2262		reg-names = "m_can", "message_ram";
2263		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2264		clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2265		clock-names = "hclk", "cclk";
2266		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
2267			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2268		interrupt-names = "int0", "int1";
2269		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2270		status = "disabled";
2271	};
2272
2273	main_mcan10: can@27a1000 {
2274		compatible = "bosch,m_can";
2275		reg = <0x00 0x027a1000 0x00 0x200>,
2276		      <0x00 0x027a8000 0x00 0x8000>;
2277		reg-names = "m_can", "message_ram";
2278		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2279		clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2280		clock-names = "hclk", "cclk";
2281		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
2282			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2283		interrupt-names = "int0", "int1";
2284		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2285		status = "disabled";
2286	};
2287
2288	main_mcan11: can@27b1000 {
2289		compatible = "bosch,m_can";
2290		reg = <0x00 0x027b1000 0x00 0x200>,
2291		      <0x00 0x027b8000 0x00 0x8000>;
2292		reg-names = "m_can", "message_ram";
2293		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2294		clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2295		clock-names = "hclk", "cclk";
2296		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
2297			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2298		interrupt-names = "int0", "int1";
2299		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2300		status = "disabled";
2301	};
2302
2303	main_mcan12: can@27c1000 {
2304		compatible = "bosch,m_can";
2305		reg = <0x00 0x027c1000 0x00 0x200>,
2306		      <0x00 0x027c8000 0x00 0x8000>;
2307		reg-names = "m_can", "message_ram";
2308		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2309		clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2310		clock-names = "hclk", "cclk";
2311		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2312			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
2313		interrupt-names = "int0", "int1";
2314		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2315		status = "disabled";
2316	};
2317
2318	main_mcan13: can@27d1000 {
2319		compatible = "bosch,m_can";
2320		reg = <0x00 0x027d1000 0x00 0x200>,
2321		      <0x00 0x027d8000 0x00 0x8000>;
2322		reg-names = "m_can", "message_ram";
2323		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2324		clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2325		clock-names = "hclk", "cclk";
2326		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2327			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
2328		interrupt-names = "int0", "int1";
2329		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2330		status = "disabled";
2331	};
2332};
2333