1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x0 0x70000000 0x0 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x70000000 0x800000>; 15 16 atf-sram@0 { 17 reg = <0x0 0x20000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 30 31 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: gic-its@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 smmu0: smmu@36600000 { 44 compatible = "arm,smmu-v3"; 45 reg = <0x0 0x36600000 0x0 0x100000>; 46 interrupt-parent = <&gic500>; 47 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 48 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 49 interrupt-names = "eventq", "gerror"; 50 #iommu-cells = <1>; 51 }; 52 53 main_gpio_intr: interrupt-controller0 { 54 compatible = "ti,sci-intr"; 55 ti,intr-trigger-type = <1>; 56 interrupt-controller; 57 interrupt-parent = <&gic500>; 58 #interrupt-cells = <2>; 59 ti,sci = <&dmsc>; 60 ti,sci-dst-id = <14>; 61 ti,sci-rm-range-girq = <0x1>; 62 }; 63 64 cbass_main_navss: interconnect0 { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 main_navss_intr: interrupt-controller1 { 71 compatible = "ti,sci-intr"; 72 ti,intr-trigger-type = <4>; 73 interrupt-controller; 74 interrupt-parent = <&gic500>; 75 #interrupt-cells = <2>; 76 ti,sci = <&dmsc>; 77 ti,sci-dst-id = <14>; 78 ti,sci-rm-range-girq = <0>, <2>; 79 }; 80 81 main_udmass_inta: interrupt-controller@33d00000 { 82 compatible = "ti,sci-inta"; 83 reg = <0x0 0x33d00000 0x0 0x100000>; 84 interrupt-controller; 85 interrupt-parent = <&main_navss_intr>; 86 msi-controller; 87 ti,sci = <&dmsc>; 88 ti,sci-dev-id = <209>; 89 ti,sci-rm-range-vint = <0xa>; 90 ti,sci-rm-range-global-event = <0xd>; 91 }; 92 93 hwspinlock: spinlock@30e00000 { 94 compatible = "ti,am654-hwspinlock"; 95 reg = <0x00 0x30e00000 0x00 0x1000>; 96 #hwlock-cells = <1>; 97 }; 98 99 mailbox0_cluster0: mailbox@31f80000 { 100 compatible = "ti,am654-mailbox"; 101 reg = <0x00 0x31f80000 0x00 0x200>; 102 #mbox-cells = <1>; 103 ti,mbox-num-users = <4>; 104 ti,mbox-num-fifos = <16>; 105 interrupt-parent = <&main_navss_intr>; 106 }; 107 108 mailbox0_cluster1: mailbox@31f81000 { 109 compatible = "ti,am654-mailbox"; 110 reg = <0x00 0x31f81000 0x00 0x200>; 111 #mbox-cells = <1>; 112 ti,mbox-num-users = <4>; 113 ti,mbox-num-fifos = <16>; 114 interrupt-parent = <&main_navss_intr>; 115 }; 116 117 mailbox0_cluster2: mailbox@31f82000 { 118 compatible = "ti,am654-mailbox"; 119 reg = <0x00 0x31f82000 0x00 0x200>; 120 #mbox-cells = <1>; 121 ti,mbox-num-users = <4>; 122 ti,mbox-num-fifos = <16>; 123 interrupt-parent = <&main_navss_intr>; 124 }; 125 126 mailbox0_cluster3: mailbox@31f83000 { 127 compatible = "ti,am654-mailbox"; 128 reg = <0x00 0x31f83000 0x00 0x200>; 129 #mbox-cells = <1>; 130 ti,mbox-num-users = <4>; 131 ti,mbox-num-fifos = <16>; 132 interrupt-parent = <&main_navss_intr>; 133 }; 134 135 mailbox0_cluster4: mailbox@31f84000 { 136 compatible = "ti,am654-mailbox"; 137 reg = <0x00 0x31f84000 0x00 0x200>; 138 #mbox-cells = <1>; 139 ti,mbox-num-users = <4>; 140 ti,mbox-num-fifos = <16>; 141 interrupt-parent = <&main_navss_intr>; 142 }; 143 144 mailbox0_cluster5: mailbox@31f85000 { 145 compatible = "ti,am654-mailbox"; 146 reg = <0x00 0x31f85000 0x00 0x200>; 147 #mbox-cells = <1>; 148 ti,mbox-num-users = <4>; 149 ti,mbox-num-fifos = <16>; 150 interrupt-parent = <&main_navss_intr>; 151 }; 152 153 mailbox0_cluster6: mailbox@31f86000 { 154 compatible = "ti,am654-mailbox"; 155 reg = <0x00 0x31f86000 0x00 0x200>; 156 #mbox-cells = <1>; 157 ti,mbox-num-users = <4>; 158 ti,mbox-num-fifos = <16>; 159 interrupt-parent = <&main_navss_intr>; 160 }; 161 162 mailbox0_cluster7: mailbox@31f87000 { 163 compatible = "ti,am654-mailbox"; 164 reg = <0x00 0x31f87000 0x00 0x200>; 165 #mbox-cells = <1>; 166 ti,mbox-num-users = <4>; 167 ti,mbox-num-fifos = <16>; 168 interrupt-parent = <&main_navss_intr>; 169 }; 170 171 mailbox0_cluster8: mailbox@31f88000 { 172 compatible = "ti,am654-mailbox"; 173 reg = <0x00 0x31f88000 0x00 0x200>; 174 #mbox-cells = <1>; 175 ti,mbox-num-users = <4>; 176 ti,mbox-num-fifos = <16>; 177 interrupt-parent = <&main_navss_intr>; 178 }; 179 180 mailbox0_cluster9: mailbox@31f89000 { 181 compatible = "ti,am654-mailbox"; 182 reg = <0x00 0x31f89000 0x00 0x200>; 183 #mbox-cells = <1>; 184 ti,mbox-num-users = <4>; 185 ti,mbox-num-fifos = <16>; 186 interrupt-parent = <&main_navss_intr>; 187 }; 188 189 mailbox0_cluster10: mailbox@31f8a000 { 190 compatible = "ti,am654-mailbox"; 191 reg = <0x00 0x31f8a000 0x00 0x200>; 192 #mbox-cells = <1>; 193 ti,mbox-num-users = <4>; 194 ti,mbox-num-fifos = <16>; 195 interrupt-parent = <&main_navss_intr>; 196 }; 197 198 mailbox0_cluster11: mailbox@31f8b000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f8b000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 }; 206 }; 207 208 secure_proxy_main: mailbox@32c00000 { 209 compatible = "ti,am654-secure-proxy"; 210 #mbox-cells = <1>; 211 reg-names = "target_data", "rt", "scfg"; 212 reg = <0x00 0x32c00000 0x00 0x100000>, 213 <0x00 0x32400000 0x00 0x100000>, 214 <0x00 0x32800000 0x00 0x100000>; 215 interrupt-names = "rx_011"; 216 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 217 }; 218 219 main_pmx0: pinmux@11c000 { 220 compatible = "pinctrl-single"; 221 /* Proxy 0 addressing */ 222 reg = <0x0 0x11c000 0x0 0x2b4>; 223 #pinctrl-cells = <1>; 224 pinctrl-single,register-width = <32>; 225 pinctrl-single,function-mask = <0xffffffff>; 226 }; 227 228 main_uart0: serial@2800000 { 229 compatible = "ti,j721e-uart", "ti,am654-uart"; 230 reg = <0x00 0x02800000 0x00 0x100>; 231 reg-shift = <2>; 232 reg-io-width = <4>; 233 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 234 clock-frequency = <48000000>; 235 current-speed = <115200>; 236 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 237 clocks = <&k3_clks 146 0>; 238 clock-names = "fclk"; 239 }; 240 241 main_uart1: serial@2810000 { 242 compatible = "ti,j721e-uart", "ti,am654-uart"; 243 reg = <0x00 0x02810000 0x00 0x100>; 244 reg-shift = <2>; 245 reg-io-width = <4>; 246 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 247 clock-frequency = <48000000>; 248 current-speed = <115200>; 249 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 250 clocks = <&k3_clks 278 0>; 251 clock-names = "fclk"; 252 }; 253 254 main_uart2: serial@2820000 { 255 compatible = "ti,j721e-uart", "ti,am654-uart"; 256 reg = <0x00 0x02820000 0x00 0x100>; 257 reg-shift = <2>; 258 reg-io-width = <4>; 259 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <48000000>; 261 current-speed = <115200>; 262 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 279 0>; 264 clock-names = "fclk"; 265 }; 266 267 main_uart3: serial@2830000 { 268 compatible = "ti,j721e-uart", "ti,am654-uart"; 269 reg = <0x00 0x02830000 0x00 0x100>; 270 reg-shift = <2>; 271 reg-io-width = <4>; 272 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 273 clock-frequency = <48000000>; 274 current-speed = <115200>; 275 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 276 clocks = <&k3_clks 280 0>; 277 clock-names = "fclk"; 278 }; 279 280 main_uart4: serial@2840000 { 281 compatible = "ti,j721e-uart", "ti,am654-uart"; 282 reg = <0x00 0x02840000 0x00 0x100>; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 286 clock-frequency = <48000000>; 287 current-speed = <115200>; 288 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 289 clocks = <&k3_clks 281 0>; 290 clock-names = "fclk"; 291 }; 292 293 main_uart5: serial@2850000 { 294 compatible = "ti,j721e-uart", "ti,am654-uart"; 295 reg = <0x00 0x02850000 0x00 0x100>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 299 clock-frequency = <48000000>; 300 current-speed = <115200>; 301 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 302 clocks = <&k3_clks 282 0>; 303 clock-names = "fclk"; 304 }; 305 306 main_uart6: serial@2860000 { 307 compatible = "ti,j721e-uart", "ti,am654-uart"; 308 reg = <0x00 0x02860000 0x00 0x100>; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 312 clock-frequency = <48000000>; 313 current-speed = <115200>; 314 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 315 clocks = <&k3_clks 283 0>; 316 clock-names = "fclk"; 317 }; 318 319 main_uart7: serial@2870000 { 320 compatible = "ti,j721e-uart", "ti,am654-uart"; 321 reg = <0x00 0x02870000 0x00 0x100>; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 325 clock-frequency = <48000000>; 326 current-speed = <115200>; 327 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 328 clocks = <&k3_clks 284 0>; 329 clock-names = "fclk"; 330 }; 331 332 main_uart8: serial@2880000 { 333 compatible = "ti,j721e-uart", "ti,am654-uart"; 334 reg = <0x00 0x02880000 0x00 0x100>; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 338 clock-frequency = <48000000>; 339 current-speed = <115200>; 340 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 341 clocks = <&k3_clks 285 0>; 342 clock-names = "fclk"; 343 }; 344 345 main_uart9: serial@2890000 { 346 compatible = "ti,j721e-uart", "ti,am654-uart"; 347 reg = <0x00 0x02890000 0x00 0x100>; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 351 clock-frequency = <48000000>; 352 current-speed = <115200>; 353 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 354 clocks = <&k3_clks 286 0>; 355 clock-names = "fclk"; 356 }; 357 358 main_gpio0: gpio@600000 { 359 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 360 reg = <0x0 0x00600000 0x0 0x100>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-parent = <&main_gpio_intr>; 364 interrupts = <105 0>, <105 1>, <105 2>, <105 3>, 365 <105 4>, <105 5>, <105 6>, <105 7>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 ti,ngpio = <128>; 369 ti,davinci-gpio-unbanked = <0>; 370 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 371 clocks = <&k3_clks 105 0>; 372 clock-names = "gpio"; 373 }; 374 375 main_gpio1: gpio@601000 { 376 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 377 reg = <0x0 0x00601000 0x0 0x100>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 interrupt-parent = <&main_gpio_intr>; 381 interrupts = <106 0>, <106 1>, <106 2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 ti,ngpio = <36>; 385 ti,davinci-gpio-unbanked = <0>; 386 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 387 clocks = <&k3_clks 106 0>; 388 clock-names = "gpio"; 389 }; 390 391 main_gpio2: gpio@610000 { 392 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 393 reg = <0x0 0x00610000 0x0 0x100>; 394 gpio-controller; 395 #gpio-cells = <2>; 396 interrupt-parent = <&main_gpio_intr>; 397 interrupts = <107 0>, <107 1>, <107 2>, <107 3>, 398 <107 4>, <107 5>, <107 6>, <107 7>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 ti,ngpio = <128>; 402 ti,davinci-gpio-unbanked = <0>; 403 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 404 clocks = <&k3_clks 107 0>; 405 clock-names = "gpio"; 406 }; 407 408 main_gpio3: gpio@611000 { 409 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 410 reg = <0x0 0x00611000 0x0 0x100>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 interrupt-parent = <&main_gpio_intr>; 414 interrupts = <108 0>, <108 1>, <108 2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 ti,ngpio = <36>; 418 ti,davinci-gpio-unbanked = <0>; 419 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 108 0>; 421 clock-names = "gpio"; 422 }; 423 424 main_gpio4: gpio@620000 { 425 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 426 reg = <0x0 0x00620000 0x0 0x100>; 427 gpio-controller; 428 #gpio-cells = <2>; 429 interrupt-parent = <&main_gpio_intr>; 430 interrupts = <109 0>, <109 1>, <109 2>, <109 3>, 431 <109 4>, <109 5>, <109 6>, <109 7>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 ti,ngpio = <128>; 435 ti,davinci-gpio-unbanked = <0>; 436 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 437 clocks = <&k3_clks 109 0>; 438 clock-names = "gpio"; 439 }; 440 441 main_gpio5: gpio@621000 { 442 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 443 reg = <0x0 0x00621000 0x0 0x100>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 interrupt-parent = <&main_gpio_intr>; 447 interrupts = <110 0>, <110 1>, <110 2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 ti,ngpio = <36>; 451 ti,davinci-gpio-unbanked = <0>; 452 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 453 clocks = <&k3_clks 110 0>; 454 clock-names = "gpio"; 455 }; 456 457 main_gpio6: gpio@630000 { 458 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 459 reg = <0x0 0x00630000 0x0 0x100>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 interrupt-parent = <&main_gpio_intr>; 463 interrupts = <111 0>, <111 1>, <111 2>, <111 3>, 464 <111 4>, <111 5>, <111 6>, <111 7>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 ti,ngpio = <128>; 468 ti,davinci-gpio-unbanked = <0>; 469 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 470 clocks = <&k3_clks 111 0>; 471 clock-names = "gpio"; 472 }; 473 474 main_gpio7: gpio@631000 { 475 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 476 reg = <0x0 0x00631000 0x0 0x100>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-parent = <&main_gpio_intr>; 480 interrupts = <112 0>, <112 1>, <112 2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 ti,ngpio = <36>; 484 ti,davinci-gpio-unbanked = <0>; 485 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 486 clocks = <&k3_clks 112 0>; 487 clock-names = "gpio"; 488 }; 489 490 main_sdhci0: sdhci@4f80000 { 491 compatible = "ti,j721e-sdhci-8bit"; 492 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 493 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 494 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 495 clock-names = "clk_xin", "clk_ahb"; 496 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 497 assigned-clocks = <&k3_clks 91 1>; 498 assigned-clock-parents = <&k3_clks 91 2>; 499 bus-width = <8>; 500 mmc-hs400-1_8v; 501 mmc-ddr-1_8v; 502 ti,otap-del-sel = <0x2>; 503 ti,trm-icp = <0x8>; 504 ti,strobe-sel = <0x77>; 505 dma-coherent; 506 }; 507 508 main_sdhci1: sdhci@4fb0000 { 509 compatible = "ti,j721e-sdhci-4bit"; 510 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 511 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 512 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 513 clock-names = "clk_xin", "clk_ahb"; 514 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 515 assigned-clocks = <&k3_clks 92 0>; 516 assigned-clock-parents = <&k3_clks 92 1>; 517 ti,otap-del-sel = <0x2>; 518 ti,trm-icp = <0x8>; 519 ti,clkbuf-sel = <0x7>; 520 dma-coherent; 521 no-1-8-v; 522 }; 523 524 main_sdhci2: sdhci@4f98000 { 525 compatible = "ti,j721e-sdhci-4bit"; 526 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 527 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 528 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 529 clock-names = "clk_xin", "clk_ahb"; 530 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 531 assigned-clocks = <&k3_clks 93 0>; 532 assigned-clock-parents = <&k3_clks 93 1>; 533 ti,otap-del-sel = <0x2>; 534 ti,trm-icp = <0x8>; 535 ti,clkbuf-sel = <0x7>; 536 dma-coherent; 537 no-1-8-v; 538 }; 539 540 usbss0: cdns_usb@4104000 { 541 compatible = "ti,j721e-usb"; 542 reg = <0x00 0x4104000 0x00 0x100>; 543 dma-coherent; 544 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 545 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 546 clock-names = "ref", "lpm"; 547 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 548 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 549 #address-cells = <2>; 550 #size-cells = <2>; 551 ranges; 552 553 usb0: usb@6000000 { 554 compatible = "cdns,usb3"; 555 reg = <0x00 0x6000000 0x00 0x10000>, 556 <0x00 0x6010000 0x00 0x10000>, 557 <0x00 0x6020000 0x00 0x10000>; 558 reg-names = "otg", "xhci", "dev"; 559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 560 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 561 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 562 interrupt-names = "host", 563 "peripheral", 564 "otg"; 565 maximum-speed = "super-speed"; 566 dr_mode = "otg"; 567 }; 568 }; 569 570 usbss1: cdns_usb@4114000 { 571 compatible = "ti,j721e-usb"; 572 reg = <0x00 0x4114000 0x00 0x100>; 573 dma-coherent; 574 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 575 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 576 clock-names = "ref", "lpm"; 577 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 578 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 579 #address-cells = <2>; 580 #size-cells = <2>; 581 ranges; 582 583 usb1: usb@6400000 { 584 compatible = "cdns,usb3"; 585 reg = <0x00 0x6400000 0x00 0x10000>, 586 <0x00 0x6410000 0x00 0x10000>, 587 <0x00 0x6420000 0x00 0x10000>; 588 reg-names = "otg", "xhci", "dev"; 589 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 590 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 591 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 592 interrupt-names = "host", 593 "peripheral", 594 "otg"; 595 maximum-speed = "super-speed"; 596 dr_mode = "otg"; 597 }; 598 }; 599}; 600