1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/net/ti-dp83867.h> 12 13/ { 14 chosen { 15 stdout-path = "serial2:115200n8"; 16 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 17 }; 18 19 gpio_keys: gpio-keys { 20 compatible = "gpio-keys"; 21 autorepeat; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; 24 25 sw10: sw10 { 26 label = "GPIO Key USER1"; 27 linux,code = <BTN_0>; 28 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 29 }; 30 31 sw11: sw11 { 32 label = "GPIO Key USER2"; 33 linux,code = <BTN_1>; 34 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 35 }; 36 }; 37 38 evm_12v0: fixedregulator-evm12v0 { 39 /* main supply */ 40 compatible = "regulator-fixed"; 41 regulator-name = "evm_12v0"; 42 regulator-min-microvolt = <12000000>; 43 regulator-max-microvolt = <12000000>; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 vsys_3v3: fixedregulator-vsys3v3 { 49 /* Output of LMS140 */ 50 compatible = "regulator-fixed"; 51 regulator-name = "vsys_3v3"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&evm_12v0>; 55 regulator-always-on; 56 regulator-boot-on; 57 }; 58 59 vsys_5v0: fixedregulator-vsys5v0 { 60 /* Output of LM5140 */ 61 compatible = "regulator-fixed"; 62 regulator-name = "vsys_5v0"; 63 regulator-min-microvolt = <5000000>; 64 regulator-max-microvolt = <5000000>; 65 vin-supply = <&evm_12v0>; 66 regulator-always-on; 67 regulator-boot-on; 68 }; 69 70 sound0: sound@0 { 71 compatible = "ti,j721e-cpb-audio"; 72 model = "j721e-cpb"; 73 74 ti,cpb-mcasp = <&mcasp10>; 75 ti,cpb-codec = <&pcm3168a_1>; 76 77 clocks = <&k3_clks 184 1>, 78 <&k3_clks 184 2>, <&k3_clks 184 4>, 79 <&k3_clks 157 371>, 80 <&k3_clks 157 400>, <&k3_clks 157 401>; 81 clock-names = "cpb-mcasp-auxclk", 82 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 83 "cpb-codec-scki", 84 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 85 }; 86}; 87 88&main_pmx0 { 89 sw10_button_pins_default: sw10-button-pins-default { 90 pinctrl-single,pins = < 91 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 92 >; 93 }; 94 95 main_mmc1_pins_default: main-mmc1-pins-default { 96 pinctrl-single,pins = < 97 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 98 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 99 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 100 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 101 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 102 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 103 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 104 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 105 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 106 >; 107 }; 108 109 main_usbss0_pins_default: main-usbss0-pins-default { 110 pinctrl-single,pins = < 111 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 112 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 113 >; 114 }; 115 116 main_usbss1_pins_default: main-usbss1-pins-default { 117 pinctrl-single,pins = < 118 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 119 >; 120 }; 121 122 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { 123 pinctrl-single,pins = < 124 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 125 >; 126 }; 127 128 main_i2c0_pins_default: main-i2c0-pins-default { 129 pinctrl-single,pins = < 130 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 131 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 132 >; 133 }; 134 135 main_i2c1_pins_default: main-i2c1-pins-default { 136 pinctrl-single,pins = < 137 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 138 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 139 >; 140 }; 141 142 main_i2c3_pins_default: main-i2c3-pins-default { 143 pinctrl-single,pins = < 144 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 145 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 146 >; 147 }; 148 149 main_i2c6_pins_default: main-i2c6-pins-default { 150 pinctrl-single,pins = < 151 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 152 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 153 >; 154 }; 155 156 mcasp10_pins_default: mcasp10-pins-default { 157 pinctrl-single,pins = < 158 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 159 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 160 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 161 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 162 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 163 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 164 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 165 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 166 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 167 >; 168 }; 169 170 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { 171 pinctrl-single,pins = < 172 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 173 >; 174 }; 175}; 176 177&wkup_pmx0 { 178 sw11_button_pins_default: sw11-button-pins-default { 179 pinctrl-single,pins = < 180 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 181 >; 182 }; 183 184 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 185 pinctrl-single,pins = < 186 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 187 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 188 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 189 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 190 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 191 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 192 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 193 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 194 >; 195 }; 196 197 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 198 pinctrl-single,pins = < 199 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 200 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 201 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 202 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 203 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 204 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 205 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 206 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 207 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 208 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 209 J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ 210 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 211 >; 212 }; 213 214 mcu_mdio_pins_default: mcu-mdio1-pins-default { 215 pinctrl-single,pins = < 216 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 217 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 218 >; 219 }; 220}; 221 222&wkup_uart0 { 223 /* Wakeup UART is used by System firmware */ 224 status = "disabled"; 225}; 226 227&main_uart0 { 228 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 229}; 230 231&main_uart3 { 232 /* UART not brought out */ 233 status = "disabled"; 234}; 235 236&main_uart5 { 237 /* UART not brought out */ 238 status = "disabled"; 239}; 240 241&main_uart6 { 242 /* UART not brought out */ 243 status = "disabled"; 244}; 245 246&main_uart7 { 247 /* UART not brought out */ 248 status = "disabled"; 249}; 250 251&main_uart8 { 252 /* UART not brought out */ 253 status = "disabled"; 254}; 255 256&main_uart9 { 257 /* UART not brought out */ 258 status = "disabled"; 259}; 260 261&main_gpio2 { 262 status = "disabled"; 263}; 264 265&main_gpio3 { 266 status = "disabled"; 267}; 268 269&main_gpio4 { 270 status = "disabled"; 271}; 272 273&main_gpio5 { 274 status = "disabled"; 275}; 276 277&main_gpio6 { 278 status = "disabled"; 279}; 280 281&main_gpio7 { 282 status = "disabled"; 283}; 284 285&wkup_gpio1 { 286 status = "disabled"; 287}; 288 289&main_sdhci0 { 290 /* eMMC */ 291 non-removable; 292 ti,driver-strength-ohm = <50>; 293 disable-wp; 294}; 295 296&main_sdhci1 { 297 /* SD/MMC */ 298 pinctrl-names = "default"; 299 pinctrl-0 = <&main_mmc1_pins_default>; 300 ti,driver-strength-ohm = <50>; 301 disable-wp; 302}; 303 304&main_sdhci2 { 305 /* Unused */ 306 status = "disabled"; 307}; 308 309&usb_serdes_mux { 310 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 311}; 312 313&serdes_ln_ctrl { 314 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 315 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 316 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 317 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 318 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 319 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 320}; 321 322&serdes_wiz3 { 323 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 324 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 325}; 326 327&serdes3 { 328 serdes3_usb_link: link@0 { 329 reg = <0>; 330 cdns,num-lanes = <2>; 331 #phy-cells = <0>; 332 cdns,phy-type = <PHY_TYPE_USB3>; 333 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 334 }; 335}; 336 337&usbss0 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&main_usbss0_pins_default>; 340 ti,vbus-divider; 341}; 342 343&usb0 { 344 dr_mode = "otg"; 345 maximum-speed = "super-speed"; 346 phys = <&serdes3_usb_link>; 347 phy-names = "cdns3,usb3-phy"; 348}; 349 350&usbss1 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&main_usbss1_pins_default>; 353 ti,usb2-only; 354}; 355 356&usb1 { 357 dr_mode = "host"; 358 maximum-speed = "high-speed"; 359}; 360 361&ospi1 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 364 365 flash@0{ 366 compatible = "jedec,spi-nor"; 367 reg = <0x0>; 368 spi-tx-bus-width = <1>; 369 spi-rx-bus-width = <4>; 370 spi-max-frequency = <40000000>; 371 cdns,tshsl-ns = <60>; 372 cdns,tsd2d-ns = <60>; 373 cdns,tchsh-ns = <60>; 374 cdns,tslch-ns = <60>; 375 cdns,read-delay = <2>; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 }; 379}; 380 381&tscadc0 { 382 adc { 383 ti,adc-channels = <0 1 2 3 4 5 6 7>; 384 }; 385}; 386 387&tscadc1 { 388 adc { 389 ti,adc-channels = <0 1 2 3 4 5 6 7>; 390 }; 391}; 392 393&main_i2c0 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&main_i2c0_pins_default>; 396 clock-frequency = <400000>; 397 398 exp1: gpio@20 { 399 compatible = "ti,tca6416"; 400 reg = <0x20>; 401 gpio-controller; 402 #gpio-cells = <2>; 403 }; 404 405 exp2: gpio@22 { 406 compatible = "ti,tca6424"; 407 reg = <0x22>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 411 p09-hog { 412 /* P11 - MCASP/TRACE_MUX_S0 */ 413 gpio-hog; 414 gpios = <9 GPIO_ACTIVE_HIGH>; 415 output-low; 416 line-name = "MCASP/TRACE_MUX_S0"; 417 }; 418 419 p10-hog { 420 /* P12 - MCASP/TRACE_MUX_S1 */ 421 gpio-hog; 422 gpios = <10 GPIO_ACTIVE_HIGH>; 423 output-high; 424 line-name = "MCASP/TRACE_MUX_S1"; 425 }; 426 }; 427}; 428 429&main_i2c1 { 430 pinctrl-names = "default"; 431 pinctrl-0 = <&main_i2c1_pins_default>; 432 clock-frequency = <400000>; 433 434 exp4: gpio@20 { 435 compatible = "ti,tca6408"; 436 reg = <0x20>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 441 interrupt-parent = <&main_gpio1>; 442 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 }; 446}; 447 448&k3_clks { 449 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 450 pinctrl-names = "default"; 451 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 452}; 453 454&main_i2c3 { 455 pinctrl-names = "default"; 456 pinctrl-0 = <&main_i2c3_pins_default>; 457 clock-frequency = <400000>; 458 459 exp3: gpio@20 { 460 compatible = "ti,tca6408"; 461 reg = <0x20>; 462 gpio-controller; 463 #gpio-cells = <2>; 464 }; 465 466 pcm3168a_1: audio-codec@44 { 467 compatible = "ti,pcm3168a"; 468 reg = <0x44>; 469 470 #sound-dai-cells = <1>; 471 472 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 473 474 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 475 clocks = <&k3_clks 157 371>; 476 clock-names = "scki"; 477 478 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 479 assigned-clocks = <&k3_clks 157 371>; 480 assigned-clock-parents = <&k3_clks 157 400>; 481 assigned-clock-rates = <24576000>; /* for 48KHz */ 482 483 VDD1-supply = <&vsys_3v3>; 484 VDD2-supply = <&vsys_3v3>; 485 VCCAD1-supply = <&vsys_5v0>; 486 VCCAD2-supply = <&vsys_5v0>; 487 VCCDA1-supply = <&vsys_5v0>; 488 VCCDA2-supply = <&vsys_5v0>; 489 }; 490}; 491 492&main_i2c6 { 493 pinctrl-names = "default"; 494 pinctrl-0 = <&main_i2c6_pins_default>; 495 clock-frequency = <400000>; 496 497 exp5: gpio@20 { 498 compatible = "ti,tca6408"; 499 reg = <0x20>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 }; 503}; 504 505&mcu_cpsw { 506 pinctrl-names = "default"; 507 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 508}; 509 510&davinci_mdio { 511 phy0: ethernet-phy@0 { 512 reg = <0>; 513 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 514 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 515 }; 516}; 517 518&cpsw_port1 { 519 phy-mode = "rgmii-rxid"; 520 phy-handle = <&phy0>; 521}; 522 523&dss { 524 /* 525 * These clock assignments are chosen to enable the following outputs: 526 * 527 * VP0 - DisplayPort SST 528 * VP1 - DPI0 529 * VP2 - DSI 530 * VP3 - DPI1 531 */ 532 533 assigned-clocks = <&k3_clks 152 1>, 534 <&k3_clks 152 4>, 535 <&k3_clks 152 9>, 536 <&k3_clks 152 13>; 537 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 538 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 539 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 540 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 541}; 542 543&mcasp10 { 544 #sound-dai-cells = <0>; 545 546 pinctrl-names = "default"; 547 pinctrl-0 = <&mcasp10_pins_default>; 548 549 op-mode = <0>; /* MCASP_IIS_MODE */ 550 tdm-slots = <2>; 551 auxclk-fs-ratio = <256>; 552 553 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 554 1 1 1 1 555 2 2 2 0 556 >; 557 tx-num-evt = <0>; 558 rx-num-evt = <0>; 559 560 status = "okay"; 561}; 562 563&serdes0 { 564 serdes0_pcie_link: link@0 { 565 reg = <0>; 566 cdns,num-lanes = <1>; 567 #phy-cells = <0>; 568 cdns,phy-type = <PHY_TYPE_PCIE>; 569 resets = <&serdes_wiz0 1>; 570 }; 571}; 572 573&serdes1 { 574 serdes1_pcie_link: link@0 { 575 reg = <0>; 576 cdns,num-lanes = <2>; 577 #phy-cells = <0>; 578 cdns,phy-type = <PHY_TYPE_PCIE>; 579 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 580 }; 581}; 582 583&serdes2 { 584 serdes2_pcie_link: link@0 { 585 reg = <0>; 586 cdns,num-lanes = <2>; 587 #phy-cells = <0>; 588 cdns,phy-type = <PHY_TYPE_PCIE>; 589 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 590 }; 591}; 592 593&pcie0_rc { 594 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 595 phys = <&serdes0_pcie_link>; 596 phy-names = "pcie-phy"; 597 num-lanes = <1>; 598}; 599 600&pcie1_rc { 601 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 602 phys = <&serdes1_pcie_link>; 603 phy-names = "pcie-phy"; 604 num-lanes = <2>; 605}; 606 607&pcie2_rc { 608 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 609 phys = <&serdes2_pcie_link>; 610 phy-names = "pcie-phy"; 611 num-lanes = <2>; 612}; 613 614&pcie0_ep { 615 phys = <&serdes0_pcie_link>; 616 phy-names = "pcie-phy"; 617 num-lanes = <1>; 618 status = "disabled"; 619}; 620 621&pcie1_ep { 622 phys = <&serdes1_pcie_link>; 623 phy-names = "pcie-phy"; 624 num-lanes = <2>; 625 status = "disabled"; 626}; 627 628&pcie2_ep { 629 phys = <&serdes2_pcie_link>; 630 phy-names = "pcie-phy"; 631 num-lanes = <2>; 632 status = "disabled"; 633}; 634 635&pcie3_rc { 636 status = "disabled"; 637}; 638 639&pcie3_ep { 640 status = "disabled"; 641}; 642