1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-cadence.h> 13 14/ { 15 compatible = "ti,j721e-evm", "ti,j721e"; 16 model = "Texas Instruments J721e EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 21 }; 22 23 gpio_keys: gpio-keys { 24 compatible = "gpio-keys"; 25 autorepeat; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; 28 29 sw10: sw10 { 30 label = "GPIO Key USER1"; 31 linux,code = <BTN_0>; 32 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 33 }; 34 35 sw11: sw11 { 36 label = "GPIO Key USER2"; 37 linux,code = <BTN_1>; 38 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 39 }; 40 }; 41 42 evm_12v0: fixedregulator-evm12v0 { 43 /* main supply */ 44 compatible = "regulator-fixed"; 45 regulator-name = "evm_12v0"; 46 regulator-min-microvolt = <12000000>; 47 regulator-max-microvolt = <12000000>; 48 regulator-always-on; 49 regulator-boot-on; 50 }; 51 52 vsys_3v3: fixedregulator-vsys3v3 { 53 /* Output of LMS140 */ 54 compatible = "regulator-fixed"; 55 regulator-name = "vsys_3v3"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 vin-supply = <&evm_12v0>; 59 regulator-always-on; 60 regulator-boot-on; 61 }; 62 63 vsys_5v0: fixedregulator-vsys5v0 { 64 /* Output of LM5140 */ 65 compatible = "regulator-fixed"; 66 regulator-name = "vsys_5v0"; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 vin-supply = <&evm_12v0>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 vdd_mmc1: fixedregulator-sd { 75 compatible = "regulator-fixed"; 76 regulator-name = "vdd_mmc1"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 regulator-boot-on; 80 enable-active-high; 81 vin-supply = <&vsys_3v3>; 82 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 83 }; 84 85 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 86 compatible = "regulator-gpio"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 89 regulator-name = "tlv71033"; 90 regulator-min-microvolt = <1800000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-boot-on; 93 vin-supply = <&vsys_5v0>; 94 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 95 states = <1800000 0x0>, 96 <3300000 0x1>; 97 }; 98 99 sound0: sound@0 { 100 compatible = "ti,j721e-cpb-audio"; 101 model = "j721e-cpb"; 102 103 ti,cpb-mcasp = <&mcasp10>; 104 ti,cpb-codec = <&pcm3168a_1>; 105 106 clocks = <&k3_clks 184 1>, 107 <&k3_clks 184 2>, <&k3_clks 184 4>, 108 <&k3_clks 157 371>, 109 <&k3_clks 157 400>, <&k3_clks 157 401>; 110 clock-names = "cpb-mcasp-auxclk", 111 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 112 "cpb-codec-scki", 113 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 114 }; 115}; 116 117&main_pmx0 { 118 sw10_button_pins_default: sw10-button-pins-default { 119 pinctrl-single,pins = < 120 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 121 >; 122 }; 123 124 main_mmc1_pins_default: main-mmc1-pins-default { 125 pinctrl-single,pins = < 126 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 127 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 128 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 129 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 130 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 131 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 132 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 133 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 134 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 135 >; 136 }; 137 138 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 139 pinctrl-single,pins = < 140 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 141 >; 142 }; 143 144 main_usbss0_pins_default: main-usbss0-pins-default { 145 pinctrl-single,pins = < 146 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 147 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 148 >; 149 }; 150 151 main_usbss1_pins_default: main-usbss1-pins-default { 152 pinctrl-single,pins = < 153 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 154 >; 155 }; 156 157 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { 158 pinctrl-single,pins = < 159 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 160 >; 161 }; 162 163 main_i2c0_pins_default: main-i2c0-pins-default { 164 pinctrl-single,pins = < 165 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 166 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 167 >; 168 }; 169 170 main_i2c1_pins_default: main-i2c1-pins-default { 171 pinctrl-single,pins = < 172 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 173 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 174 >; 175 }; 176 177 main_i2c3_pins_default: main-i2c3-pins-default { 178 pinctrl-single,pins = < 179 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 180 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 181 >; 182 }; 183 184 main_i2c6_pins_default: main-i2c6-pins-default { 185 pinctrl-single,pins = < 186 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 187 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 188 >; 189 }; 190 191 mcasp10_pins_default: mcasp10-pins-default { 192 pinctrl-single,pins = < 193 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 194 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 195 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 196 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 197 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 198 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 199 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 200 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 201 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 202 >; 203 }; 204 205 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { 206 pinctrl-single,pins = < 207 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 208 >; 209 }; 210}; 211 212&wkup_pmx0 { 213 sw11_button_pins_default: sw11-button-pins-default { 214 pinctrl-single,pins = < 215 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 216 >; 217 }; 218 219 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 220 pinctrl-single,pins = < 221 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 222 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 223 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 224 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 225 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 226 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 227 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 228 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 229 >; 230 }; 231 232 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 233 pinctrl-single,pins = < 234 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 235 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 236 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 237 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 238 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 239 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 240 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 241 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 242 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 243 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 244 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 245 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 246 >; 247 }; 248 249 mcu_mdio_pins_default: mcu-mdio1-pins-default { 250 pinctrl-single,pins = < 251 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 252 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 253 >; 254 }; 255}; 256 257&wkup_uart0 { 258 /* Wakeup UART is used by System firmware */ 259 status = "reserved"; 260}; 261 262&main_uart0 { 263 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 264}; 265 266&main_uart3 { 267 /* UART not brought out */ 268 status = "disabled"; 269}; 270 271&main_uart5 { 272 /* UART not brought out */ 273 status = "disabled"; 274}; 275 276&main_uart6 { 277 /* UART not brought out */ 278 status = "disabled"; 279}; 280 281&main_uart7 { 282 /* UART not brought out */ 283 status = "disabled"; 284}; 285 286&main_uart8 { 287 /* UART not brought out */ 288 status = "disabled"; 289}; 290 291&main_uart9 { 292 /* UART not brought out */ 293 status = "disabled"; 294}; 295 296&main_gpio2 { 297 status = "disabled"; 298}; 299 300&main_gpio3 { 301 status = "disabled"; 302}; 303 304&main_gpio4 { 305 status = "disabled"; 306}; 307 308&main_gpio5 { 309 status = "disabled"; 310}; 311 312&main_gpio6 { 313 status = "disabled"; 314}; 315 316&main_gpio7 { 317 status = "disabled"; 318}; 319 320&wkup_gpio1 { 321 status = "disabled"; 322}; 323 324&main_sdhci0 { 325 /* eMMC */ 326 non-removable; 327 ti,driver-strength-ohm = <50>; 328 disable-wp; 329}; 330 331&main_sdhci1 { 332 /* SD/MMC */ 333 vmmc-supply = <&vdd_mmc1>; 334 vqmmc-supply = <&vdd_sd_dv_alt>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&main_mmc1_pins_default>; 337 ti,driver-strength-ohm = <50>; 338 disable-wp; 339}; 340 341&main_sdhci2 { 342 /* Unused */ 343 status = "disabled"; 344}; 345 346&usb_serdes_mux { 347 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 348}; 349 350&serdes_ln_ctrl { 351 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 352 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 353 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 354 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 355 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 356 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 357}; 358 359&serdes_wiz3 { 360 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 361 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 362}; 363 364&serdes3 { 365 serdes3_usb_link: phy@0 { 366 reg = <0>; 367 cdns,num-lanes = <2>; 368 #phy-cells = <0>; 369 cdns,phy-type = <PHY_TYPE_USB3>; 370 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 371 }; 372}; 373 374&usbss0 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&main_usbss0_pins_default>; 377 ti,vbus-divider; 378}; 379 380&usb0 { 381 dr_mode = "otg"; 382 maximum-speed = "super-speed"; 383 phys = <&serdes3_usb_link>; 384 phy-names = "cdns3,usb3-phy"; 385}; 386 387&usbss1 { 388 pinctrl-names = "default"; 389 pinctrl-0 = <&main_usbss1_pins_default>; 390 ti,usb2-only; 391}; 392 393&usb1 { 394 dr_mode = "host"; 395 maximum-speed = "high-speed"; 396}; 397 398&ospi1 { 399 pinctrl-names = "default"; 400 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 401 402 flash@0{ 403 compatible = "jedec,spi-nor"; 404 reg = <0x0>; 405 spi-tx-bus-width = <1>; 406 spi-rx-bus-width = <4>; 407 spi-max-frequency = <40000000>; 408 cdns,tshsl-ns = <60>; 409 cdns,tsd2d-ns = <60>; 410 cdns,tchsh-ns = <60>; 411 cdns,tslch-ns = <60>; 412 cdns,read-delay = <2>; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 }; 416}; 417 418&tscadc0 { 419 adc { 420 ti,adc-channels = <0 1 2 3 4 5 6 7>; 421 }; 422}; 423 424&tscadc1 { 425 adc { 426 ti,adc-channels = <0 1 2 3 4 5 6 7>; 427 }; 428}; 429 430&main_i2c0 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&main_i2c0_pins_default>; 433 clock-frequency = <400000>; 434 435 exp1: gpio@20 { 436 compatible = "ti,tca6416"; 437 reg = <0x20>; 438 gpio-controller; 439 #gpio-cells = <2>; 440 }; 441 442 exp2: gpio@22 { 443 compatible = "ti,tca6424"; 444 reg = <0x22>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 448 p09-hog { 449 /* P11 - MCASP/TRACE_MUX_S0 */ 450 gpio-hog; 451 gpios = <9 GPIO_ACTIVE_HIGH>; 452 output-low; 453 line-name = "MCASP/TRACE_MUX_S0"; 454 }; 455 456 p10-hog { 457 /* P12 - MCASP/TRACE_MUX_S1 */ 458 gpio-hog; 459 gpios = <10 GPIO_ACTIVE_HIGH>; 460 output-high; 461 line-name = "MCASP/TRACE_MUX_S1"; 462 }; 463 }; 464}; 465 466&main_i2c1 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&main_i2c1_pins_default>; 469 clock-frequency = <400000>; 470 471 exp4: gpio@20 { 472 compatible = "ti,tca6408"; 473 reg = <0x20>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 478 interrupt-parent = <&main_gpio1>; 479 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 }; 483}; 484 485&k3_clks { 486 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 487 pinctrl-names = "default"; 488 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 489}; 490 491&main_i2c3 { 492 pinctrl-names = "default"; 493 pinctrl-0 = <&main_i2c3_pins_default>; 494 clock-frequency = <400000>; 495 496 exp3: gpio@20 { 497 compatible = "ti,tca6408"; 498 reg = <0x20>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 }; 502 503 pcm3168a_1: audio-codec@44 { 504 compatible = "ti,pcm3168a"; 505 reg = <0x44>; 506 507 #sound-dai-cells = <1>; 508 509 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 510 511 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 512 clocks = <&k3_clks 157 371>; 513 clock-names = "scki"; 514 515 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 516 assigned-clocks = <&k3_clks 157 371>; 517 assigned-clock-parents = <&k3_clks 157 400>; 518 assigned-clock-rates = <24576000>; /* for 48KHz */ 519 520 VDD1-supply = <&vsys_3v3>; 521 VDD2-supply = <&vsys_3v3>; 522 VCCAD1-supply = <&vsys_5v0>; 523 VCCAD2-supply = <&vsys_5v0>; 524 VCCDA1-supply = <&vsys_5v0>; 525 VCCDA2-supply = <&vsys_5v0>; 526 }; 527}; 528 529&main_i2c6 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&main_i2c6_pins_default>; 532 clock-frequency = <400000>; 533 534 exp5: gpio@20 { 535 compatible = "ti,tca6408"; 536 reg = <0x20>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 }; 540}; 541 542&mcu_cpsw { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 545}; 546 547&davinci_mdio { 548 phy0: ethernet-phy@0 { 549 reg = <0>; 550 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 551 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 552 }; 553}; 554 555&cpsw_port1 { 556 phy-mode = "rgmii-rxid"; 557 phy-handle = <&phy0>; 558}; 559 560&dss { 561 /* 562 * These clock assignments are chosen to enable the following outputs: 563 * 564 * VP0 - DisplayPort SST 565 * VP1 - DPI0 566 * VP2 - DSI 567 * VP3 - DPI1 568 */ 569 570 assigned-clocks = <&k3_clks 152 1>, 571 <&k3_clks 152 4>, 572 <&k3_clks 152 9>, 573 <&k3_clks 152 13>; 574 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 575 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 576 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 577 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 578}; 579 580&mcasp0 { 581 status = "disabled"; 582}; 583 584&mcasp1 { 585 status = "disabled"; 586}; 587 588&mcasp2 { 589 status = "disabled"; 590}; 591 592&mcasp3 { 593 status = "disabled"; 594}; 595 596&mcasp4 { 597 status = "disabled"; 598}; 599 600&mcasp5 { 601 status = "disabled"; 602}; 603 604&mcasp6 { 605 status = "disabled"; 606}; 607 608&mcasp7 { 609 status = "disabled"; 610}; 611 612&mcasp8 { 613 status = "disabled"; 614}; 615 616&mcasp9 { 617 status = "disabled"; 618}; 619 620&mcasp10 { 621 #sound-dai-cells = <0>; 622 623 pinctrl-names = "default"; 624 pinctrl-0 = <&mcasp10_pins_default>; 625 626 op-mode = <0>; /* MCASP_IIS_MODE */ 627 tdm-slots = <2>; 628 auxclk-fs-ratio = <256>; 629 630 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 631 1 1 1 1 632 2 2 2 0 633 >; 634 tx-num-evt = <0>; 635 rx-num-evt = <0>; 636}; 637 638&mcasp11 { 639 status = "disabled"; 640}; 641 642&cmn_refclk1 { 643 clock-frequency = <100000000>; 644}; 645 646&wiz0_pll1_refclk { 647 assigned-clocks = <&wiz0_pll1_refclk>; 648 assigned-clock-parents = <&cmn_refclk1>; 649}; 650 651&wiz0_refclk_dig { 652 assigned-clocks = <&wiz0_refclk_dig>; 653 assigned-clock-parents = <&cmn_refclk1>; 654}; 655 656&wiz1_pll1_refclk { 657 assigned-clocks = <&wiz1_pll1_refclk>; 658 assigned-clock-parents = <&cmn_refclk1>; 659}; 660 661&wiz1_refclk_dig { 662 assigned-clocks = <&wiz1_refclk_dig>; 663 assigned-clock-parents = <&cmn_refclk1>; 664}; 665 666&wiz2_pll1_refclk { 667 assigned-clocks = <&wiz2_pll1_refclk>; 668 assigned-clock-parents = <&cmn_refclk1>; 669}; 670 671&wiz2_refclk_dig { 672 assigned-clocks = <&wiz2_refclk_dig>; 673 assigned-clock-parents = <&cmn_refclk1>; 674}; 675 676&serdes0 { 677 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; 678 assigned-clock-parents = <&wiz0_pll1_refclk>; 679 680 serdes0_pcie_link: phy@0 { 681 reg = <0>; 682 cdns,num-lanes = <1>; 683 #phy-cells = <0>; 684 cdns,phy-type = <PHY_TYPE_PCIE>; 685 resets = <&serdes_wiz0 1>; 686 }; 687}; 688 689&serdes1 { 690 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; 691 assigned-clock-parents = <&wiz1_pll1_refclk>; 692 693 serdes1_pcie_link: phy@0 { 694 reg = <0>; 695 cdns,num-lanes = <2>; 696 #phy-cells = <0>; 697 cdns,phy-type = <PHY_TYPE_PCIE>; 698 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 699 }; 700}; 701 702&serdes2 { 703 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; 704 assigned-clock-parents = <&wiz2_pll1_refclk>; 705 706 serdes2_pcie_link: phy@0 { 707 reg = <0>; 708 cdns,num-lanes = <2>; 709 #phy-cells = <0>; 710 cdns,phy-type = <PHY_TYPE_PCIE>; 711 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 712 }; 713}; 714 715&pcie0_rc { 716 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 717 phys = <&serdes0_pcie_link>; 718 phy-names = "pcie-phy"; 719 num-lanes = <1>; 720}; 721 722&pcie1_rc { 723 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 724 phys = <&serdes1_pcie_link>; 725 phy-names = "pcie-phy"; 726 num-lanes = <2>; 727}; 728 729&pcie2_rc { 730 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 731 phys = <&serdes2_pcie_link>; 732 phy-names = "pcie-phy"; 733 num-lanes = <2>; 734}; 735 736&pcie0_ep { 737 phys = <&serdes0_pcie_link>; 738 phy-names = "pcie-phy"; 739 num-lanes = <1>; 740 status = "disabled"; 741}; 742 743&pcie1_ep { 744 phys = <&serdes1_pcie_link>; 745 phy-names = "pcie-phy"; 746 num-lanes = <2>; 747 status = "disabled"; 748}; 749 750&pcie2_ep { 751 phys = <&serdes2_pcie_link>; 752 phy-names = "pcie-phy"; 753 num-lanes = <2>; 754 status = "disabled"; 755}; 756 757&pcie3_rc { 758 status = "disabled"; 759}; 760 761&pcie3_ep { 762 status = "disabled"; 763}; 764 765&dss { 766 status = "disabled"; 767}; 768 769&icssg0_mdio { 770 status = "disabled"; 771}; 772 773&icssg1_mdio { 774 status = "disabled"; 775}; 776