1// SPDX-License-Identifier: GPL-2.0 2/* 3 * https://beagleboard.org/ai-64 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation 6 * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation 7 */ 8 9/dts-v1/; 10 11#include "k3-j721e.dtsi" 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/leds/common.h> 15#include <dt-bindings/net/ti-dp83867.h> 16#include <dt-bindings/phy/phy-cadence.h> 17 18/ { 19 compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; 20 model = "BeagleBoard.org BeagleBone AI-64"; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial2 = &main_uart0; 25 mmc0 = &main_sdhci0; 26 mmc1 = &main_sdhci1; 27 i2c0 = &wkup_i2c0; 28 i2c1 = &main_i2c6; 29 i2c2 = &main_i2c2; 30 i2c3 = &main_i2c4; 31 }; 32 33 chosen { 34 stdout-path = "serial2:115200n8"; 35 }; 36 37 memory@80000000 { 38 device_type = "memory"; 39 /* 4G RAM */ 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 41 <0x00000008 0x80000000 0x00000000 0x80000000>; 42 }; 43 44 reserved_memory: reserved-memory { 45 #address-cells = <2>; 46 #size-cells = <2>; 47 ranges; 48 49 secure_ddr: optee@9e800000 { 50 reg = <0x00 0x9e800000 0x00 0x01800000>; 51 no-map; 52 }; 53 54 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa0000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa0100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa1000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa1100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa2000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa2100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa3000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa3100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa4000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa4100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0x00 0xa5000000 0x00 0x100000>; 117 no-map; 118 }; 119 120 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 121 compatible = "shared-dma-pool"; 122 reg = <0x00 0xa5100000 0x00 0xf00000>; 123 no-map; 124 }; 125 126 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 127 compatible = "shared-dma-pool"; 128 reg = <0x00 0xa6000000 0x00 0x100000>; 129 no-map; 130 }; 131 132 c66_0_memory_region: c66-memory@a6100000 { 133 compatible = "shared-dma-pool"; 134 reg = <0x00 0xa6100000 0x00 0xf00000>; 135 no-map; 136 }; 137 138 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 139 compatible = "shared-dma-pool"; 140 reg = <0x00 0xa7000000 0x00 0x100000>; 141 no-map; 142 }; 143 144 c66_1_memory_region: c66-memory@a7100000 { 145 compatible = "shared-dma-pool"; 146 reg = <0x00 0xa7100000 0x00 0xf00000>; 147 no-map; 148 }; 149 150 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 151 compatible = "shared-dma-pool"; 152 reg = <0x00 0xa8000000 0x00 0x100000>; 153 no-map; 154 }; 155 156 c71_0_memory_region: c71-memory@a8100000 { 157 compatible = "shared-dma-pool"; 158 reg = <0x00 0xa8100000 0x00 0xf00000>; 159 no-map; 160 }; 161 162 rtos_ipc_memory_region: ipc-memories@aa000000 { 163 reg = <0x00 0xaa000000 0x00 0x01c00000>; 164 alignment = <0x1000>; 165 no-map; 166 }; 167 }; 168 169 gpio_keys: gpio-keys { 170 compatible = "gpio-keys"; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&sw_pwr_pins_default>; 173 174 button-1 { 175 label = "BOOT"; 176 linux,code = <BTN_0>; 177 gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; 178 }; 179 180 button-2 { 181 label = "POWER"; 182 linux,code = <KEY_POWER>; 183 gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; 184 }; 185 }; 186 187 leds { 188 compatible = "gpio-leds"; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&led_pins_default>; 191 192 led-0 { 193 gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; 194 function = LED_FUNCTION_HEARTBEAT; 195 linux,default-trigger = "heartbeat"; 196 }; 197 198 led-1 { 199 gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; 200 function = LED_FUNCTION_DISK_ACTIVITY; 201 linux,default-trigger = "mmc0"; 202 }; 203 204 led-2 { 205 gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; 206 function = LED_FUNCTION_CPU; 207 linux,default-trigger = "cpu"; 208 }; 209 210 led-3 { 211 gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; 212 function = LED_FUNCTION_DISK_ACTIVITY; 213 linux,default-trigger = "mmc1"; 214 }; 215 216 led-4 { 217 gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; 218 function = LED_FUNCTION_WLAN; 219 default-state = "off"; 220 }; 221 }; 222 223 evm_12v0: regulator-0 { 224 /* main supply */ 225 compatible = "regulator-fixed"; 226 regulator-name = "evm_12v0"; 227 regulator-min-microvolt = <12000000>; 228 regulator-max-microvolt = <12000000>; 229 regulator-always-on; 230 regulator-boot-on; 231 }; 232 233 vsys_3v3: regulator-1 { 234 /* Output of LMS140 */ 235 compatible = "regulator-fixed"; 236 regulator-name = "vsys_3v3"; 237 regulator-min-microvolt = <3300000>; 238 regulator-max-microvolt = <3300000>; 239 vin-supply = <&evm_12v0>; 240 regulator-always-on; 241 regulator-boot-on; 242 }; 243 244 vsys_5v0: regulator-2 { 245 /* Output of LM5140 */ 246 compatible = "regulator-fixed"; 247 regulator-name = "vsys_5v0"; 248 regulator-min-microvolt = <5000000>; 249 regulator-max-microvolt = <5000000>; 250 vin-supply = <&evm_12v0>; 251 regulator-always-on; 252 regulator-boot-on; 253 }; 254 255 vdd_mmc1: regulator-3 { 256 compatible = "regulator-fixed"; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&sd_pwr_en_pins_default>; 259 regulator-name = "vdd_mmc1"; 260 regulator-min-microvolt = <3300000>; 261 regulator-max-microvolt = <3300000>; 262 regulator-boot-on; 263 enable-active-high; 264 vin-supply = <&vsys_3v3>; 265 gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; 266 }; 267 268 vdd_sd_dv_alt: regulator-4 { 269 compatible = "regulator-gpio"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 272 regulator-name = "tlv71033"; 273 regulator-min-microvolt = <1800000>; 274 regulator-max-microvolt = <3300000>; 275 regulator-boot-on; 276 vin-supply = <&vsys_5v0>; 277 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 278 states = <1800000 0x0>, 279 <3300000 0x1>; 280 }; 281 282 dp_pwr_3v3: regulator-5 { 283 compatible = "regulator-fixed"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&dp0_3v3_en_pins_default>; 286 regulator-name = "dp-pwr"; 287 regulator-min-microvolt = <3300000>; 288 regulator-max-microvolt = <3300000>; 289 gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ 290 enable-active-high; 291 }; 292 293 dp0: connector { 294 compatible = "dp-connector"; 295 label = "DP0"; 296 type = "full-size"; 297 dp-pwr-supply = <&dp_pwr_3v3>; 298 299 port { 300 dp_connector_in: endpoint { 301 remote-endpoint = <&dp0_out>; 302 }; 303 }; 304 }; 305}; 306 307&main_pmx0 { 308 led_pins_default: led-default-pins { 309 pinctrl-single,pins = < 310 J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ 311 J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ 312 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 313 J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ 314 J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ 315 >; 316 }; 317 318 main_mmc1_pins_default: main-mmc1-default-pins { 319 pinctrl-single,pins = < 320 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 321 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 322 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 323 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 324 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 325 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 326 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 327 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 328 >; 329 }; 330 331 main_uart0_pins_default: main-uart0-default-pins { 332 pinctrl-single,pins = < 333 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 334 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 335 >; 336 }; 337 338 sd_pwr_en_pins_default: sd-pwr-en-default-pins { 339 pinctrl-single,pins = < 340 J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 341 >; 342 }; 343 344 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 345 pinctrl-single,pins = < 346 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 347 >; 348 }; 349 350 main_usbss0_pins_default: main-usbss0-default-pins { 351 pinctrl-single,pins = < 352 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ 353 >; 354 }; 355 356 main_usbss1_pins_default: main-usbss1-default-pins { 357 pinctrl-single,pins = < 358 J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ 359 >; 360 }; 361 362 dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { 363 pinctrl-single,pins = < 364 J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ 365 >; 366 }; 367 368 dp0_pins_default: dp0-default-pins { 369 pinctrl-single,pins = < 370 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ 371 >; 372 }; 373 374 main_i2c0_pins_default: main-i2c0-default-pins { 375 pinctrl-single,pins = < 376 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 377 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 378 >; 379 }; 380 381 main_i2c1_pins_default: main-i2c1-default-pins { 382 pinctrl-single,pins = < 383 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 384 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 385 >; 386 }; 387 388 main_i2c2_pins_default: main-i2c2-default-pins { 389 pinctrl-single,pins = < 390 J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ 391 J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ 392 J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ 393 J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ 394 >; 395 }; 396 397 main_i2c3_pins_default: main-i2c3-default-pins { 398 pinctrl-single,pins = < 399 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 400 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 401 >; 402 }; 403 404 main_i2c4_pins_default: main-i2c4-default-pins { 405 pinctrl-single,pins = < 406 J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ 407 J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ 408 J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ 409 J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ 410 >; 411 }; 412 413 main_i2c5_pins_default: main-i2c5-default-pins { 414 pinctrl-single,pins = < 415 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 416 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 417 >; 418 }; 419 420 main_i2c6_pins_default: main-i2c6-default-pins { 421 pinctrl-single,pins = < 422 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 423 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 424 J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ 425 J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ 426 >; 427 }; 428 429 csi0_gpio_pins_default: csi0-gpio-default-pins { 430 pinctrl-single,pins = < 431 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 432 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 433 >; 434 }; 435 436 csi1_gpio_pins_default: csi1-gpio-default-pins { 437 pinctrl-single,pins = < 438 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 439 J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 440 >; 441 }; 442 443 pcie1_rst_pins_default: pcie1-rst-default-pins { 444 pinctrl-single,pins = < 445 J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ 446 >; 447 }; 448}; 449 450&wkup_pmx0 { 451 eeprom_wp_pins_default: eeprom-wp-default-pins { 452 pinctrl-single,pins = < 453 J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ 454 >; 455 }; 456 457 mcu_adc0_pins_default: mcu-adc0-default-pins { 458 pinctrl-single,pins = < 459 J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ 460 J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ 461 J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ 462 J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ 463 J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ 464 J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ 465 J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ 466 >; 467 }; 468 469 mcu_adc1_pins_default: mcu-adc1-default-pins { 470 pinctrl-single,pins = < 471 J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ 472 >; 473 }; 474 475 mikro_bus_pins_default: mikro-bus-default-pins { 476 pinctrl-single,pins = < 477 J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ 478 J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ 479 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ 480 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ 481 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ 482 483 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ 484 J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ 485 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ 486 J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ 487 488 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ 489 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ 490 491 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ 492 J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ 493 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ 494 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ 495 >; 496 }; 497 498 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 499 pinctrl-single,pins = < 500 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 501 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 502 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 503 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 504 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 505 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 506 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 507 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 508 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 509 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 510 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 511 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 512 >; 513 }; 514 515 mcu_mdio_pins_default: mcu-mdio1-default-pins { 516 pinctrl-single,pins = < 517 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 518 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 519 >; 520 }; 521 522 sw_pwr_pins_default: sw-pwr-default-pins { 523 pinctrl-single,pins = < 524 J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ 525 >; 526 }; 527 528 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 529 pinctrl-single,pins = < 530 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 531 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 532 >; 533 }; 534 535 wkup_uart0_pins_default: wkup-uart0-default-pins { 536 pinctrl-single,pins = < 537 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 538 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 539 >; 540 }; 541 542 mcu_usbss1_pins_default: mcu-usbss1-default-pins { 543 pinctrl-single,pins = < 544 J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ 545 >; 546 }; 547}; 548 549&wkup_uart0 { 550 /* Wakeup UART is used by TIFS firmware. */ 551 status = "reserved"; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&wkup_uart0_pins_default>; 554}; 555 556&main_uart0 { 557 status = "okay"; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&main_uart0_pins_default>; 560 /* Shared with ATF on this platform */ 561 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 562}; 563 564&main_sdhci0 { 565 /* eMMC */ 566 non-removable; 567 ti,driver-strength-ohm = <50>; 568 disable-wp; 569}; 570 571&main_sdhci1 { 572 /* SD Card */ 573 vmmc-supply = <&vdd_mmc1>; 574 vqmmc-supply = <&vdd_sd_dv_alt>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&main_mmc1_pins_default>; 577 ti,driver-strength-ohm = <50>; 578 disable-wp; 579}; 580 581&main_sdhci2 { 582 /* Unused */ 583 status = "disabled"; 584}; 585 586&ospi0 { 587 /* Unused */ 588 status = "disabled"; 589}; 590 591&ospi1 { 592 /* Unused */ 593 status = "disabled"; 594}; 595 596&main_i2c0 { 597 status = "okay"; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&main_i2c0_pins_default>; 600 clock-frequency = <400000>; 601}; 602 603&main_i2c1 { 604 status = "okay"; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&main_i2c1_pins_default>; 607 clock-frequency = <400000>; 608}; 609 610&main_i2c2 { 611 /* BBB Header: P9.19 and P9.20 */ 612 status = "okay"; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&main_i2c2_pins_default>; 615 clock-frequency = <100000>; 616}; 617 618&main_i2c3 { 619 status = "okay"; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&main_i2c3_pins_default>; 622 clock-frequency = <400000>; 623}; 624 625&main_i2c4 { 626 /* BBB Header: P9.24 and P9.26 */ 627 status = "okay"; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&main_i2c4_pins_default>; 630 clock-frequency = <100000>; 631}; 632 633&main_i2c5 { 634 status = "okay"; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&main_i2c5_pins_default>; 637 clock-frequency = <400000>; 638}; 639 640&main_i2c6 { 641 /* BBB Header: P9.17 and P9.18 */ 642 status = "okay"; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&main_i2c6_pins_default>; 645 clock-frequency = <100000>; 646 status = "okay"; 647}; 648 649&wkup_i2c0 { 650 status = "okay"; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&wkup_i2c0_pins_default>; 653 clock-frequency = <400000>; 654 655 eeprom@50 { 656 compatible = "atmel,24c04"; 657 reg = <0x50>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&eeprom_wp_pins_default>; 660 }; 661}; 662 663&main_gpio2 { 664 /* Unused */ 665 status = "disabled"; 666}; 667 668&main_gpio3 { 669 /* Unused */ 670 status = "disabled"; 671}; 672 673&main_gpio4 { 674 /* Unused */ 675 status = "disabled"; 676}; 677 678&main_gpio5 { 679 /* Unused */ 680 status = "disabled"; 681}; 682 683&main_gpio6 { 684 /* Unused */ 685 status = "disabled"; 686}; 687 688&main_gpio7 { 689 /* Unused */ 690 status = "disabled"; 691}; 692 693&wkup_gpio0 { 694 pinctrl-names = "default"; 695 pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, 696 <&mikro_bus_pins_default>; 697}; 698 699&wkup_gpio1 { 700 /* Unused */ 701 status = "disabled"; 702}; 703 704&main_gpio0 { 705 pinctrl-names = "default"; 706 pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; 707}; 708 709&usb_serdes_mux { 710 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 711}; 712 713&serdes_ln_ctrl { 714 idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 715 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 716 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 717 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 718 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 719 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 720}; 721 722&serdes_wiz3 { 723 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; 724 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 725}; 726 727&serdes3 { 728 serdes3_usb_link: phy@0 { 729 reg = <0>; 730 cdns,num-lanes = <2>; 731 #phy-cells = <0>; 732 cdns,phy-type = <PHY_TYPE_USB3>; 733 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 734 }; 735}; 736 737&serdes4 { 738 torrent_phy_dp: phy@0 { 739 reg = <0>; 740 resets = <&serdes_wiz4 1>; 741 cdns,phy-type = <PHY_TYPE_DP>; 742 cdns,num-lanes = <4>; 743 cdns,max-bit-rate = <5400>; 744 #phy-cells = <0>; 745 }; 746}; 747 748&mhdp { 749 phys = <&torrent_phy_dp>; 750 phy-names = "dpphy"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&dp0_pins_default>; 753}; 754 755&usbss0 { 756 pinctrl-names = "default"; 757 pinctrl-0 = <&main_usbss0_pins_default>; 758 ti,vbus-divider; 759}; 760 761&usb0 { 762 dr_mode = "peripheral"; 763 maximum-speed = "super-speed"; 764 phys = <&serdes3_usb_link>; 765 phy-names = "cdns3,usb3-phy"; 766}; 767 768&serdes2 { 769 serdes2_usb_link: phy@1 { 770 reg = <1>; 771 cdns,num-lanes = <1>; 772 #phy-cells = <0>; 773 cdns,phy-type = <PHY_TYPE_USB3>; 774 resets = <&serdes_wiz2 2>; 775 }; 776}; 777 778&usbss1 { 779 pinctrl-names = "default"; 780 pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; 781 ti,vbus-divider; 782}; 783 784&usb1 { 785 dr_mode = "host"; 786 maximum-speed = "super-speed"; 787 phys = <&serdes2_usb_link>; 788 phy-names = "cdns3,usb3-phy"; 789}; 790 791&tscadc0 { 792 /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ 793 adc { 794 ti,adc-channels = <0 1 2 3 4 5 6>; 795 }; 796}; 797 798&tscadc1 { 799 /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ 800 adc { 801 ti,adc-channels = <0>; 802 }; 803}; 804 805&mcu_cpsw { 806 pinctrl-names = "default"; 807 pinctrl-0 = <&mcu_cpsw_pins_default>; 808}; 809 810&davinci_mdio { 811 pinctrl-names = "default"; 812 pinctrl-0 = <&mcu_mdio_pins_default>; 813 814 phy0: ethernet-phy@0 { 815 reg = <0>; 816 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 817 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 818 }; 819}; 820 821&cpsw_port1 { 822 phy-mode = "rgmii-rxid"; 823 phy-handle = <&phy0>; 824}; 825 826&dss { 827 /* 828 * These clock assignments are chosen to enable the following outputs: 829 * 830 * VP0 - DisplayPort SST 831 * VP1 - DPI0 832 * VP2 - DSI 833 * VP3 - DPI1 834 */ 835 836 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 837 <&k3_clks 152 4>, /* VP 2 pixel clock */ 838 <&k3_clks 152 9>, /* VP 3 pixel clock */ 839 <&k3_clks 152 13>; /* VP 4 pixel clock */ 840 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 841 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 842 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 843 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 844}; 845 846&dss_ports { 847 port { 848 dpi0_out: endpoint { 849 remote-endpoint = <&dp0_in>; 850 }; 851 }; 852}; 853 854&dp0_ports { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 858 port@0 { 859 reg = <0>; 860 dp0_in: endpoint { 861 remote-endpoint = <&dpi0_out>; 862 }; 863 }; 864 865 port@4 { 866 reg = <4>; 867 dp0_out: endpoint { 868 remote-endpoint = <&dp_connector_in>; 869 }; 870 }; 871}; 872 873&serdes0 { 874 serdes0_pcie_link: phy@0 { 875 reg = <0>; 876 cdns,num-lanes = <1>; 877 #phy-cells = <0>; 878 cdns,phy-type = <PHY_TYPE_PCIE>; 879 resets = <&serdes_wiz0 1>; 880 }; 881}; 882 883&serdes1 { 884 serdes1_pcie_link: phy@0 { 885 reg = <0>; 886 cdns,num-lanes = <2>; 887 #phy-cells = <0>; 888 cdns,phy-type = <PHY_TYPE_PCIE>; 889 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 890 }; 891}; 892 893&pcie1_rc { 894 status = "okay"; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&pcie1_rst_pins_default>; 897 phys = <&serdes1_pcie_link>; 898 phy-names = "pcie-phy"; 899 num-lanes = <2>; 900 max-link-speed = <3>; 901 reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; 902}; 903 904&ufs_wrapper { 905 status = "disabled"; 906}; 907 908&mailbox0_cluster0 { 909 status = "okay"; 910 interrupts = <436>; 911 912 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 913 ti,mbox-rx = <0 0 0>; 914 ti,mbox-tx = <1 0 0>; 915 }; 916 917 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 918 ti,mbox-rx = <2 0 0>; 919 ti,mbox-tx = <3 0 0>; 920 }; 921}; 922 923&mailbox0_cluster1 { 924 status = "okay"; 925 interrupts = <432>; 926 927 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 928 ti,mbox-rx = <0 0 0>; 929 ti,mbox-tx = <1 0 0>; 930 }; 931 932 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 933 ti,mbox-rx = <2 0 0>; 934 ti,mbox-tx = <3 0 0>; 935 }; 936}; 937 938&mailbox0_cluster2 { 939 status = "okay"; 940 interrupts = <428>; 941 942 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 943 ti,mbox-rx = <0 0 0>; 944 ti,mbox-tx = <1 0 0>; 945 }; 946 947 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 948 ti,mbox-rx = <2 0 0>; 949 ti,mbox-tx = <3 0 0>; 950 }; 951}; 952 953&mailbox0_cluster3 { 954 status = "okay"; 955 interrupts = <424>; 956 957 mbox_c66_0: mbox-c66-0 { 958 ti,mbox-rx = <0 0 0>; 959 ti,mbox-tx = <1 0 0>; 960 }; 961 962 mbox_c66_1: mbox-c66-1 { 963 ti,mbox-rx = <2 0 0>; 964 ti,mbox-tx = <3 0 0>; 965 }; 966}; 967 968&mailbox0_cluster4 { 969 status = "okay"; 970 interrupts = <420>; 971 972 mbox_c71_0: mbox-c71-0 { 973 ti,mbox-rx = <0 0 0>; 974 ti,mbox-tx = <1 0 0>; 975 }; 976}; 977 978&mcu_r5fss0_core0 { 979 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; 980 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 981 <&mcu_r5fss0_core0_memory_region>; 982}; 983 984&mcu_r5fss0_core1 { 985 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; 986 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 987 <&mcu_r5fss0_core1_memory_region>; 988}; 989 990&main_r5fss0_core0 { 991 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; 992 memory-region = <&main_r5fss0_core0_dma_memory_region>, 993 <&main_r5fss0_core0_memory_region>; 994}; 995 996&main_r5fss0_core1 { 997 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; 998 memory-region = <&main_r5fss0_core1_dma_memory_region>, 999 <&main_r5fss0_core1_memory_region>; 1000}; 1001 1002&main_r5fss1_core0 { 1003 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; 1004 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1005 <&main_r5fss1_core0_memory_region>; 1006}; 1007 1008&main_r5fss1_core1 { 1009 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; 1010 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1011 <&main_r5fss1_core1_memory_region>; 1012}; 1013 1014&c66_0 { 1015 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; 1016 memory-region = <&c66_0_dma_memory_region>, 1017 <&c66_0_memory_region>; 1018}; 1019 1020&c66_1 { 1021 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; 1022 memory-region = <&c66_1_dma_memory_region>, 1023 <&c66_1_memory_region>; 1024}; 1025 1026&c71_0 { 1027 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 1028 memory-region = <&c71_0_dma_memory_region>, 1029 <&c71_0_memory_region>; 1030}; 1031