1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/soc/ti,sci_pm_domain.h> 11 12#include "k3-pinctrl.h" 13 14/ { 15 model = "Texas Instruments K3 J7200 SoC"; 16 compatible = "ti,j7200"; 17 interrupt-parent = <&gic500>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 serial0 = &wkup_uart0; 23 serial1 = &mcu_uart0; 24 serial2 = &main_uart0; 25 serial3 = &main_uart1; 26 serial4 = &main_uart2; 27 serial5 = &main_uart3; 28 serial6 = &main_uart4; 29 serial7 = &main_uart5; 30 serial8 = &main_uart6; 31 serial9 = &main_uart7; 32 serial10 = &main_uart8; 33 serial11 = &main_uart9; 34 mmc0 = &main_sdhci0; 35 mmc1 = &main_sdhci1; 36 }; 37 38 chosen { }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 cpu-map { 44 cluster0: cluster0 { 45 core0 { 46 cpu = <&cpu0>; 47 }; 48 49 core1 { 50 cpu = <&cpu1>; 51 }; 52 }; 53 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a72"; 58 reg = <0x000>; 59 device_type = "cpu"; 60 enable-method = "psci"; 61 i-cache-size = <0xc000>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 d-cache-size = <0x8000>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <256>; 67 next-level-cache = <&L2_0>; 68 }; 69 70 cpu1: cpu@1 { 71 compatible = "arm,cortex-a72"; 72 reg = <0x001>; 73 device_type = "cpu"; 74 enable-method = "psci"; 75 i-cache-size = <0xc000>; 76 i-cache-line-size = <64>; 77 i-cache-sets = <256>; 78 d-cache-size = <0x8000>; 79 d-cache-line-size = <64>; 80 d-cache-sets = <256>; 81 next-level-cache = <&L2_0>; 82 }; 83 }; 84 85 L2_0: l2-cache0 { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 cache-size = <0x100000>; 90 cache-line-size = <64>; 91 cache-sets = <1024>; 92 next-level-cache = <&msmc_l3>; 93 }; 94 95 msmc_l3: l3-cache0 { 96 compatible = "cache"; 97 cache-level = <3>; 98 }; 99 100 firmware { 101 optee { 102 compatible = "linaro,optee-tz"; 103 method = "smc"; 104 }; 105 106 psci: psci { 107 compatible = "arm,psci-1.0"; 108 method = "smc"; 109 }; 110 }; 111 112 a72_timer0: timer-cl0-cpu0 { 113 compatible = "arm,armv8-timer"; 114 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 115 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 116 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 117 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 118 }; 119 120 pmu: pmu { 121 compatible = "arm,cortex-a72-pmu"; 122 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 123 }; 124 125 cbass_main: bus@100000 { 126 compatible = "simple-bus"; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 130 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 131 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ 132 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ 133 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 134 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 135 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 136 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ 137 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ 138 139 /* MCUSS_WKUP Range */ 140 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 141 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 142 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 143 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 144 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 145 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 146 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 147 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 148 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 149 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 150 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 151 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 152 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 153 154 cbass_mcu_wakeup: bus@28380000 { 155 compatible = "simple-bus"; 156 #address-cells = <2>; 157 #size-cells = <2>; 158 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 159 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 160 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 161 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 162 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 163 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 164 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 165 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 166 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 167 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 168 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 169 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 170 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ 171 }; 172 }; 173}; 174 175/* Now include the peripherals for each bus segments */ 176#include "k3-j7200-main.dtsi" 177#include "k3-j7200-mcu-wakeup.dtsi" 178