1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9	dmsc: system-controller@44083000 {
10		compatible = "ti,k2g-sci";
11		ti,host-id = <12>;
12
13		mbox-names = "rx", "tx";
14
15		mboxes = <&secure_proxy_main 11>,
16			 <&secure_proxy_main 13>;
17
18		reg-names = "debug_messages";
19		reg = <0x00 0x44083000 0x00 0x1000>;
20
21		k3_pds: power-controller {
22			compatible = "ti,sci-pm-domain";
23			#power-domain-cells = <2>;
24		};
25
26		k3_clks: clock-controller {
27			compatible = "ti,k2g-sci-clk";
28			#clock-cells = <2>;
29		};
30
31		k3_reset: reset-controller {
32			compatible = "ti,sci-reset";
33			#reset-cells = <2>;
34		};
35	};
36
37	mcu_conf: syscon@40f00000 {
38		compatible = "syscon", "simple-mfd";
39		reg = <0x00 0x40f00000 0x00 0x20000>;
40		#address-cells = <1>;
41		#size-cells = <1>;
42		ranges = <0x00 0x00 0x40f00000 0x20000>;
43
44		phy_gmii_sel: phy@4040 {
45			compatible = "ti,am654-phy-gmii-sel";
46			reg = <0x4040 0x4>;
47			#phy-cells = <1>;
48		};
49	};
50
51	chipid@43000014 {
52		compatible = "ti,am654-chipid";
53		reg = <0x00 0x43000014 0x00 0x4>;
54	};
55
56	wkup_pmx0: pinctrl@4301c000 {
57		compatible = "pinctrl-single";
58		/* Proxy 0 addressing */
59		reg = <0x00 0x4301c000 0x00 0x178>;
60		#pinctrl-cells = <1>;
61		pinctrl-single,register-width = <32>;
62		pinctrl-single,function-mask = <0xffffffff>;
63	};
64
65	mcu_ram: sram@41c00000 {
66		compatible = "mmio-sram";
67		reg = <0x00 0x41c00000 0x00 0x100000>;
68		ranges = <0x00 0x00 0x41c00000 0x100000>;
69		#address-cells = <1>;
70		#size-cells = <1>;
71	};
72
73	wkup_uart0: serial@42300000 {
74		compatible = "ti,j721e-uart", "ti,am654-uart";
75		reg = <0x00 0x42300000 0x00 0x100>;
76		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
77		clock-frequency = <48000000>;
78		current-speed = <115200>;
79		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
80		clocks = <&k3_clks 287 2>;
81		clock-names = "fclk";
82	};
83
84	mcu_uart0: serial@40a00000 {
85		compatible = "ti,j721e-uart", "ti,am654-uart";
86		reg = <0x00 0x40a00000 0x00 0x100>;
87		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
88		clock-frequency = <96000000>;
89		current-speed = <115200>;
90		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
91		clocks = <&k3_clks 149 2>;
92		clock-names = "fclk";
93	};
94
95	wkup_gpio_intr: interrupt-controller@42200000 {
96		compatible = "ti,sci-intr";
97		reg = <0x00 0x42200000 0x00 0x400>;
98		ti,intr-trigger-type = <1>;
99		interrupt-controller;
100		interrupt-parent = <&gic500>;
101		#interrupt-cells = <1>;
102		ti,sci = <&dmsc>;
103		ti,sci-dev-id = <137>;
104		ti,interrupt-ranges = <16 960 16>;
105	};
106
107	wkup_gpio0: gpio@42110000 {
108		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
109		reg = <0x00 0x42110000 0x00 0x100>;
110		gpio-controller;
111		#gpio-cells = <2>;
112		interrupt-parent = <&wkup_gpio_intr>;
113		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
114		interrupt-controller;
115		#interrupt-cells = <2>;
116		ti,ngpio = <85>;
117		ti,davinci-gpio-unbanked = <0>;
118		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
119		clocks = <&k3_clks 113 0>;
120		clock-names = "gpio";
121	};
122
123	wkup_gpio1: gpio@42100000 {
124		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
125		reg = <0x00 0x42100000 0x00 0x100>;
126		gpio-controller;
127		#gpio-cells = <2>;
128		interrupt-parent = <&wkup_gpio_intr>;
129		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
130		interrupt-controller;
131		#interrupt-cells = <2>;
132		ti,ngpio = <85>;
133		ti,davinci-gpio-unbanked = <0>;
134		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
135		clocks = <&k3_clks 114 0>;
136		clock-names = "gpio";
137	};
138
139	mcu_navss: bus@28380000 {
140		compatible = "simple-mfd";
141		#address-cells = <2>;
142		#size-cells = <2>;
143		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
144		dma-coherent;
145		dma-ranges;
146		ti,sci-dev-id = <232>;
147
148		mcu_ringacc: ringacc@2b800000 {
149			compatible = "ti,am654-navss-ringacc";
150			reg =	<0x00 0x2b800000 0x00 0x400000>,
151				<0x00 0x2b000000 0x00 0x400000>,
152				<0x00 0x28590000 0x00 0x100>,
153				<0x00 0x2a500000 0x00 0x40000>;
154			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
155			ti,num-rings = <286>;
156			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
157			ti,sci = <&dmsc>;
158			ti,sci-dev-id = <235>;
159			msi-parent = <&main_udmass_inta>;
160		};
161
162		mcu_udmap: dma-controller@285c0000 {
163			compatible = "ti,j721e-navss-mcu-udmap";
164			reg =	<0x00 0x285c0000 0x00 0x100>,
165				<0x00 0x2a800000 0x00 0x40000>,
166				<0x00 0x2aa00000 0x00 0x40000>;
167			reg-names = "gcfg", "rchanrt", "tchanrt";
168			msi-parent = <&main_udmass_inta>;
169			#dma-cells = <1>;
170
171			ti,sci = <&dmsc>;
172			ti,sci-dev-id = <236>;
173			ti,ringacc = <&mcu_ringacc>;
174
175			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
176						<0x0f>; /* TX_HCHAN */
177			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
178						<0x0b>; /* RX_HCHAN */
179			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
180		};
181	};
182
183	mcu_cpsw: ethernet@46000000 {
184		compatible = "ti,j721e-cpsw-nuss";
185		#address-cells = <2>;
186		#size-cells = <2>;
187		reg = <0x00 0x46000000 0x00 0x200000>;
188		reg-names = "cpsw_nuss";
189		ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
190		dma-coherent;
191		clocks = <&k3_clks 18 21>;
192		clock-names = "fck";
193		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
194
195		dmas = <&mcu_udmap 0xf000>,
196		       <&mcu_udmap 0xf001>,
197		       <&mcu_udmap 0xf002>,
198		       <&mcu_udmap 0xf003>,
199		       <&mcu_udmap 0xf004>,
200		       <&mcu_udmap 0xf005>,
201		       <&mcu_udmap 0xf006>,
202		       <&mcu_udmap 0xf007>,
203		       <&mcu_udmap 0x7000>;
204		dma-names = "tx0", "tx1", "tx2", "tx3",
205			    "tx4", "tx5", "tx6", "tx7",
206			    "rx";
207
208		ethernet-ports {
209			#address-cells = <1>;
210			#size-cells = <0>;
211
212			cpsw_port1: port@1 {
213				reg = <1>;
214				ti,mac-only;
215				label = "port1";
216				ti,syscon-efuse = <&mcu_conf 0x200>;
217				phys = <&phy_gmii_sel 1>;
218			};
219		};
220
221		davinci_mdio: mdio@f00 {
222			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
223			reg = <0x00 0xf00 0x00 0x100>;
224			#address-cells = <1>;
225			#size-cells = <0>;
226			clocks = <&k3_clks 18 21>;
227			clock-names = "fck";
228			bus_freq = <1000000>;
229		};
230
231		cpts@3d000 {
232			compatible = "ti,am65-cpts";
233			reg = <0x00 0x3d000 0x00 0x400>;
234			clocks = <&k3_clks 18 2>;
235			clock-names = "cpts";
236			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
237			interrupt-names = "cpts";
238			ti,cpts-ext-ts-inputs = <4>;
239			ti,cpts-periodic-outputs = <2>;
240		};
241	};
242
243	mcu_i2c0: i2c@40b00000 {
244		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
245		reg = <0x00 0x40b00000 0x00 0x100>;
246		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
247		#address-cells = <1>;
248		#size-cells = <0>;
249		clock-names = "fck";
250		clocks = <&k3_clks 194 1>;
251		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
252	};
253
254	mcu_i2c1: i2c@40b10000 {
255		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
256		reg = <0x00 0x40b10000 0x00 0x100>;
257		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
258		#address-cells = <1>;
259		#size-cells = <0>;
260		clock-names = "fck";
261		clocks = <&k3_clks 195 1>;
262		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
263	};
264
265	wkup_i2c0: i2c@42120000 {
266		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
267		reg = <0x00 0x42120000 0x00 0x100>;
268		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
269		#address-cells = <1>;
270		#size-cells = <0>;
271		clock-names = "fck";
272		clocks = <&k3_clks 197 1>;
273		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
274	};
275
276	fss: syscon@47000000 {
277		compatible = "syscon", "simple-mfd";
278		reg = <0x00 0x47000000 0x00 0x100>;
279		#address-cells = <2>;
280		#size-cells = <2>;
281		ranges;
282
283		hbmc_mux: hbmc-mux {
284			compatible = "mmio-mux";
285			#mux-control-cells = <1>;
286			mux-reg-masks = <0x4 0x2>; /* HBMC select */
287		};
288
289		hbmc: hyperbus@47034000 {
290			compatible = "ti,am654-hbmc";
291			reg = <0x00 0x47034000 0x00 0x100>,
292				<0x05 0x00000000 0x01 0x0000000>;
293			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
294			clocks = <&k3_clks 102 0>;
295			assigned-clocks = <&k3_clks 102 5>;
296			assigned-clock-rates = <333333333>;
297			#address-cells = <2>;
298			#size-cells = <1>;
299			mux-controls = <&hbmc_mux 0>;
300		};
301
302		ospi0: spi@47040000 {
303			compatible = "ti,am654-ospi", "cdns,qspi-nor";
304			reg = <0x0 0x47040000 0x0 0x100>,
305			      <0x5 0x00000000 0x1 0x0000000>;
306			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
307			cdns,fifo-depth = <256>;
308			cdns,fifo-width = <4>;
309			cdns,trigger-address = <0x0>;
310			clocks = <&k3_clks 103 0>;
311			assigned-clocks = <&k3_clks 103 0>;
312			assigned-clock-parents = <&k3_clks 103 2>;
313			assigned-clock-rates = <166666666>;
314			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
315			#address-cells = <1>;
316			#size-cells = <0>;
317		};
318	};
319
320	tscadc0: tscadc@40200000 {
321		compatible = "ti,am3359-tscadc";
322		reg = <0x00 0x40200000 0x00 0x1000>;
323		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
324		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
325		clocks = <&k3_clks 0 1>;
326		assigned-clocks = <&k3_clks 0 3>;
327		assigned-clock-rates = <60000000>;
328		clock-names = "adc_tsc_fck";
329		dmas = <&main_udmap 0x7400>,
330			<&main_udmap 0x7401>;
331		dma-names = "fifo0", "fifo1";
332
333		adc {
334			#io-channel-cells = <1>;
335			compatible = "ti,am3359-adc";
336		};
337	};
338
339	mcu_r5fss0: r5fss@41000000 {
340		compatible = "ti,j7200-r5fss";
341		ti,cluster-mode = <1>;
342		#address-cells = <1>;
343		#size-cells = <1>;
344		ranges = <0x41000000 0x00 0x41000000 0x20000>,
345			 <0x41400000 0x00 0x41400000 0x20000>;
346		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
347
348		mcu_r5fss0_core0: r5f@41000000 {
349			compatible = "ti,j7200-r5f";
350			reg = <0x41000000 0x00010000>,
351			      <0x41010000 0x00010000>;
352			reg-names = "atcm", "btcm";
353			ti,sci = <&dmsc>;
354			ti,sci-dev-id = <250>;
355			ti,sci-proc-ids = <0x01 0xff>;
356			resets = <&k3_reset 250 1>;
357			firmware-name = "j7200-mcu-r5f0_0-fw";
358			ti,atcm-enable = <1>;
359			ti,btcm-enable = <1>;
360			ti,loczrama = <1>;
361		};
362
363		mcu_r5fss0_core1: r5f@41400000 {
364			compatible = "ti,j7200-r5f";
365			reg = <0x41400000 0x00008000>,
366			      <0x41410000 0x00008000>;
367			reg-names = "atcm", "btcm";
368			ti,sci = <&dmsc>;
369			ti,sci-dev-id = <251>;
370			ti,sci-proc-ids = <0x02 0xff>;
371			resets = <&k3_reset 251 1>;
372			firmware-name = "j7200-mcu-r5f0_1-fw";
373			ti,atcm-enable = <1>;
374			ti,btcm-enable = <1>;
375			ti,loczrama = <1>;
376		};
377	};
378
379	mcu_crypto: crypto@40900000 {
380		compatible = "ti,j721e-sa2ul";
381		reg = <0x00 0x40900000 0x00 0x1200>;
382		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
383		#address-cells = <2>;
384		#size-cells = <2>;
385		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
386		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
387		       <&mcu_udmap 0x7503>;
388		dma-names = "tx", "rx1", "rx2";
389		dma-coherent;
390
391		rng: rng@40910000 {
392			compatible = "inside-secure,safexcel-eip76";
393			reg = <0x00 0x40910000 0x00 0x7d>;
394			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
395			status = "disabled"; /* Used by OP-TEE */
396		};
397	};
398};
399