1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9	dmsc: system-controller@44083000 {
10		compatible = "ti,k2g-sci";
11		ti,host-id = <12>;
12
13		mbox-names = "rx", "tx";
14
15		mboxes = <&secure_proxy_main 11>,
16			 <&secure_proxy_main 13>;
17
18		reg-names = "debug_messages";
19		reg = <0x00 0x44083000 0x00 0x1000>;
20
21		k3_pds: power-controller {
22			compatible = "ti,sci-pm-domain";
23			#power-domain-cells = <2>;
24		};
25
26		k3_clks: clock-controller {
27			compatible = "ti,k2g-sci-clk";
28			#clock-cells = <2>;
29		};
30
31		k3_reset: reset-controller {
32			compatible = "ti,sci-reset";
33			#reset-cells = <2>;
34		};
35	};
36
37	mcu_conf: syscon@40f00000 {
38		compatible = "syscon", "simple-mfd";
39		reg = <0x00 0x40f00000 0x00 0x20000>;
40		#address-cells = <1>;
41		#size-cells = <1>;
42		ranges = <0x00 0x00 0x40f00000 0x20000>;
43
44		phy_gmii_sel: phy@4040 {
45			compatible = "ti,am654-phy-gmii-sel";
46			reg = <0x4040 0x4>;
47			#phy-cells = <1>;
48		};
49	};
50
51	chipid@43000014 {
52		compatible = "ti,am654-chipid";
53		reg = <0x00 0x43000014 0x00 0x4>;
54	};
55
56	wkup_pmx0: pinctrl@4301c000 {
57		compatible = "pinctrl-single";
58		/* Proxy 0 addressing */
59		reg = <0x00 0x4301c000 0x00 0x178>;
60		#pinctrl-cells = <1>;
61		pinctrl-single,register-width = <32>;
62		pinctrl-single,function-mask = <0xffffffff>;
63	};
64
65	mcu_ram: sram@41c00000 {
66		compatible = "mmio-sram";
67		reg = <0x00 0x41c00000 0x00 0x100000>;
68		ranges = <0x00 0x00 0x41c00000 0x100000>;
69		#address-cells = <1>;
70		#size-cells = <1>;
71	};
72
73	wkup_uart0: serial@42300000 {
74		compatible = "ti,j721e-uart", "ti,am654-uart";
75		reg = <0x00 0x42300000 0x00 0x100>;
76		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
77		clock-frequency = <48000000>;
78		current-speed = <115200>;
79		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
80		clocks = <&k3_clks 287 2>;
81		clock-names = "fclk";
82		status = "disabled";
83	};
84
85	mcu_uart0: serial@40a00000 {
86		compatible = "ti,j721e-uart", "ti,am654-uart";
87		reg = <0x00 0x40a00000 0x00 0x100>;
88		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
89		clock-frequency = <96000000>;
90		current-speed = <115200>;
91		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
92		clocks = <&k3_clks 149 2>;
93		clock-names = "fclk";
94		status = "disabled";
95	};
96
97	wkup_gpio_intr: interrupt-controller@42200000 {
98		compatible = "ti,sci-intr";
99		reg = <0x00 0x42200000 0x00 0x400>;
100		ti,intr-trigger-type = <1>;
101		interrupt-controller;
102		interrupt-parent = <&gic500>;
103		#interrupt-cells = <1>;
104		ti,sci = <&dmsc>;
105		ti,sci-dev-id = <137>;
106		ti,interrupt-ranges = <16 960 16>;
107	};
108
109	wkup_gpio0: gpio@42110000 {
110		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
111		reg = <0x00 0x42110000 0x00 0x100>;
112		gpio-controller;
113		#gpio-cells = <2>;
114		interrupt-parent = <&wkup_gpio_intr>;
115		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
116		interrupt-controller;
117		#interrupt-cells = <2>;
118		ti,ngpio = <85>;
119		ti,davinci-gpio-unbanked = <0>;
120		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
121		clocks = <&k3_clks 113 0>;
122		clock-names = "gpio";
123	};
124
125	wkup_gpio1: gpio@42100000 {
126		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
127		reg = <0x00 0x42100000 0x00 0x100>;
128		gpio-controller;
129		#gpio-cells = <2>;
130		interrupt-parent = <&wkup_gpio_intr>;
131		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
132		interrupt-controller;
133		#interrupt-cells = <2>;
134		ti,ngpio = <85>;
135		ti,davinci-gpio-unbanked = <0>;
136		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
137		clocks = <&k3_clks 114 0>;
138		clock-names = "gpio";
139	};
140
141	mcu_navss: bus@28380000 {
142		compatible = "simple-mfd";
143		#address-cells = <2>;
144		#size-cells = <2>;
145		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
146		dma-coherent;
147		dma-ranges;
148		ti,sci-dev-id = <232>;
149
150		mcu_ringacc: ringacc@2b800000 {
151			compatible = "ti,am654-navss-ringacc";
152			reg =	<0x00 0x2b800000 0x00 0x400000>,
153				<0x00 0x2b000000 0x00 0x400000>,
154				<0x00 0x28590000 0x00 0x100>,
155				<0x00 0x2a500000 0x00 0x40000>;
156			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
157			ti,num-rings = <286>;
158			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
159			ti,sci = <&dmsc>;
160			ti,sci-dev-id = <235>;
161			msi-parent = <&main_udmass_inta>;
162		};
163
164		mcu_udmap: dma-controller@285c0000 {
165			compatible = "ti,j721e-navss-mcu-udmap";
166			reg =	<0x00 0x285c0000 0x00 0x100>,
167				<0x00 0x2a800000 0x00 0x40000>,
168				<0x00 0x2aa00000 0x00 0x40000>;
169			reg-names = "gcfg", "rchanrt", "tchanrt";
170			msi-parent = <&main_udmass_inta>;
171			#dma-cells = <1>;
172
173			ti,sci = <&dmsc>;
174			ti,sci-dev-id = <236>;
175			ti,ringacc = <&mcu_ringacc>;
176
177			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
178						<0x0f>; /* TX_HCHAN */
179			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
180						<0x0b>; /* RX_HCHAN */
181			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
182		};
183	};
184
185	mcu_cpsw: ethernet@46000000 {
186		compatible = "ti,j721e-cpsw-nuss";
187		#address-cells = <2>;
188		#size-cells = <2>;
189		reg = <0x00 0x46000000 0x00 0x200000>;
190		reg-names = "cpsw_nuss";
191		ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
192		dma-coherent;
193		clocks = <&k3_clks 18 21>;
194		clock-names = "fck";
195		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
196
197		dmas = <&mcu_udmap 0xf000>,
198		       <&mcu_udmap 0xf001>,
199		       <&mcu_udmap 0xf002>,
200		       <&mcu_udmap 0xf003>,
201		       <&mcu_udmap 0xf004>,
202		       <&mcu_udmap 0xf005>,
203		       <&mcu_udmap 0xf006>,
204		       <&mcu_udmap 0xf007>,
205		       <&mcu_udmap 0x7000>;
206		dma-names = "tx0", "tx1", "tx2", "tx3",
207			    "tx4", "tx5", "tx6", "tx7",
208			    "rx";
209
210		ethernet-ports {
211			#address-cells = <1>;
212			#size-cells = <0>;
213
214			cpsw_port1: port@1 {
215				reg = <1>;
216				ti,mac-only;
217				label = "port1";
218				ti,syscon-efuse = <&mcu_conf 0x200>;
219				phys = <&phy_gmii_sel 1>;
220			};
221		};
222
223		davinci_mdio: mdio@f00 {
224			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
225			reg = <0x00 0xf00 0x00 0x100>;
226			#address-cells = <1>;
227			#size-cells = <0>;
228			clocks = <&k3_clks 18 21>;
229			clock-names = "fck";
230			bus_freq = <1000000>;
231		};
232
233		cpts@3d000 {
234			compatible = "ti,am65-cpts";
235			reg = <0x00 0x3d000 0x00 0x400>;
236			clocks = <&k3_clks 18 2>;
237			clock-names = "cpts";
238			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
239			interrupt-names = "cpts";
240			ti,cpts-ext-ts-inputs = <4>;
241			ti,cpts-periodic-outputs = <2>;
242		};
243	};
244
245	mcu_i2c0: i2c@40b00000 {
246		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
247		reg = <0x00 0x40b00000 0x00 0x100>;
248		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
249		#address-cells = <1>;
250		#size-cells = <0>;
251		clock-names = "fck";
252		clocks = <&k3_clks 194 1>;
253		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
254		status = "disabled";
255	};
256
257	mcu_i2c1: i2c@40b10000 {
258		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
259		reg = <0x00 0x40b10000 0x00 0x100>;
260		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
261		#address-cells = <1>;
262		#size-cells = <0>;
263		clock-names = "fck";
264		clocks = <&k3_clks 195 1>;
265		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
266		status = "disabled";
267	};
268
269	wkup_i2c0: i2c@42120000 {
270		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
271		reg = <0x00 0x42120000 0x00 0x100>;
272		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
273		#address-cells = <1>;
274		#size-cells = <0>;
275		clock-names = "fck";
276		clocks = <&k3_clks 197 1>;
277		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
278		status = "disabled";
279	};
280
281	fss: syscon@47000000 {
282		compatible = "syscon", "simple-mfd";
283		reg = <0x00 0x47000000 0x00 0x100>;
284		#address-cells = <2>;
285		#size-cells = <2>;
286		ranges;
287
288		hbmc_mux: hbmc-mux {
289			compatible = "mmio-mux";
290			#mux-control-cells = <1>;
291			mux-reg-masks = <0x4 0x2>; /* HBMC select */
292		};
293
294		hbmc: hyperbus@47034000 {
295			compatible = "ti,am654-hbmc";
296			reg = <0x00 0x47034000 0x00 0x100>,
297				<0x05 0x00000000 0x01 0x0000000>;
298			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
299			clocks = <&k3_clks 102 0>;
300			assigned-clocks = <&k3_clks 102 5>;
301			assigned-clock-rates = <333333333>;
302			#address-cells = <2>;
303			#size-cells = <1>;
304			mux-controls = <&hbmc_mux 0>;
305		};
306
307		ospi0: spi@47040000 {
308			compatible = "ti,am654-ospi", "cdns,qspi-nor";
309			reg = <0x0 0x47040000 0x0 0x100>,
310			      <0x5 0x00000000 0x1 0x0000000>;
311			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
312			cdns,fifo-depth = <256>;
313			cdns,fifo-width = <4>;
314			cdns,trigger-address = <0x0>;
315			clocks = <&k3_clks 103 0>;
316			assigned-clocks = <&k3_clks 103 0>;
317			assigned-clock-parents = <&k3_clks 103 2>;
318			assigned-clock-rates = <166666666>;
319			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
320			#address-cells = <1>;
321			#size-cells = <0>;
322		};
323	};
324
325	tscadc0: tscadc@40200000 {
326		compatible = "ti,am3359-tscadc";
327		reg = <0x00 0x40200000 0x00 0x1000>;
328		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
329		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
330		clocks = <&k3_clks 0 1>;
331		assigned-clocks = <&k3_clks 0 3>;
332		assigned-clock-rates = <60000000>;
333		clock-names = "fck";
334		dmas = <&main_udmap 0x7400>,
335			<&main_udmap 0x7401>;
336		dma-names = "fifo0", "fifo1";
337
338		adc {
339			#io-channel-cells = <1>;
340			compatible = "ti,am3359-adc";
341		};
342	};
343
344	mcu_r5fss0: r5fss@41000000 {
345		compatible = "ti,j7200-r5fss";
346		ti,cluster-mode = <1>;
347		#address-cells = <1>;
348		#size-cells = <1>;
349		ranges = <0x41000000 0x00 0x41000000 0x20000>,
350			 <0x41400000 0x00 0x41400000 0x20000>;
351		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
352
353		mcu_r5fss0_core0: r5f@41000000 {
354			compatible = "ti,j7200-r5f";
355			reg = <0x41000000 0x00010000>,
356			      <0x41010000 0x00010000>;
357			reg-names = "atcm", "btcm";
358			ti,sci = <&dmsc>;
359			ti,sci-dev-id = <250>;
360			ti,sci-proc-ids = <0x01 0xff>;
361			resets = <&k3_reset 250 1>;
362			firmware-name = "j7200-mcu-r5f0_0-fw";
363			ti,atcm-enable = <1>;
364			ti,btcm-enable = <1>;
365			ti,loczrama = <1>;
366		};
367
368		mcu_r5fss0_core1: r5f@41400000 {
369			compatible = "ti,j7200-r5f";
370			reg = <0x41400000 0x00008000>,
371			      <0x41410000 0x00008000>;
372			reg-names = "atcm", "btcm";
373			ti,sci = <&dmsc>;
374			ti,sci-dev-id = <251>;
375			ti,sci-proc-ids = <0x02 0xff>;
376			resets = <&k3_reset 251 1>;
377			firmware-name = "j7200-mcu-r5f0_1-fw";
378			ti,atcm-enable = <1>;
379			ti,btcm-enable = <1>;
380			ti,loczrama = <1>;
381		};
382	};
383
384	mcu_crypto: crypto@40900000 {
385		compatible = "ti,j721e-sa2ul";
386		reg = <0x00 0x40900000 0x00 0x1200>;
387		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
388		#address-cells = <2>;
389		#size-cells = <2>;
390		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
391		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
392		       <&mcu_udmap 0x7503>;
393		dma-names = "tx", "rx1", "rx2";
394
395		rng: rng@40910000 {
396			compatible = "inside-secure,safexcel-eip76";
397			reg = <0x00 0x40910000 0x00 0x7d>;
398			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
399			status = "disabled"; /* Used by OP-TEE */
400		};
401	};
402};
403