1d361ed88SLokesh Vutla// SPDX-License-Identifier: GPL-2.0
2d361ed88SLokesh Vutla/*
3d361ed88SLokesh Vutla * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
4d361ed88SLokesh Vutla *
5eb6f3655SSuman Anna * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6d361ed88SLokesh Vutla */
7d361ed88SLokesh Vutla
8d361ed88SLokesh Vutla&cbass_mcu_wakeup {
99d3c9378SNishanth Menon	dmsc: system-controller@44083000 {
10d361ed88SLokesh Vutla		compatible = "ti,k2g-sci";
11d361ed88SLokesh Vutla		ti,host-id = <12>;
12d361ed88SLokesh Vutla
13d361ed88SLokesh Vutla		mbox-names = "rx", "tx";
14d361ed88SLokesh Vutla
15d361ed88SLokesh Vutla		mboxes = <&secure_proxy_main 11>,
16d361ed88SLokesh Vutla			 <&secure_proxy_main 13>;
17d361ed88SLokesh Vutla
18d361ed88SLokesh Vutla		reg-names = "debug_messages";
19d361ed88SLokesh Vutla		reg = <0x00 0x44083000 0x00 0x1000>;
20d361ed88SLokesh Vutla
21d361ed88SLokesh Vutla		k3_pds: power-controller {
22d361ed88SLokesh Vutla			compatible = "ti,sci-pm-domain";
23d361ed88SLokesh Vutla			#power-domain-cells = <2>;
24d361ed88SLokesh Vutla		};
25d361ed88SLokesh Vutla
26a0812885SNishanth Menon		k3_clks: clock-controller {
27d361ed88SLokesh Vutla			compatible = "ti,k2g-sci-clk";
28d361ed88SLokesh Vutla			#clock-cells = <2>;
29d361ed88SLokesh Vutla		};
30d361ed88SLokesh Vutla
31d361ed88SLokesh Vutla		k3_reset: reset-controller {
32d361ed88SLokesh Vutla			compatible = "ti,sci-reset";
33d361ed88SLokesh Vutla			#reset-cells = <2>;
34d361ed88SLokesh Vutla		};
35d361ed88SLokesh Vutla	};
36d361ed88SLokesh Vutla
37c8a28ed4SUdit Kumar	mcu_timer0: timer@40400000 {
38c8a28ed4SUdit Kumar		status = "reserved";
39c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
40c8a28ed4SUdit Kumar		reg = <0x00 0x40400000 0x00 0x400>;
41c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
42c8a28ed4SUdit Kumar		clocks = <&k3_clks 35 1>;
43c8a28ed4SUdit Kumar		clock-names = "fck";
44c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 35 1>;
45c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 35 2>;
46c8a28ed4SUdit Kumar		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
47c8a28ed4SUdit Kumar		ti,timer-pwm;
48c8a28ed4SUdit Kumar	};
49c8a28ed4SUdit Kumar
50c8a28ed4SUdit Kumar	mcu_timer1: timer@40410000 {
51c8a28ed4SUdit Kumar		status = "reserved";
52c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
53c8a28ed4SUdit Kumar		reg = <0x00 0x40410000 0x00 0x400>;
54c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
55c8a28ed4SUdit Kumar		clocks = <&k3_clks 71 1>;
56c8a28ed4SUdit Kumar		clock-names = "fck";
57c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
58c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
59c8a28ed4SUdit Kumar		power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
60c8a28ed4SUdit Kumar		ti,timer-pwm;
61c8a28ed4SUdit Kumar	};
62c8a28ed4SUdit Kumar
63c8a28ed4SUdit Kumar	mcu_timer2: timer@40420000 {
64c8a28ed4SUdit Kumar		status = "reserved";
65c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
66c8a28ed4SUdit Kumar		reg = <0x00 0x40420000 0x00 0x400>;
67c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
68c8a28ed4SUdit Kumar		clocks = <&k3_clks 72 1>;
69c8a28ed4SUdit Kumar		clock-names = "fck";
70c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 72 1>;
71c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 72 2>;
72c8a28ed4SUdit Kumar		power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
73c8a28ed4SUdit Kumar		ti,timer-pwm;
74c8a28ed4SUdit Kumar	};
75c8a28ed4SUdit Kumar
76c8a28ed4SUdit Kumar	mcu_timer3: timer@40430000 {
77c8a28ed4SUdit Kumar		status = "reserved";
78c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
79c8a28ed4SUdit Kumar		reg = <0x00 0x40430000 0x00 0x400>;
80c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
81c8a28ed4SUdit Kumar		clocks = <&k3_clks 73 1>;
82c8a28ed4SUdit Kumar		clock-names = "fck";
83c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
84c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
85c8a28ed4SUdit Kumar		power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
86c8a28ed4SUdit Kumar		ti,timer-pwm;
87c8a28ed4SUdit Kumar	};
88c8a28ed4SUdit Kumar
89c8a28ed4SUdit Kumar	mcu_timer4: timer@40440000 {
90c8a28ed4SUdit Kumar		status = "reserved";
91c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
92c8a28ed4SUdit Kumar		reg = <0x00 0x40440000 0x00 0x400>;
93c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
94c8a28ed4SUdit Kumar		clocks = <&k3_clks 74 1>;
95c8a28ed4SUdit Kumar		clock-names = "fck";
96c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 74 1>;
97c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 74 2>;
98c8a28ed4SUdit Kumar		power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
99c8a28ed4SUdit Kumar		ti,timer-pwm;
100c8a28ed4SUdit Kumar	};
101c8a28ed4SUdit Kumar
102c8a28ed4SUdit Kumar	mcu_timer5: timer@40450000 {
103c8a28ed4SUdit Kumar		status = "reserved";
104c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
105c8a28ed4SUdit Kumar		reg = <0x00 0x40450000 0x00 0x400>;
106c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
107c8a28ed4SUdit Kumar		clocks = <&k3_clks 75 1>;
108c8a28ed4SUdit Kumar		clock-names = "fck";
109c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
110c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
111c8a28ed4SUdit Kumar		power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
112c8a28ed4SUdit Kumar		ti,timer-pwm;
113c8a28ed4SUdit Kumar	};
114c8a28ed4SUdit Kumar
115c8a28ed4SUdit Kumar	mcu_timer6: timer@40460000 {
116c8a28ed4SUdit Kumar		status = "reserved";
117c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
118c8a28ed4SUdit Kumar		reg = <0x00 0x40460000 0x00 0x400>;
119c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
120c8a28ed4SUdit Kumar		clocks = <&k3_clks 76 1>;
121c8a28ed4SUdit Kumar		clock-names = "fck";
122c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 76 1>;
123c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 76 2>;
124c8a28ed4SUdit Kumar		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
125c8a28ed4SUdit Kumar		ti,timer-pwm;
126c8a28ed4SUdit Kumar	};
127c8a28ed4SUdit Kumar
128c8a28ed4SUdit Kumar	mcu_timer7: timer@40470000 {
129c8a28ed4SUdit Kumar		status = "reserved";
130c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
131c8a28ed4SUdit Kumar		reg = <0x00 0x40470000 0x00 0x400>;
132c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
133c8a28ed4SUdit Kumar		clocks = <&k3_clks 77 1>;
134c8a28ed4SUdit Kumar		clock-names = "fck";
135c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
136c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
137c8a28ed4SUdit Kumar		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
138c8a28ed4SUdit Kumar		ti,timer-pwm;
139c8a28ed4SUdit Kumar	};
140c8a28ed4SUdit Kumar
141c8a28ed4SUdit Kumar	mcu_timer8: timer@40480000 {
142c8a28ed4SUdit Kumar		status = "reserved";
143c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
144c8a28ed4SUdit Kumar		reg = <0x00 0x40480000 0x00 0x400>;
145c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
146c8a28ed4SUdit Kumar		clocks = <&k3_clks 78 1>;
147c8a28ed4SUdit Kumar		clock-names = "fck";
148c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 78 1>;
149c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 78 2>;
150c8a28ed4SUdit Kumar		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
151c8a28ed4SUdit Kumar		ti,timer-pwm;
152c8a28ed4SUdit Kumar	};
153c8a28ed4SUdit Kumar
154c8a28ed4SUdit Kumar	mcu_timer9: timer@40490000 {
155c8a28ed4SUdit Kumar		status = "reserved";
156c8a28ed4SUdit Kumar		compatible = "ti,am654-timer";
157c8a28ed4SUdit Kumar		reg = <0x00 0x40490000 0x00 0x400>;
158c8a28ed4SUdit Kumar		interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
159c8a28ed4SUdit Kumar		clocks = <&k3_clks 79 1>;
160c8a28ed4SUdit Kumar		clock-names = "fck";
161c8a28ed4SUdit Kumar		assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
162c8a28ed4SUdit Kumar		assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
163c8a28ed4SUdit Kumar		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
164c8a28ed4SUdit Kumar		ti,timer-pwm;
165c8a28ed4SUdit Kumar	};
166c8a28ed4SUdit Kumar
167a323da4bSGrygorii Strashko	mcu_conf: syscon@40f00000 {
168a323da4bSGrygorii Strashko		compatible = "syscon", "simple-mfd";
169a323da4bSGrygorii Strashko		reg = <0x00 0x40f00000 0x00 0x20000>;
170a323da4bSGrygorii Strashko		#address-cells = <1>;
171a323da4bSGrygorii Strashko		#size-cells = <1>;
172a323da4bSGrygorii Strashko		ranges = <0x00 0x00 0x40f00000 0x20000>;
173a323da4bSGrygorii Strashko
174a323da4bSGrygorii Strashko		phy_gmii_sel: phy@4040 {
175a323da4bSGrygorii Strashko			compatible = "ti,am654-phy-gmii-sel";
176a323da4bSGrygorii Strashko			reg = <0x4040 0x4>;
177a323da4bSGrygorii Strashko			#phy-cells = <1>;
178a323da4bSGrygorii Strashko		};
179a323da4bSGrygorii Strashko	};
180a323da4bSGrygorii Strashko
181d361ed88SLokesh Vutla	chipid@43000014 {
182d361ed88SLokesh Vutla		compatible = "ti,am654-chipid";
183d361ed88SLokesh Vutla		reg = <0x00 0x43000014 0x00 0x4>;
184d361ed88SLokesh Vutla	};
185d361ed88SLokesh Vutla
18603612d38SUdit Kumar	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
18703612d38SUdit Kumar	mcu_timerio_input: pinctrl@40f04200 {
18803612d38SUdit Kumar		compatible = "pinctrl-single";
18903612d38SUdit Kumar		reg = <0x0 0x40f04200 0x0 0x28>;
19003612d38SUdit Kumar		#pinctrl-cells = <1>;
19103612d38SUdit Kumar		pinctrl-single,register-width = <32>;
19203612d38SUdit Kumar		pinctrl-single,function-mask = <0x0000000F>;
19303612d38SUdit Kumar		status = "reserved";
19403612d38SUdit Kumar	};
19503612d38SUdit Kumar
19603612d38SUdit Kumar	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
19703612d38SUdit Kumar	mcu_timerio_output: pinctrl@40f04280 {
19803612d38SUdit Kumar		compatible = "pinctrl-single";
19903612d38SUdit Kumar		reg = <0x0 0x40f04280 0x0 0x28>;
20003612d38SUdit Kumar		#pinctrl-cells = <1>;
20103612d38SUdit Kumar		pinctrl-single,register-width = <32>;
20203612d38SUdit Kumar		pinctrl-single,function-mask = <0x0000000F>;
20303612d38SUdit Kumar		status = "reserved";
20403612d38SUdit Kumar	};
20503612d38SUdit Kumar
206d361ed88SLokesh Vutla	wkup_pmx0: pinctrl@4301c000 {
207d361ed88SLokesh Vutla		compatible = "pinctrl-single";
208d361ed88SLokesh Vutla		/* Proxy 0 addressing */
2099ae21ac4SVaishnav Achath		reg = <0x00 0x4301c000 0x00 0x34>;
2109ae21ac4SVaishnav Achath		#pinctrl-cells = <1>;
2119ae21ac4SVaishnav Achath		pinctrl-single,register-width = <32>;
2129ae21ac4SVaishnav Achath		pinctrl-single,function-mask = <0xffffffff>;
2139ae21ac4SVaishnav Achath	};
2149ae21ac4SVaishnav Achath
2154c3cdac1SNishanth Menon	wkup_pmx1: pinctrl@4301c038 {
2169ae21ac4SVaishnav Achath		compatible = "pinctrl-single";
2179ae21ac4SVaishnav Achath		/* Proxy 0 addressing */
2189ae21ac4SVaishnav Achath		reg = <0x00 0x4301c038 0x00 0x8>;
2199ae21ac4SVaishnav Achath		#pinctrl-cells = <1>;
2209ae21ac4SVaishnav Achath		pinctrl-single,register-width = <32>;
2219ae21ac4SVaishnav Achath		pinctrl-single,function-mask = <0xffffffff>;
2229ae21ac4SVaishnav Achath	};
2239ae21ac4SVaishnav Achath
2244c3cdac1SNishanth Menon	wkup_pmx2: pinctrl@4301c068 {
2259ae21ac4SVaishnav Achath		compatible = "pinctrl-single";
2269ae21ac4SVaishnav Achath		/* Proxy 0 addressing */
2279ae21ac4SVaishnav Achath		reg = <0x00 0x4301c068 0x00 0xec>;
2289ae21ac4SVaishnav Achath		#pinctrl-cells = <1>;
2299ae21ac4SVaishnav Achath		pinctrl-single,register-width = <32>;
2309ae21ac4SVaishnav Achath		pinctrl-single,function-mask = <0xffffffff>;
2319ae21ac4SVaishnav Achath	};
2329ae21ac4SVaishnav Achath
2334c3cdac1SNishanth Menon	wkup_pmx3: pinctrl@4301c174 {
2349ae21ac4SVaishnav Achath		compatible = "pinctrl-single";
2359ae21ac4SVaishnav Achath		/* Proxy 0 addressing */
2369ae21ac4SVaishnav Achath		reg = <0x00 0x4301c174 0x00 0x20>;
237d361ed88SLokesh Vutla		#pinctrl-cells = <1>;
238d361ed88SLokesh Vutla		pinctrl-single,register-width = <32>;
239d361ed88SLokesh Vutla		pinctrl-single,function-mask = <0xffffffff>;
240d361ed88SLokesh Vutla	};
241d361ed88SLokesh Vutla
242d361ed88SLokesh Vutla	mcu_ram: sram@41c00000 {
243d361ed88SLokesh Vutla		compatible = "mmio-sram";
244d361ed88SLokesh Vutla		reg = <0x00 0x41c00000 0x00 0x100000>;
245d361ed88SLokesh Vutla		ranges = <0x00 0x00 0x41c00000 0x100000>;
246d361ed88SLokesh Vutla		#address-cells = <1>;
247d361ed88SLokesh Vutla		#size-cells = <1>;
248d361ed88SLokesh Vutla	};
249d361ed88SLokesh Vutla
250d361ed88SLokesh Vutla	wkup_uart0: serial@42300000 {
251d361ed88SLokesh Vutla		compatible = "ti,j721e-uart", "ti,am654-uart";
252d361ed88SLokesh Vutla		reg = <0x00 0x42300000 0x00 0x100>;
253d361ed88SLokesh Vutla		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
254d361ed88SLokesh Vutla		clock-frequency = <48000000>;
255d361ed88SLokesh Vutla		current-speed = <115200>;
256d361ed88SLokesh Vutla		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
257d361ed88SLokesh Vutla		clocks = <&k3_clks 287 2>;
258d361ed88SLokesh Vutla		clock-names = "fclk";
259dae322f8SAndrew Davis		status = "disabled";
260d361ed88SLokesh Vutla	};
261d361ed88SLokesh Vutla
262d361ed88SLokesh Vutla	mcu_uart0: serial@40a00000 {
263d361ed88SLokesh Vutla		compatible = "ti,j721e-uart", "ti,am654-uart";
264d361ed88SLokesh Vutla		reg = <0x00 0x40a00000 0x00 0x100>;
265d361ed88SLokesh Vutla		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
266d361ed88SLokesh Vutla		clock-frequency = <96000000>;
267d361ed88SLokesh Vutla		current-speed = <115200>;
268d361ed88SLokesh Vutla		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
269d361ed88SLokesh Vutla		clocks = <&k3_clks 149 2>;
270d361ed88SLokesh Vutla		clock-names = "fclk";
271dae322f8SAndrew Davis		status = "disabled";
272d361ed88SLokesh Vutla	};
273d361ed88SLokesh Vutla
274cab12badSNishanth Menon	wkup_gpio_intr: interrupt-controller@42200000 {
275d361ed88SLokesh Vutla		compatible = "ti,sci-intr";
276cab12badSNishanth Menon		reg = <0x00 0x42200000 0x00 0x400>;
277d361ed88SLokesh Vutla		ti,intr-trigger-type = <1>;
278d361ed88SLokesh Vutla		interrupt-controller;
279d361ed88SLokesh Vutla		interrupt-parent = <&gic500>;
280d361ed88SLokesh Vutla		#interrupt-cells = <1>;
281d361ed88SLokesh Vutla		ti,sci = <&dmsc>;
282d361ed88SLokesh Vutla		ti,sci-dev-id = <137>;
283d361ed88SLokesh Vutla		ti,interrupt-ranges = <16 960 16>;
284d361ed88SLokesh Vutla	};
28546374264SPeter Ujfalusi
286e0b2e6afSFaiz Abbas	wkup_gpio0: gpio@42110000 {
287e0b2e6afSFaiz Abbas		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
288e0b2e6afSFaiz Abbas		reg = <0x00 0x42110000 0x00 0x100>;
289e0b2e6afSFaiz Abbas		gpio-controller;
290e0b2e6afSFaiz Abbas		#gpio-cells = <2>;
291e0b2e6afSFaiz Abbas		interrupt-parent = <&wkup_gpio_intr>;
292e0b2e6afSFaiz Abbas		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
293e0b2e6afSFaiz Abbas		interrupt-controller;
294e0b2e6afSFaiz Abbas		#interrupt-cells = <2>;
295e0b2e6afSFaiz Abbas		ti,ngpio = <85>;
296e0b2e6afSFaiz Abbas		ti,davinci-gpio-unbanked = <0>;
297e0b2e6afSFaiz Abbas		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
298e0b2e6afSFaiz Abbas		clocks = <&k3_clks 113 0>;
299e0b2e6afSFaiz Abbas		clock-names = "gpio";
300e0b2e6afSFaiz Abbas	};
301e0b2e6afSFaiz Abbas
302e0b2e6afSFaiz Abbas	wkup_gpio1: gpio@42100000 {
303e0b2e6afSFaiz Abbas		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
304e0b2e6afSFaiz Abbas		reg = <0x00 0x42100000 0x00 0x100>;
305e0b2e6afSFaiz Abbas		gpio-controller;
306e0b2e6afSFaiz Abbas		#gpio-cells = <2>;
307e0b2e6afSFaiz Abbas		interrupt-parent = <&wkup_gpio_intr>;
308e0b2e6afSFaiz Abbas		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
309e0b2e6afSFaiz Abbas		interrupt-controller;
310e0b2e6afSFaiz Abbas		#interrupt-cells = <2>;
311e0b2e6afSFaiz Abbas		ti,ngpio = <85>;
312e0b2e6afSFaiz Abbas		ti,davinci-gpio-unbanked = <0>;
313e0b2e6afSFaiz Abbas		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
314e0b2e6afSFaiz Abbas		clocks = <&k3_clks 114 0>;
315e0b2e6afSFaiz Abbas		clock-names = "gpio";
316e0b2e6afSFaiz Abbas	};
317e0b2e6afSFaiz Abbas
31846374264SPeter Ujfalusi	mcu_navss: bus@28380000 {
31946374264SPeter Ujfalusi		compatible = "simple-mfd";
32046374264SPeter Ujfalusi		#address-cells = <2>;
32146374264SPeter Ujfalusi		#size-cells = <2>;
32246374264SPeter Ujfalusi		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
32346374264SPeter Ujfalusi		dma-coherent;
32446374264SPeter Ujfalusi		dma-ranges;
32546374264SPeter Ujfalusi		ti,sci-dev-id = <232>;
32646374264SPeter Ujfalusi
32746374264SPeter Ujfalusi		mcu_ringacc: ringacc@2b800000 {
32846374264SPeter Ujfalusi			compatible = "ti,am654-navss-ringacc";
32946374264SPeter Ujfalusi			reg = <0x00 0x2b800000 0x00 0x400000>,
33046374264SPeter Ujfalusi			      <0x00 0x2b000000 0x00 0x400000>,
33146374264SPeter Ujfalusi			      <0x00 0x28590000 0x00 0x100>,
332*702110c2SVignesh Raghavendra			      <0x00 0x2a500000 0x00 0x40000>,
333*702110c2SVignesh Raghavendra			      <0x00 0x28440000 0x00 0x40000>;
334*702110c2SVignesh Raghavendra			reg-names = "rt", "fifos", "proxy_gcfg",
335*702110c2SVignesh Raghavendra				    "proxy_target", "cfg";
33646374264SPeter Ujfalusi			ti,num-rings = <286>;
33746374264SPeter Ujfalusi			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
33846374264SPeter Ujfalusi			ti,sci = <&dmsc>;
33946374264SPeter Ujfalusi			ti,sci-dev-id = <235>;
34046374264SPeter Ujfalusi			msi-parent = <&main_udmass_inta>;
34146374264SPeter Ujfalusi		};
34246374264SPeter Ujfalusi
34346374264SPeter Ujfalusi		mcu_udmap: dma-controller@285c0000 {
34446374264SPeter Ujfalusi			compatible = "ti,j721e-navss-mcu-udmap";
34546374264SPeter Ujfalusi			reg = <0x00 0x285c0000 0x00 0x100>,
34646374264SPeter Ujfalusi			      <0x00 0x2a800000 0x00 0x40000>,
34746374264SPeter Ujfalusi			      <0x00 0x2aa00000 0x00 0x40000>;
34846374264SPeter Ujfalusi			reg-names = "gcfg", "rchanrt", "tchanrt";
34946374264SPeter Ujfalusi			msi-parent = <&main_udmass_inta>;
35046374264SPeter Ujfalusi			#dma-cells = <1>;
35146374264SPeter Ujfalusi
35246374264SPeter Ujfalusi			ti,sci = <&dmsc>;
35346374264SPeter Ujfalusi			ti,sci-dev-id = <236>;
35446374264SPeter Ujfalusi			ti,ringacc = <&mcu_ringacc>;
35546374264SPeter Ujfalusi
35646374264SPeter Ujfalusi			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
35746374264SPeter Ujfalusi						<0x0f>; /* TX_HCHAN */
35846374264SPeter Ujfalusi			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
35946374264SPeter Ujfalusi						<0x0b>; /* RX_HCHAN */
36046374264SPeter Ujfalusi			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
36146374264SPeter Ujfalusi		};
36246374264SPeter Ujfalusi	};
363a323da4bSGrygorii Strashko
364c4e43f5aSNishanth Menon	secure_proxy_mcu: mailbox@2a480000 {
365c4e43f5aSNishanth Menon		compatible = "ti,am654-secure-proxy";
366c4e43f5aSNishanth Menon		#mbox-cells = <1>;
367c4e43f5aSNishanth Menon		reg-names = "target_data", "rt", "scfg";
368c4e43f5aSNishanth Menon		reg = <0x0 0x2a480000 0x0 0x80000>,
369c4e43f5aSNishanth Menon		      <0x0 0x2a380000 0x0 0x80000>,
370c4e43f5aSNishanth Menon		      <0x0 0x2a400000 0x0 0x80000>;
371c4e43f5aSNishanth Menon		/*
372c4e43f5aSNishanth Menon		 * Marked Disabled:
373c4e43f5aSNishanth Menon		 * Node is incomplete as it is meant for bootloaders and
374c4e43f5aSNishanth Menon		 * firmware on non-MPU processors
375c4e43f5aSNishanth Menon		 */
376c4e43f5aSNishanth Menon		status = "disabled";
377c4e43f5aSNishanth Menon	};
378c4e43f5aSNishanth Menon
379a323da4bSGrygorii Strashko	mcu_cpsw: ethernet@46000000 {
380a323da4bSGrygorii Strashko		compatible = "ti,j721e-cpsw-nuss";
381a323da4bSGrygorii Strashko		#address-cells = <2>;
382a323da4bSGrygorii Strashko		#size-cells = <2>;
383a323da4bSGrygorii Strashko		reg = <0x00 0x46000000 0x00 0x200000>;
384a323da4bSGrygorii Strashko		reg-names = "cpsw_nuss";
385a323da4bSGrygorii Strashko		ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
386a323da4bSGrygorii Strashko		dma-coherent;
387a323da4bSGrygorii Strashko		clocks = <&k3_clks 18 21>;
388a323da4bSGrygorii Strashko		clock-names = "fck";
389a323da4bSGrygorii Strashko		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
390a323da4bSGrygorii Strashko
391a323da4bSGrygorii Strashko		dmas = <&mcu_udmap 0xf000>,
392a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf001>,
393a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf002>,
394a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf003>,
395a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf004>,
396a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf005>,
397a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf006>,
398a323da4bSGrygorii Strashko		       <&mcu_udmap 0xf007>,
399a323da4bSGrygorii Strashko		       <&mcu_udmap 0x7000>;
400a323da4bSGrygorii Strashko		dma-names = "tx0", "tx1", "tx2", "tx3",
401a323da4bSGrygorii Strashko			    "tx4", "tx5", "tx6", "tx7",
402a323da4bSGrygorii Strashko			    "rx";
403a323da4bSGrygorii Strashko
404a323da4bSGrygorii Strashko		ethernet-ports {
405a323da4bSGrygorii Strashko			#address-cells = <1>;
406a323da4bSGrygorii Strashko			#size-cells = <0>;
407a323da4bSGrygorii Strashko
408a323da4bSGrygorii Strashko			cpsw_port1: port@1 {
409a323da4bSGrygorii Strashko				reg = <1>;
410a323da4bSGrygorii Strashko				ti,mac-only;
411a323da4bSGrygorii Strashko				label = "port1";
412a323da4bSGrygorii Strashko				ti,syscon-efuse = <&mcu_conf 0x200>;
413a323da4bSGrygorii Strashko				phys = <&phy_gmii_sel 1>;
414a323da4bSGrygorii Strashko			};
415a323da4bSGrygorii Strashko		};
416a323da4bSGrygorii Strashko
417a323da4bSGrygorii Strashko		davinci_mdio: mdio@f00 {
418a323da4bSGrygorii Strashko			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
419a323da4bSGrygorii Strashko			reg = <0x00 0xf00 0x00 0x100>;
420a323da4bSGrygorii Strashko			#address-cells = <1>;
421a323da4bSGrygorii Strashko			#size-cells = <0>;
422a323da4bSGrygorii Strashko			clocks = <&k3_clks 18 21>;
423a323da4bSGrygorii Strashko			clock-names = "fck";
424a323da4bSGrygorii Strashko			bus_freq = <1000000>;
425a323da4bSGrygorii Strashko		};
426a323da4bSGrygorii Strashko
427a323da4bSGrygorii Strashko		cpts@3d000 {
428a323da4bSGrygorii Strashko			compatible = "ti,am65-cpts";
429a323da4bSGrygorii Strashko			reg = <0x00 0x3d000 0x00 0x400>;
430a323da4bSGrygorii Strashko			clocks = <&k3_clks 18 2>;
431a323da4bSGrygorii Strashko			clock-names = "cpts";
432a323da4bSGrygorii Strashko			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
433a323da4bSGrygorii Strashko			interrupt-names = "cpts";
434a323da4bSGrygorii Strashko			ti,cpts-ext-ts-inputs = <4>;
435a323da4bSGrygorii Strashko			ti,cpts-periodic-outputs = <2>;
436a323da4bSGrygorii Strashko		};
437a323da4bSGrygorii Strashko	};
43803bfeb52SVignesh Raghavendra
43903bfeb52SVignesh Raghavendra	mcu_i2c0: i2c@40b00000 {
44003bfeb52SVignesh Raghavendra		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
44103bfeb52SVignesh Raghavendra		reg = <0x00 0x40b00000 0x00 0x100>;
44203bfeb52SVignesh Raghavendra		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
44303bfeb52SVignesh Raghavendra		#address-cells = <1>;
44403bfeb52SVignesh Raghavendra		#size-cells = <0>;
44503bfeb52SVignesh Raghavendra		clock-names = "fck";
44603bfeb52SVignesh Raghavendra		clocks = <&k3_clks 194 1>;
44703bfeb52SVignesh Raghavendra		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
448a9ed915cSAndrew Davis		status = "disabled";
44903bfeb52SVignesh Raghavendra	};
45003bfeb52SVignesh Raghavendra
45103bfeb52SVignesh Raghavendra	mcu_i2c1: i2c@40b10000 {
45203bfeb52SVignesh Raghavendra		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
45303bfeb52SVignesh Raghavendra		reg = <0x00 0x40b10000 0x00 0x100>;
45403bfeb52SVignesh Raghavendra		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
45503bfeb52SVignesh Raghavendra		#address-cells = <1>;
45603bfeb52SVignesh Raghavendra		#size-cells = <0>;
45703bfeb52SVignesh Raghavendra		clock-names = "fck";
45803bfeb52SVignesh Raghavendra		clocks = <&k3_clks 195 1>;
45903bfeb52SVignesh Raghavendra		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
460a9ed915cSAndrew Davis		status = "disabled";
46103bfeb52SVignesh Raghavendra	};
46203bfeb52SVignesh Raghavendra
46303bfeb52SVignesh Raghavendra	wkup_i2c0: i2c@42120000 {
46403bfeb52SVignesh Raghavendra		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
46503bfeb52SVignesh Raghavendra		reg = <0x00 0x42120000 0x00 0x100>;
46603bfeb52SVignesh Raghavendra		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
46703bfeb52SVignesh Raghavendra		#address-cells = <1>;
46803bfeb52SVignesh Raghavendra		#size-cells = <0>;
46903bfeb52SVignesh Raghavendra		clock-names = "fck";
47003bfeb52SVignesh Raghavendra		clocks = <&k3_clks 197 1>;
47103bfeb52SVignesh Raghavendra		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
472a9ed915cSAndrew Davis		status = "disabled";
47303bfeb52SVignesh Raghavendra	};
4741b772656SVignesh Raghavendra
4758f6c475fSVaishnav Achath	mcu_spi0: spi@40300000 {
4768f6c475fSVaishnav Achath		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
4778f6c475fSVaishnav Achath		reg = <0x00 0x040300000 0x00 0x400>;
4788f6c475fSVaishnav Achath		interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
4798f6c475fSVaishnav Achath		#address-cells = <1>;
4808f6c475fSVaishnav Achath		#size-cells = <0>;
4818f6c475fSVaishnav Achath		power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
4828f6c475fSVaishnav Achath		clocks = <&k3_clks 274 0>;
4838f6c475fSVaishnav Achath		status = "disabled";
4848f6c475fSVaishnav Achath	};
4858f6c475fSVaishnav Achath
4868f6c475fSVaishnav Achath	mcu_spi1: spi@40310000 {
4878f6c475fSVaishnav Achath		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
4888f6c475fSVaishnav Achath		reg = <0x00 0x040310000 0x00 0x400>;
4898f6c475fSVaishnav Achath		interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
4908f6c475fSVaishnav Achath		#address-cells = <1>;
4918f6c475fSVaishnav Achath		#size-cells = <0>;
4928f6c475fSVaishnav Achath		power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
4938f6c475fSVaishnav Achath		clocks = <&k3_clks 275 0>;
4948f6c475fSVaishnav Achath		status = "disabled";
4958f6c475fSVaishnav Achath	};
4968f6c475fSVaishnav Achath
4978f6c475fSVaishnav Achath	mcu_spi2: spi@40320000 {
4988f6c475fSVaishnav Achath		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
4998f6c475fSVaishnav Achath		reg = <0x00 0x040320000 0x00 0x400>;
5008f6c475fSVaishnav Achath		interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
5018f6c475fSVaishnav Achath		#address-cells = <1>;
5028f6c475fSVaishnav Achath		#size-cells = <0>;
5038f6c475fSVaishnav Achath		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
5048f6c475fSVaishnav Achath		clocks = <&k3_clks 276 0>;
5058f6c475fSVaishnav Achath		status = "disabled";
5068f6c475fSVaishnav Achath	};
5078f6c475fSVaishnav Achath
5081b772656SVignesh Raghavendra	fss: syscon@47000000 {
5091b772656SVignesh Raghavendra		compatible = "syscon", "simple-mfd";
5101b772656SVignesh Raghavendra		reg = <0x00 0x47000000 0x00 0x100>;
5111b772656SVignesh Raghavendra		#address-cells = <2>;
5121b772656SVignesh Raghavendra		#size-cells = <2>;
5131b772656SVignesh Raghavendra		ranges;
5141b772656SVignesh Raghavendra
5151b772656SVignesh Raghavendra		hbmc_mux: hbmc-mux {
5161b772656SVignesh Raghavendra			compatible = "mmio-mux";
5171b772656SVignesh Raghavendra			#mux-control-cells = <1>;
5181b772656SVignesh Raghavendra			mux-reg-masks = <0x4 0x2>; /* HBMC select */
5191b772656SVignesh Raghavendra		};
5201b772656SVignesh Raghavendra
5211b772656SVignesh Raghavendra		hbmc: hyperbus@47034000 {
5221b772656SVignesh Raghavendra			compatible = "ti,am654-hbmc";
5231b772656SVignesh Raghavendra			reg = <0x00 0x47034000 0x00 0x100>,
5241b772656SVignesh Raghavendra				<0x05 0x00000000 0x01 0x0000000>;
5251b772656SVignesh Raghavendra			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
5261b772656SVignesh Raghavendra			clocks = <&k3_clks 102 0>;
5271b772656SVignesh Raghavendra			assigned-clocks = <&k3_clks 102 5>;
5281b772656SVignesh Raghavendra			assigned-clock-rates = <333333333>;
5291b772656SVignesh Raghavendra			#address-cells = <2>;
5301b772656SVignesh Raghavendra			#size-cells = <1>;
5311b772656SVignesh Raghavendra			mux-controls = <&hbmc_mux 0>;
5321b772656SVignesh Raghavendra		};
533efbdf2e9SPratyush Yadav
534efbdf2e9SPratyush Yadav		ospi0: spi@47040000 {
5350e941f49SPratyush Yadav			compatible = "ti,am654-ospi", "cdns,qspi-nor";
536efbdf2e9SPratyush Yadav			reg = <0x0 0x47040000 0x0 0x100>,
537efbdf2e9SPratyush Yadav			      <0x5 0x00000000 0x1 0x0000000>;
538efbdf2e9SPratyush Yadav			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
539efbdf2e9SPratyush Yadav			cdns,fifo-depth = <256>;
540efbdf2e9SPratyush Yadav			cdns,fifo-width = <4>;
541efbdf2e9SPratyush Yadav			cdns,trigger-address = <0x0>;
542efbdf2e9SPratyush Yadav			clocks = <&k3_clks 103 0>;
543efbdf2e9SPratyush Yadav			assigned-clocks = <&k3_clks 103 0>;
544efbdf2e9SPratyush Yadav			assigned-clock-parents = <&k3_clks 103 2>;
545efbdf2e9SPratyush Yadav			assigned-clock-rates = <166666666>;
546efbdf2e9SPratyush Yadav			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
547efbdf2e9SPratyush Yadav			#address-cells = <1>;
548efbdf2e9SPratyush Yadav			#size-cells = <0>;
549efbdf2e9SPratyush Yadav		};
5501b772656SVignesh Raghavendra	};
551e6b45168SVignesh Raghavendra
552e6b45168SVignesh Raghavendra	tscadc0: tscadc@40200000 {
553e6b45168SVignesh Raghavendra		compatible = "ti,am3359-tscadc";
554e6b45168SVignesh Raghavendra		reg = <0x00 0x40200000 0x00 0x1000>;
555e6b45168SVignesh Raghavendra		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
556e6b45168SVignesh Raghavendra		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
557e6b45168SVignesh Raghavendra		clocks = <&k3_clks 0 1>;
558e6b45168SVignesh Raghavendra		assigned-clocks = <&k3_clks 0 3>;
559e6b45168SVignesh Raghavendra		assigned-clock-rates = <60000000>;
560e5bad300SMatt Ranostay		clock-names = "fck";
561e6b45168SVignesh Raghavendra		dmas = <&main_udmap 0x7400>,
562e6b45168SVignesh Raghavendra			<&main_udmap 0x7401>;
563e6b45168SVignesh Raghavendra		dma-names = "fifo0", "fifo1";
564e6b45168SVignesh Raghavendra
565e6b45168SVignesh Raghavendra		adc {
566e6b45168SVignesh Raghavendra			#io-channel-cells = <1>;
567e6b45168SVignesh Raghavendra			compatible = "ti,am3359-adc";
568e6b45168SVignesh Raghavendra		};
569e6b45168SVignesh Raghavendra	};
570eb6f3655SSuman Anna
571eb6f3655SSuman Anna	mcu_r5fss0: r5fss@41000000 {
572eb6f3655SSuman Anna		compatible = "ti,j7200-r5fss";
573eb6f3655SSuman Anna		ti,cluster-mode = <1>;
574eb6f3655SSuman Anna		#address-cells = <1>;
575eb6f3655SSuman Anna		#size-cells = <1>;
576eb6f3655SSuman Anna		ranges = <0x41000000 0x00 0x41000000 0x20000>,
577eb6f3655SSuman Anna			 <0x41400000 0x00 0x41400000 0x20000>;
578eb6f3655SSuman Anna		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
579eb6f3655SSuman Anna
580eb6f3655SSuman Anna		mcu_r5fss0_core0: r5f@41000000 {
581eb6f3655SSuman Anna			compatible = "ti,j7200-r5f";
582eb6f3655SSuman Anna			reg = <0x41000000 0x00010000>,
583eb6f3655SSuman Anna			      <0x41010000 0x00010000>;
584eb6f3655SSuman Anna			reg-names = "atcm", "btcm";
585eb6f3655SSuman Anna			ti,sci = <&dmsc>;
586eb6f3655SSuman Anna			ti,sci-dev-id = <250>;
587eb6f3655SSuman Anna			ti,sci-proc-ids = <0x01 0xff>;
588eb6f3655SSuman Anna			resets = <&k3_reset 250 1>;
589eb6f3655SSuman Anna			firmware-name = "j7200-mcu-r5f0_0-fw";
590eb6f3655SSuman Anna			ti,atcm-enable = <1>;
591eb6f3655SSuman Anna			ti,btcm-enable = <1>;
592eb6f3655SSuman Anna			ti,loczrama = <1>;
593eb6f3655SSuman Anna		};
594eb6f3655SSuman Anna
595eb6f3655SSuman Anna		mcu_r5fss0_core1: r5f@41400000 {
596eb6f3655SSuman Anna			compatible = "ti,j7200-r5f";
597eb6f3655SSuman Anna			reg = <0x41400000 0x00008000>,
598eb6f3655SSuman Anna			      <0x41410000 0x00008000>;
599eb6f3655SSuman Anna			reg-names = "atcm", "btcm";
600eb6f3655SSuman Anna			ti,sci = <&dmsc>;
601eb6f3655SSuman Anna			ti,sci-dev-id = <251>;
602eb6f3655SSuman Anna			ti,sci-proc-ids = <0x02 0xff>;
603eb6f3655SSuman Anna			resets = <&k3_reset 251 1>;
604eb6f3655SSuman Anna			firmware-name = "j7200-mcu-r5f0_1-fw";
605eb6f3655SSuman Anna			ti,atcm-enable = <1>;
606eb6f3655SSuman Anna			ti,btcm-enable = <1>;
607eb6f3655SSuman Anna			ti,loczrama = <1>;
608eb6f3655SSuman Anna		};
609eb6f3655SSuman Anna	};
610d683a739SAndrew Davis
611d683a739SAndrew Davis	mcu_crypto: crypto@40900000 {
612d683a739SAndrew Davis		compatible = "ti,j721e-sa2ul";
613d683a739SAndrew Davis		reg = <0x00 0x40900000 0x00 0x1200>;
614d683a739SAndrew Davis		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
615d683a739SAndrew Davis		#address-cells = <2>;
616d683a739SAndrew Davis		#size-cells = <2>;
617d683a739SAndrew Davis		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
618d683a739SAndrew Davis		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
619d683a739SAndrew Davis		       <&mcu_udmap 0x7503>;
620d683a739SAndrew Davis		dma-names = "tx", "rx1", "rx2";
621d683a739SAndrew Davis
622d683a739SAndrew Davis		rng: rng@40910000 {
623d683a739SAndrew Davis			compatible = "inside-secure,safexcel-eip76";
624d683a739SAndrew Davis			reg = <0x00 0x40910000 0x00 0x7d>;
625d683a739SAndrew Davis			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
626d683a739SAndrew Davis			status = "disabled"; /* Used by OP-TEE */
627d683a739SAndrew Davis		};
628d683a739SAndrew Davis	};
6294aa6586aSKeerthy
6304aa6586aSKeerthy	wkup_vtm0: temperature-sensor@42040000 {
6314aa6586aSKeerthy		compatible = "ti,j7200-vtm";
6324aa6586aSKeerthy		reg = <0x00 0x42040000 0x00 0x350>,
6334aa6586aSKeerthy		      <0x00 0x42050000 0x00 0x350>;
6344aa6586aSKeerthy		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
6354aa6586aSKeerthy		#thermal-sensor-cells = <1>;
6364aa6586aSKeerthy	};
637d361ed88SLokesh Vutla};
638