1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 58 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 59 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 60 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 61 62 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 63 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 64 65 gic_its: msi-controller@1820000 { 66 compatible = "arm,gic-v3-its"; 67 reg = <0x00 0x01820000 0x00 0x10000>; 68 socionext,synquacer-pre-its = <0x1000000 0x400000>; 69 msi-controller; 70 #msi-cells = <1>; 71 }; 72 }; 73 74 main_gpio_intr: interrupt-controller@a00000 { 75 compatible = "ti,sci-intr"; 76 reg = <0x00 0x00a00000 0x00 0x800>; 77 ti,intr-trigger-type = <1>; 78 interrupt-controller; 79 interrupt-parent = <&gic500>; 80 #interrupt-cells = <1>; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <131>; 83 ti,interrupt-ranges = <8 392 56>; 84 }; 85 86 main_navss: bus@30000000 { 87 compatible = "simple-mfd"; 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 91 ti,sci-dev-id = <199>; 92 dma-coherent; 93 dma-ranges; 94 95 main_navss_intr: interrupt-controller@310e0000 { 96 compatible = "ti,sci-intr"; 97 reg = <0x00 0x310e0000 0x00 0x4000>; 98 ti,intr-trigger-type = <4>; 99 interrupt-controller; 100 interrupt-parent = <&gic500>; 101 #interrupt-cells = <1>; 102 ti,sci = <&dmsc>; 103 ti,sci-dev-id = <213>; 104 ti,interrupt-ranges = <0 64 64>, 105 <64 448 64>, 106 <128 672 64>; 107 }; 108 109 main_udmass_inta: msi-controller@33d00000 { 110 compatible = "ti,sci-inta"; 111 reg = <0x00 0x33d00000 0x00 0x100000>; 112 interrupt-controller; 113 #interrupt-cells = <0>; 114 interrupt-parent = <&main_navss_intr>; 115 msi-controller; 116 ti,sci = <&dmsc>; 117 ti,sci-dev-id = <209>; 118 ti,interrupt-ranges = <0 0 256>; 119 }; 120 121 secure_proxy_main: mailbox@32c00000 { 122 compatible = "ti,am654-secure-proxy"; 123 #mbox-cells = <1>; 124 reg-names = "target_data", "rt", "scfg"; 125 reg = <0x00 0x32c00000 0x00 0x100000>, 126 <0x00 0x32400000 0x00 0x100000>, 127 <0x00 0x32800000 0x00 0x100000>; 128 interrupt-names = "rx_011"; 129 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 hwspinlock: spinlock@30e00000 { 133 compatible = "ti,am654-hwspinlock"; 134 reg = <0x00 0x30e00000 0x00 0x1000>; 135 #hwlock-cells = <1>; 136 }; 137 138 mailbox0_cluster0: mailbox@31f80000 { 139 compatible = "ti,am654-mailbox"; 140 reg = <0x00 0x31f80000 0x00 0x200>; 141 #mbox-cells = <1>; 142 ti,mbox-num-users = <4>; 143 ti,mbox-num-fifos = <16>; 144 interrupt-parent = <&main_navss_intr>; 145 status = "disabled"; 146 }; 147 148 mailbox0_cluster1: mailbox@31f81000 { 149 compatible = "ti,am654-mailbox"; 150 reg = <0x00 0x31f81000 0x00 0x200>; 151 #mbox-cells = <1>; 152 ti,mbox-num-users = <4>; 153 ti,mbox-num-fifos = <16>; 154 interrupt-parent = <&main_navss_intr>; 155 status = "disabled"; 156 }; 157 158 mailbox0_cluster2: mailbox@31f82000 { 159 compatible = "ti,am654-mailbox"; 160 reg = <0x00 0x31f82000 0x00 0x200>; 161 #mbox-cells = <1>; 162 ti,mbox-num-users = <4>; 163 ti,mbox-num-fifos = <16>; 164 interrupt-parent = <&main_navss_intr>; 165 status = "disabled"; 166 }; 167 168 mailbox0_cluster3: mailbox@31f83000 { 169 compatible = "ti,am654-mailbox"; 170 reg = <0x00 0x31f83000 0x00 0x200>; 171 #mbox-cells = <1>; 172 ti,mbox-num-users = <4>; 173 ti,mbox-num-fifos = <16>; 174 interrupt-parent = <&main_navss_intr>; 175 status = "disabled"; 176 }; 177 178 mailbox0_cluster4: mailbox@31f84000 { 179 compatible = "ti,am654-mailbox"; 180 reg = <0x00 0x31f84000 0x00 0x200>; 181 #mbox-cells = <1>; 182 ti,mbox-num-users = <4>; 183 ti,mbox-num-fifos = <16>; 184 interrupt-parent = <&main_navss_intr>; 185 status = "disabled"; 186 }; 187 188 mailbox0_cluster5: mailbox@31f85000 { 189 compatible = "ti,am654-mailbox"; 190 reg = <0x00 0x31f85000 0x00 0x200>; 191 #mbox-cells = <1>; 192 ti,mbox-num-users = <4>; 193 ti,mbox-num-fifos = <16>; 194 interrupt-parent = <&main_navss_intr>; 195 status = "disabled"; 196 }; 197 198 mailbox0_cluster6: mailbox@31f86000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f86000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 status = "disabled"; 206 }; 207 208 mailbox0_cluster7: mailbox@31f87000 { 209 compatible = "ti,am654-mailbox"; 210 reg = <0x00 0x31f87000 0x00 0x200>; 211 #mbox-cells = <1>; 212 ti,mbox-num-users = <4>; 213 ti,mbox-num-fifos = <16>; 214 interrupt-parent = <&main_navss_intr>; 215 status = "disabled"; 216 }; 217 218 mailbox0_cluster8: mailbox@31f88000 { 219 compatible = "ti,am654-mailbox"; 220 reg = <0x00 0x31f88000 0x00 0x200>; 221 #mbox-cells = <1>; 222 ti,mbox-num-users = <4>; 223 ti,mbox-num-fifos = <16>; 224 interrupt-parent = <&main_navss_intr>; 225 status = "disabled"; 226 }; 227 228 mailbox0_cluster9: mailbox@31f89000 { 229 compatible = "ti,am654-mailbox"; 230 reg = <0x00 0x31f89000 0x00 0x200>; 231 #mbox-cells = <1>; 232 ti,mbox-num-users = <4>; 233 ti,mbox-num-fifos = <16>; 234 interrupt-parent = <&main_navss_intr>; 235 status = "disabled"; 236 }; 237 238 mailbox0_cluster10: mailbox@31f8a000 { 239 compatible = "ti,am654-mailbox"; 240 reg = <0x00 0x31f8a000 0x00 0x200>; 241 #mbox-cells = <1>; 242 ti,mbox-num-users = <4>; 243 ti,mbox-num-fifos = <16>; 244 interrupt-parent = <&main_navss_intr>; 245 status = "disabled"; 246 }; 247 248 mailbox0_cluster11: mailbox@31f8b000 { 249 compatible = "ti,am654-mailbox"; 250 reg = <0x00 0x31f8b000 0x00 0x200>; 251 #mbox-cells = <1>; 252 ti,mbox-num-users = <4>; 253 ti,mbox-num-fifos = <16>; 254 interrupt-parent = <&main_navss_intr>; 255 status = "disabled"; 256 }; 257 258 main_ringacc: ringacc@3c000000 { 259 compatible = "ti,am654-navss-ringacc"; 260 reg = <0x00 0x3c000000 0x00 0x400000>, 261 <0x00 0x38000000 0x00 0x400000>, 262 <0x00 0x31120000 0x00 0x100>, 263 <0x00 0x33000000 0x00 0x40000>; 264 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 265 ti,num-rings = <1024>; 266 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 267 ti,sci = <&dmsc>; 268 ti,sci-dev-id = <211>; 269 msi-parent = <&main_udmass_inta>; 270 }; 271 272 main_udmap: dma-controller@31150000 { 273 compatible = "ti,j721e-navss-main-udmap"; 274 reg = <0x00 0x31150000 0x00 0x100>, 275 <0x00 0x34000000 0x00 0x100000>, 276 <0x00 0x35000000 0x00 0x100000>; 277 reg-names = "gcfg", "rchanrt", "tchanrt"; 278 msi-parent = <&main_udmass_inta>; 279 #dma-cells = <1>; 280 281 ti,sci = <&dmsc>; 282 ti,sci-dev-id = <212>; 283 ti,ringacc = <&main_ringacc>; 284 285 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 286 <0x0f>, /* TX_HCHAN */ 287 <0x10>; /* TX_UHCHAN */ 288 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 289 <0x0b>, /* RX_HCHAN */ 290 <0x0c>; /* RX_UHCHAN */ 291 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 292 }; 293 294 cpts@310d0000 { 295 compatible = "ti,j721e-cpts"; 296 reg = <0x00 0x310d0000 0x00 0x400>; 297 reg-names = "cpts"; 298 clocks = <&k3_clks 201 1>; 299 clock-names = "cpts"; 300 interrupts-extended = <&main_navss_intr 391>; 301 interrupt-names = "cpts"; 302 ti,cpts-periodic-outputs = <6>; 303 ti,cpts-ext-ts-inputs = <8>; 304 }; 305 }; 306 307 main_pmx0: pinctrl@11c000 { 308 compatible = "pinctrl-single"; 309 /* Proxy 0 addressing */ 310 reg = <0x00 0x11c000 0x00 0x10c>; 311 #pinctrl-cells = <1>; 312 pinctrl-single,register-width = <32>; 313 pinctrl-single,function-mask = <0xffffffff>; 314 }; 315 316 main_pmx1: pinctrl@11c11c { 317 compatible = "pinctrl-single"; 318 /* Proxy 0 addressing */ 319 reg = <0x00 0x11c11c 0x00 0xc>; 320 #pinctrl-cells = <1>; 321 pinctrl-single,register-width = <32>; 322 pinctrl-single,function-mask = <0xffffffff>; 323 }; 324 325 main_uart0: serial@2800000 { 326 compatible = "ti,j721e-uart", "ti,am654-uart"; 327 reg = <0x00 0x02800000 0x00 0x100>; 328 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 329 clock-frequency = <48000000>; 330 current-speed = <115200>; 331 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 332 clocks = <&k3_clks 146 2>; 333 clock-names = "fclk"; 334 status = "disabled"; 335 }; 336 337 main_uart1: serial@2810000 { 338 compatible = "ti,j721e-uart", "ti,am654-uart"; 339 reg = <0x00 0x02810000 0x00 0x100>; 340 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 341 clock-frequency = <48000000>; 342 current-speed = <115200>; 343 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 344 clocks = <&k3_clks 278 2>; 345 clock-names = "fclk"; 346 status = "disabled"; 347 }; 348 349 main_uart2: serial@2820000 { 350 compatible = "ti,j721e-uart", "ti,am654-uart"; 351 reg = <0x00 0x02820000 0x00 0x100>; 352 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 353 clock-frequency = <48000000>; 354 current-speed = <115200>; 355 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 279 2>; 357 clock-names = "fclk"; 358 status = "disabled"; 359 }; 360 361 main_uart3: serial@2830000 { 362 compatible = "ti,j721e-uart", "ti,am654-uart"; 363 reg = <0x00 0x02830000 0x00 0x100>; 364 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 365 clock-frequency = <48000000>; 366 current-speed = <115200>; 367 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 368 clocks = <&k3_clks 280 2>; 369 clock-names = "fclk"; 370 status = "disabled"; 371 }; 372 373 main_uart4: serial@2840000 { 374 compatible = "ti,j721e-uart", "ti,am654-uart"; 375 reg = <0x00 0x02840000 0x00 0x100>; 376 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 377 clock-frequency = <48000000>; 378 current-speed = <115200>; 379 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 380 clocks = <&k3_clks 281 2>; 381 clock-names = "fclk"; 382 status = "disabled"; 383 }; 384 385 main_uart5: serial@2850000 { 386 compatible = "ti,j721e-uart", "ti,am654-uart"; 387 reg = <0x00 0x02850000 0x00 0x100>; 388 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 389 clock-frequency = <48000000>; 390 current-speed = <115200>; 391 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 392 clocks = <&k3_clks 282 2>; 393 clock-names = "fclk"; 394 status = "disabled"; 395 }; 396 397 main_uart6: serial@2860000 { 398 compatible = "ti,j721e-uart", "ti,am654-uart"; 399 reg = <0x00 0x02860000 0x00 0x100>; 400 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 401 clock-frequency = <48000000>; 402 current-speed = <115200>; 403 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 404 clocks = <&k3_clks 283 2>; 405 clock-names = "fclk"; 406 status = "disabled"; 407 }; 408 409 main_uart7: serial@2870000 { 410 compatible = "ti,j721e-uart", "ti,am654-uart"; 411 reg = <0x00 0x02870000 0x00 0x100>; 412 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 413 clock-frequency = <48000000>; 414 current-speed = <115200>; 415 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 284 2>; 417 clock-names = "fclk"; 418 status = "disabled"; 419 }; 420 421 main_uart8: serial@2880000 { 422 compatible = "ti,j721e-uart", "ti,am654-uart"; 423 reg = <0x00 0x02880000 0x00 0x100>; 424 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 425 clock-frequency = <48000000>; 426 current-speed = <115200>; 427 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 428 clocks = <&k3_clks 285 2>; 429 clock-names = "fclk"; 430 status = "disabled"; 431 }; 432 433 main_uart9: serial@2890000 { 434 compatible = "ti,j721e-uart", "ti,am654-uart"; 435 reg = <0x00 0x02890000 0x00 0x100>; 436 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 437 clock-frequency = <48000000>; 438 current-speed = <115200>; 439 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 440 clocks = <&k3_clks 286 2>; 441 clock-names = "fclk"; 442 status = "disabled"; 443 }; 444 445 main_i2c0: i2c@2000000 { 446 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 447 reg = <0x00 0x2000000 0x00 0x100>; 448 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 clock-names = "fck"; 452 clocks = <&k3_clks 187 1>; 453 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 454 status = "disabled"; 455 }; 456 457 main_i2c1: i2c@2010000 { 458 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 459 reg = <0x00 0x2010000 0x00 0x100>; 460 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 clock-names = "fck"; 464 clocks = <&k3_clks 188 1>; 465 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 466 status = "disabled"; 467 }; 468 469 main_i2c2: i2c@2020000 { 470 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 471 reg = <0x00 0x2020000 0x00 0x100>; 472 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clock-names = "fck"; 476 clocks = <&k3_clks 189 1>; 477 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 478 status = "disabled"; 479 }; 480 481 main_i2c3: i2c@2030000 { 482 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 483 reg = <0x00 0x2030000 0x00 0x100>; 484 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clock-names = "fck"; 488 clocks = <&k3_clks 190 1>; 489 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 490 status = "disabled"; 491 }; 492 493 main_i2c4: i2c@2040000 { 494 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 495 reg = <0x00 0x2040000 0x00 0x100>; 496 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 clock-names = "fck"; 500 clocks = <&k3_clks 191 1>; 501 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 502 status = "disabled"; 503 }; 504 505 main_i2c5: i2c@2050000 { 506 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 507 reg = <0x00 0x2050000 0x00 0x100>; 508 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 clock-names = "fck"; 512 clocks = <&k3_clks 192 1>; 513 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 514 status = "disabled"; 515 }; 516 517 main_i2c6: i2c@2060000 { 518 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 519 reg = <0x00 0x2060000 0x00 0x100>; 520 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 clock-names = "fck"; 524 clocks = <&k3_clks 193 1>; 525 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 526 status = "disabled"; 527 }; 528 529 main_sdhci0: mmc@4f80000 { 530 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 531 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 532 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 533 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 534 clock-names = "clk_ahb", "clk_xin"; 535 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 536 ti,otap-del-sel-legacy = <0x0>; 537 ti,otap-del-sel-mmc-hs = <0x0>; 538 ti,otap-del-sel-ddr52 = <0x6>; 539 ti,otap-del-sel-hs200 = <0x8>; 540 ti,otap-del-sel-hs400 = <0x5>; 541 ti,itap-del-sel-legacy = <0x10>; 542 ti,itap-del-sel-mmc-hs = <0xa>; 543 ti,strobe-sel = <0x77>; 544 ti,clkbuf-sel = <0x7>; 545 ti,trm-icp = <0x8>; 546 bus-width = <8>; 547 mmc-ddr-1_8v; 548 mmc-hs200-1_8v; 549 mmc-hs400-1_8v; 550 dma-coherent; 551 }; 552 553 main_sdhci1: mmc@4fb0000 { 554 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 555 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 556 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 557 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 558 clock-names = "clk_ahb", "clk_xin"; 559 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 560 ti,otap-del-sel-legacy = <0x0>; 561 ti,otap-del-sel-sd-hs = <0x0>; 562 ti,otap-del-sel-sdr12 = <0xf>; 563 ti,otap-del-sel-sdr25 = <0xf>; 564 ti,otap-del-sel-sdr50 = <0xc>; 565 ti,otap-del-sel-sdr104 = <0x5>; 566 ti,otap-del-sel-ddr50 = <0xc>; 567 ti,itap-del-sel-legacy = <0x0>; 568 ti,itap-del-sel-sd-hs = <0x0>; 569 ti,itap-del-sel-sdr12 = <0x0>; 570 ti,itap-del-sel-sdr25 = <0x0>; 571 ti,clkbuf-sel = <0x7>; 572 ti,trm-icp = <0x8>; 573 dma-coherent; 574 }; 575 576 serdes_wiz0: wiz@5060000 { 577 compatible = "ti,j721e-wiz-10g"; 578 #address-cells = <1>; 579 #size-cells = <1>; 580 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 581 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 582 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 583 num-lanes = <4>; 584 #reset-cells = <1>; 585 ranges = <0x5060000 0x0 0x5060000 0x10000>; 586 587 assigned-clocks = <&k3_clks 292 85>; 588 assigned-clock-parents = <&k3_clks 292 89>; 589 590 wiz0_pll0_refclk: pll0-refclk { 591 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 592 clock-output-names = "wiz0_pll0_refclk"; 593 #clock-cells = <0>; 594 assigned-clocks = <&wiz0_pll0_refclk>; 595 assigned-clock-parents = <&k3_clks 292 85>; 596 }; 597 598 wiz0_pll1_refclk: pll1-refclk { 599 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 600 clock-output-names = "wiz0_pll1_refclk"; 601 #clock-cells = <0>; 602 assigned-clocks = <&wiz0_pll1_refclk>; 603 assigned-clock-parents = <&k3_clks 292 85>; 604 }; 605 606 wiz0_refclk_dig: refclk-dig { 607 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 608 clock-output-names = "wiz0_refclk_dig"; 609 #clock-cells = <0>; 610 assigned-clocks = <&wiz0_refclk_dig>; 611 assigned-clock-parents = <&k3_clks 292 85>; 612 }; 613 614 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 615 clocks = <&wiz0_refclk_dig>; 616 #clock-cells = <0>; 617 }; 618 619 serdes0: serdes@5060000 { 620 compatible = "ti,j721e-serdes-10g"; 621 reg = <0x05060000 0x00010000>; 622 reg-names = "torrent_phy"; 623 resets = <&serdes_wiz0 0>; 624 reset-names = "torrent_reset"; 625 clocks = <&wiz0_pll0_refclk>; 626 clock-names = "refclk"; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 }; 630 }; 631 632 pcie1_rc: pcie@2910000 { 633 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 634 reg = <0x00 0x02910000 0x00 0x1000>, 635 <0x00 0x02917000 0x00 0x400>, 636 <0x00 0x0d800000 0x00 0x00800000>, 637 <0x00 0x18000000 0x00 0x00001000>; 638 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 639 interrupt-names = "link_state"; 640 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 641 device_type = "pci"; 642 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 643 max-link-speed = <3>; 644 num-lanes = <4>; 645 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 646 clocks = <&k3_clks 240 6>; 647 clock-names = "fck"; 648 #address-cells = <3>; 649 #size-cells = <2>; 650 bus-range = <0x0 0xff>; 651 cdns,no-bar-match-nbits = <64>; 652 vendor-id = <0x104c>; 653 device-id = <0xb00f>; 654 msi-map = <0x0 &gic_its 0x0 0x10000>; 655 dma-coherent; 656 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 657 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 658 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 659 }; 660 661 pcie1_ep: pcie-ep@2910000 { 662 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 663 reg = <0x00 0x02910000 0x00 0x1000>, 664 <0x00 0x02917000 0x00 0x400>, 665 <0x00 0x0d800000 0x00 0x00800000>, 666 <0x00 0x18000000 0x00 0x08000000>; 667 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 668 interrupt-names = "link_state"; 669 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 670 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 671 max-link-speed = <3>; 672 num-lanes = <4>; 673 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 674 clocks = <&k3_clks 240 6>; 675 clock-names = "fck"; 676 max-functions = /bits/ 8 <6>; 677 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 678 dma-coherent; 679 }; 680 681 usbss0: cdns-usb@4104000 { 682 compatible = "ti,j721e-usb"; 683 reg = <0x00 0x4104000 0x00 0x100>; 684 dma-coherent; 685 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 686 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 687 clock-names = "ref", "lpm"; 688 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 689 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 690 #address-cells = <2>; 691 #size-cells = <2>; 692 ranges; 693 694 usb0: usb@6000000 { 695 compatible = "cdns,usb3"; 696 reg = <0x00 0x6000000 0x00 0x10000>, 697 <0x00 0x6010000 0x00 0x10000>, 698 <0x00 0x6020000 0x00 0x10000>; 699 reg-names = "otg", "xhci", "dev"; 700 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 701 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 702 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 703 interrupt-names = "host", 704 "peripheral", 705 "otg"; 706 maximum-speed = "super-speed"; 707 dr_mode = "otg"; 708 cdns,phyrst-a-enable; 709 }; 710 }; 711 712 main_gpio0: gpio@600000 { 713 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 714 reg = <0x00 0x00600000 0x00 0x100>; 715 gpio-controller; 716 #gpio-cells = <2>; 717 interrupt-parent = <&main_gpio_intr>; 718 interrupts = <145>, <146>, <147>, <148>, 719 <149>; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 ti,ngpio = <69>; 723 ti,davinci-gpio-unbanked = <0>; 724 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 725 clocks = <&k3_clks 105 0>; 726 clock-names = "gpio"; 727 }; 728 729 main_gpio2: gpio@610000 { 730 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 731 reg = <0x00 0x00610000 0x00 0x100>; 732 gpio-controller; 733 #gpio-cells = <2>; 734 interrupt-parent = <&main_gpio_intr>; 735 interrupts = <154>, <155>, <156>, <157>, 736 <158>; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 ti,ngpio = <69>; 740 ti,davinci-gpio-unbanked = <0>; 741 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 742 clocks = <&k3_clks 107 0>; 743 clock-names = "gpio"; 744 }; 745 746 main_gpio4: gpio@620000 { 747 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 748 reg = <0x00 0x00620000 0x00 0x100>; 749 gpio-controller; 750 #gpio-cells = <2>; 751 interrupt-parent = <&main_gpio_intr>; 752 interrupts = <163>, <164>, <165>, <166>, 753 <167>; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 ti,ngpio = <69>; 757 ti,davinci-gpio-unbanked = <0>; 758 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 759 clocks = <&k3_clks 109 0>; 760 clock-names = "gpio"; 761 }; 762 763 main_gpio6: gpio@630000 { 764 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 765 reg = <0x00 0x00630000 0x00 0x100>; 766 gpio-controller; 767 #gpio-cells = <2>; 768 interrupt-parent = <&main_gpio_intr>; 769 interrupts = <172>, <173>, <174>, <175>, 770 <176>; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 ti,ngpio = <69>; 774 ti,davinci-gpio-unbanked = <0>; 775 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 776 clocks = <&k3_clks 111 0>; 777 clock-names = "gpio"; 778 }; 779 780 watchdog0: watchdog@2200000 { 781 compatible = "ti,j7-rti-wdt"; 782 reg = <0x0 0x2200000 0x0 0x100>; 783 clocks = <&k3_clks 252 1>; 784 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 785 assigned-clocks = <&k3_clks 252 1>; 786 assigned-clock-parents = <&k3_clks 252 5>; 787 }; 788 789 watchdog1: watchdog@2210000 { 790 compatible = "ti,j7-rti-wdt"; 791 reg = <0x0 0x2210000 0x0 0x100>; 792 clocks = <&k3_clks 253 1>; 793 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 794 assigned-clocks = <&k3_clks 253 1>; 795 assigned-clock-parents = <&k3_clks 253 5>; 796 }; 797 798 main_r5fss0: r5fss@5c00000 { 799 compatible = "ti,j7200-r5fss"; 800 ti,cluster-mode = <1>; 801 #address-cells = <1>; 802 #size-cells = <1>; 803 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 804 <0x5d00000 0x00 0x5d00000 0x20000>; 805 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 806 807 main_r5fss0_core0: r5f@5c00000 { 808 compatible = "ti,j7200-r5f"; 809 reg = <0x5c00000 0x00010000>, 810 <0x5c10000 0x00010000>; 811 reg-names = "atcm", "btcm"; 812 ti,sci = <&dmsc>; 813 ti,sci-dev-id = <245>; 814 ti,sci-proc-ids = <0x06 0xff>; 815 resets = <&k3_reset 245 1>; 816 firmware-name = "j7200-main-r5f0_0-fw"; 817 ti,atcm-enable = <1>; 818 ti,btcm-enable = <1>; 819 ti,loczrama = <1>; 820 }; 821 822 main_r5fss0_core1: r5f@5d00000 { 823 compatible = "ti,j7200-r5f"; 824 reg = <0x5d00000 0x00008000>, 825 <0x5d10000 0x00008000>; 826 reg-names = "atcm", "btcm"; 827 ti,sci = <&dmsc>; 828 ti,sci-dev-id = <246>; 829 ti,sci-proc-ids = <0x07 0xff>; 830 resets = <&k3_reset 246 1>; 831 firmware-name = "j7200-main-r5f0_1-fw"; 832 ti,atcm-enable = <1>; 833 ti,btcm-enable = <1>; 834 ti,loczrama = <1>; 835 }; 836 }; 837}; 838