1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 58 59 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 60 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 61 62 gic_its: msi-controller@1820000 { 63 compatible = "arm,gic-v3-its"; 64 reg = <0x00 0x01820000 0x00 0x10000>; 65 socionext,synquacer-pre-its = <0x1000000 0x400000>; 66 msi-controller; 67 #msi-cells = <1>; 68 }; 69 }; 70 71 main_gpio_intr: interrupt-controller0 { 72 compatible = "ti,sci-intr"; 73 ti,intr-trigger-type = <1>; 74 interrupt-controller; 75 interrupt-parent = <&gic500>; 76 #interrupt-cells = <1>; 77 ti,sci = <&dmsc>; 78 ti,sci-dev-id = <131>; 79 ti,interrupt-ranges = <8 392 56>; 80 }; 81 82 main_navss: bus@30000000 { 83 compatible = "simple-mfd"; 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 87 ti,sci-dev-id = <199>; 88 89 main_navss_intr: interrupt-controller1 { 90 compatible = "ti,sci-intr"; 91 ti,intr-trigger-type = <4>; 92 interrupt-controller; 93 interrupt-parent = <&gic500>; 94 #interrupt-cells = <1>; 95 ti,sci = <&dmsc>; 96 ti,sci-dev-id = <213>; 97 ti,interrupt-ranges = <0 64 64>, 98 <64 448 64>, 99 <128 672 64>; 100 }; 101 102 main_udmass_inta: msi-controller@33d00000 { 103 compatible = "ti,sci-inta"; 104 reg = <0x00 0x33d00000 0x00 0x100000>; 105 interrupt-controller; 106 #interrupt-cells = <0>; 107 interrupt-parent = <&main_navss_intr>; 108 msi-controller; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <209>; 111 ti,interrupt-ranges = <0 0 256>; 112 }; 113 114 secure_proxy_main: mailbox@32c00000 { 115 compatible = "ti,am654-secure-proxy"; 116 #mbox-cells = <1>; 117 reg-names = "target_data", "rt", "scfg"; 118 reg = <0x00 0x32c00000 0x00 0x100000>, 119 <0x00 0x32400000 0x00 0x100000>, 120 <0x00 0x32800000 0x00 0x100000>; 121 interrupt-names = "rx_011"; 122 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 123 }; 124 125 hwspinlock: spinlock@30e00000 { 126 compatible = "ti,am654-hwspinlock"; 127 reg = <0x00 0x30e00000 0x00 0x1000>; 128 #hwlock-cells = <1>; 129 }; 130 131 mailbox0_cluster0: mailbox@31f80000 { 132 compatible = "ti,am654-mailbox"; 133 reg = <0x00 0x31f80000 0x00 0x200>; 134 #mbox-cells = <1>; 135 ti,mbox-num-users = <4>; 136 ti,mbox-num-fifos = <16>; 137 interrupt-parent = <&main_navss_intr>; 138 }; 139 140 mailbox0_cluster1: mailbox@31f81000 { 141 compatible = "ti,am654-mailbox"; 142 reg = <0x00 0x31f81000 0x00 0x200>; 143 #mbox-cells = <1>; 144 ti,mbox-num-users = <4>; 145 ti,mbox-num-fifos = <16>; 146 interrupt-parent = <&main_navss_intr>; 147 }; 148 149 mailbox0_cluster2: mailbox@31f82000 { 150 compatible = "ti,am654-mailbox"; 151 reg = <0x00 0x31f82000 0x00 0x200>; 152 #mbox-cells = <1>; 153 ti,mbox-num-users = <4>; 154 ti,mbox-num-fifos = <16>; 155 interrupt-parent = <&main_navss_intr>; 156 }; 157 158 mailbox0_cluster3: mailbox@31f83000 { 159 compatible = "ti,am654-mailbox"; 160 reg = <0x00 0x31f83000 0x00 0x200>; 161 #mbox-cells = <1>; 162 ti,mbox-num-users = <4>; 163 ti,mbox-num-fifos = <16>; 164 interrupt-parent = <&main_navss_intr>; 165 }; 166 167 mailbox0_cluster4: mailbox@31f84000 { 168 compatible = "ti,am654-mailbox"; 169 reg = <0x00 0x31f84000 0x00 0x200>; 170 #mbox-cells = <1>; 171 ti,mbox-num-users = <4>; 172 ti,mbox-num-fifos = <16>; 173 interrupt-parent = <&main_navss_intr>; 174 }; 175 176 mailbox0_cluster5: mailbox@31f85000 { 177 compatible = "ti,am654-mailbox"; 178 reg = <0x00 0x31f85000 0x00 0x200>; 179 #mbox-cells = <1>; 180 ti,mbox-num-users = <4>; 181 ti,mbox-num-fifos = <16>; 182 interrupt-parent = <&main_navss_intr>; 183 }; 184 185 mailbox0_cluster6: mailbox@31f86000 { 186 compatible = "ti,am654-mailbox"; 187 reg = <0x00 0x31f86000 0x00 0x200>; 188 #mbox-cells = <1>; 189 ti,mbox-num-users = <4>; 190 ti,mbox-num-fifos = <16>; 191 interrupt-parent = <&main_navss_intr>; 192 }; 193 194 mailbox0_cluster7: mailbox@31f87000 { 195 compatible = "ti,am654-mailbox"; 196 reg = <0x00 0x31f87000 0x00 0x200>; 197 #mbox-cells = <1>; 198 ti,mbox-num-users = <4>; 199 ti,mbox-num-fifos = <16>; 200 interrupt-parent = <&main_navss_intr>; 201 }; 202 203 mailbox0_cluster8: mailbox@31f88000 { 204 compatible = "ti,am654-mailbox"; 205 reg = <0x00 0x31f88000 0x00 0x200>; 206 #mbox-cells = <1>; 207 ti,mbox-num-users = <4>; 208 ti,mbox-num-fifos = <16>; 209 interrupt-parent = <&main_navss_intr>; 210 }; 211 212 mailbox0_cluster9: mailbox@31f89000 { 213 compatible = "ti,am654-mailbox"; 214 reg = <0x00 0x31f89000 0x00 0x200>; 215 #mbox-cells = <1>; 216 ti,mbox-num-users = <4>; 217 ti,mbox-num-fifos = <16>; 218 interrupt-parent = <&main_navss_intr>; 219 }; 220 221 mailbox0_cluster10: mailbox@31f8a000 { 222 compatible = "ti,am654-mailbox"; 223 reg = <0x00 0x31f8a000 0x00 0x200>; 224 #mbox-cells = <1>; 225 ti,mbox-num-users = <4>; 226 ti,mbox-num-fifos = <16>; 227 interrupt-parent = <&main_navss_intr>; 228 }; 229 230 mailbox0_cluster11: mailbox@31f8b000 { 231 compatible = "ti,am654-mailbox"; 232 reg = <0x00 0x31f8b000 0x00 0x200>; 233 #mbox-cells = <1>; 234 ti,mbox-num-users = <4>; 235 ti,mbox-num-fifos = <16>; 236 interrupt-parent = <&main_navss_intr>; 237 }; 238 239 main_ringacc: ringacc@3c000000 { 240 compatible = "ti,am654-navss-ringacc"; 241 reg = <0x00 0x3c000000 0x00 0x400000>, 242 <0x00 0x38000000 0x00 0x400000>, 243 <0x00 0x31120000 0x00 0x100>, 244 <0x00 0x33000000 0x00 0x40000>; 245 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 246 ti,num-rings = <1024>; 247 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 248 ti,sci = <&dmsc>; 249 ti,sci-dev-id = <211>; 250 msi-parent = <&main_udmass_inta>; 251 }; 252 253 main_udmap: dma-controller@31150000 { 254 compatible = "ti,j721e-navss-main-udmap"; 255 reg = <0x00 0x31150000 0x00 0x100>, 256 <0x00 0x34000000 0x00 0x100000>, 257 <0x00 0x35000000 0x00 0x100000>; 258 reg-names = "gcfg", "rchanrt", "tchanrt"; 259 msi-parent = <&main_udmass_inta>; 260 #dma-cells = <1>; 261 262 ti,sci = <&dmsc>; 263 ti,sci-dev-id = <212>; 264 ti,ringacc = <&main_ringacc>; 265 266 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 267 <0x0f>, /* TX_HCHAN */ 268 <0x10>; /* TX_UHCHAN */ 269 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 270 <0x0b>, /* RX_HCHAN */ 271 <0x0c>; /* RX_UHCHAN */ 272 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 273 }; 274 275 cpts@310d0000 { 276 compatible = "ti,j721e-cpts"; 277 reg = <0x00 0x310d0000 0x00 0x400>; 278 reg-names = "cpts"; 279 clocks = <&k3_clks 201 1>; 280 clock-names = "cpts"; 281 interrupts-extended = <&main_navss_intr 391>; 282 interrupt-names = "cpts"; 283 ti,cpts-periodic-outputs = <6>; 284 ti,cpts-ext-ts-inputs = <8>; 285 }; 286 }; 287 288 main_pmx0: pinctrl@11c000 { 289 compatible = "pinctrl-single"; 290 /* Proxy 0 addressing */ 291 reg = <0x00 0x11c000 0x00 0x2b4>; 292 #pinctrl-cells = <1>; 293 pinctrl-single,register-width = <32>; 294 pinctrl-single,function-mask = <0xffffffff>; 295 }; 296 297 main_uart0: serial@2800000 { 298 compatible = "ti,j721e-uart", "ti,am654-uart"; 299 reg = <0x00 0x02800000 0x00 0x100>; 300 reg-shift = <2>; 301 reg-io-width = <4>; 302 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 303 clock-frequency = <48000000>; 304 current-speed = <115200>; 305 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 306 clocks = <&k3_clks 146 2>; 307 clock-names = "fclk"; 308 }; 309 310 main_uart1: serial@2810000 { 311 compatible = "ti,j721e-uart", "ti,am654-uart"; 312 reg = <0x00 0x02810000 0x00 0x100>; 313 reg-shift = <2>; 314 reg-io-width = <4>; 315 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 316 clock-frequency = <48000000>; 317 current-speed = <115200>; 318 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 319 clocks = <&k3_clks 278 2>; 320 clock-names = "fclk"; 321 }; 322 323 main_uart2: serial@2820000 { 324 compatible = "ti,j721e-uart", "ti,am654-uart"; 325 reg = <0x00 0x02820000 0x00 0x100>; 326 reg-shift = <2>; 327 reg-io-width = <4>; 328 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 329 clock-frequency = <48000000>; 330 current-speed = <115200>; 331 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 332 clocks = <&k3_clks 279 2>; 333 clock-names = "fclk"; 334 }; 335 336 main_uart3: serial@2830000 { 337 compatible = "ti,j721e-uart", "ti,am654-uart"; 338 reg = <0x00 0x02830000 0x00 0x100>; 339 reg-shift = <2>; 340 reg-io-width = <4>; 341 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 342 clock-frequency = <48000000>; 343 current-speed = <115200>; 344 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 345 clocks = <&k3_clks 280 2>; 346 clock-names = "fclk"; 347 }; 348 349 main_uart4: serial@2840000 { 350 compatible = "ti,j721e-uart", "ti,am654-uart"; 351 reg = <0x00 0x02840000 0x00 0x100>; 352 reg-shift = <2>; 353 reg-io-width = <4>; 354 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 355 clock-frequency = <48000000>; 356 current-speed = <115200>; 357 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 358 clocks = <&k3_clks 281 2>; 359 clock-names = "fclk"; 360 }; 361 362 main_uart5: serial@2850000 { 363 compatible = "ti,j721e-uart", "ti,am654-uart"; 364 reg = <0x00 0x02850000 0x00 0x100>; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 368 clock-frequency = <48000000>; 369 current-speed = <115200>; 370 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 371 clocks = <&k3_clks 282 2>; 372 clock-names = "fclk"; 373 }; 374 375 main_uart6: serial@2860000 { 376 compatible = "ti,j721e-uart", "ti,am654-uart"; 377 reg = <0x00 0x02860000 0x00 0x100>; 378 reg-shift = <2>; 379 reg-io-width = <4>; 380 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 381 clock-frequency = <48000000>; 382 current-speed = <115200>; 383 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 384 clocks = <&k3_clks 283 2>; 385 clock-names = "fclk"; 386 }; 387 388 main_uart7: serial@2870000 { 389 compatible = "ti,j721e-uart", "ti,am654-uart"; 390 reg = <0x00 0x02870000 0x00 0x100>; 391 reg-shift = <2>; 392 reg-io-width = <4>; 393 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 394 clock-frequency = <48000000>; 395 current-speed = <115200>; 396 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 397 clocks = <&k3_clks 284 2>; 398 clock-names = "fclk"; 399 }; 400 401 main_uart8: serial@2880000 { 402 compatible = "ti,j721e-uart", "ti,am654-uart"; 403 reg = <0x00 0x02880000 0x00 0x100>; 404 reg-shift = <2>; 405 reg-io-width = <4>; 406 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 407 clock-frequency = <48000000>; 408 current-speed = <115200>; 409 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 410 clocks = <&k3_clks 285 2>; 411 clock-names = "fclk"; 412 }; 413 414 main_uart9: serial@2890000 { 415 compatible = "ti,j721e-uart", "ti,am654-uart"; 416 reg = <0x00 0x02890000 0x00 0x100>; 417 reg-shift = <2>; 418 reg-io-width = <4>; 419 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 420 clock-frequency = <48000000>; 421 current-speed = <115200>; 422 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 286 2>; 424 clock-names = "fclk"; 425 }; 426 427 main_i2c0: i2c@2000000 { 428 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 429 reg = <0x00 0x2000000 0x00 0x100>; 430 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 clock-names = "fck"; 434 clocks = <&k3_clks 187 1>; 435 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 436 }; 437 438 main_i2c1: i2c@2010000 { 439 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 440 reg = <0x00 0x2010000 0x00 0x100>; 441 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 clock-names = "fck"; 445 clocks = <&k3_clks 188 1>; 446 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 447 }; 448 449 main_i2c2: i2c@2020000 { 450 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 451 reg = <0x00 0x2020000 0x00 0x100>; 452 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clock-names = "fck"; 456 clocks = <&k3_clks 189 1>; 457 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 458 }; 459 460 main_i2c3: i2c@2030000 { 461 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 462 reg = <0x00 0x2030000 0x00 0x100>; 463 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 clock-names = "fck"; 467 clocks = <&k3_clks 190 1>; 468 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 469 }; 470 471 main_i2c4: i2c@2040000 { 472 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 473 reg = <0x00 0x2040000 0x00 0x100>; 474 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 clock-names = "fck"; 478 clocks = <&k3_clks 191 1>; 479 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 480 }; 481 482 main_i2c5: i2c@2050000 { 483 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 484 reg = <0x00 0x2050000 0x00 0x100>; 485 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 clock-names = "fck"; 489 clocks = <&k3_clks 192 1>; 490 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 491 }; 492 493 main_i2c6: i2c@2060000 { 494 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 495 reg = <0x00 0x2060000 0x00 0x100>; 496 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 clock-names = "fck"; 500 clocks = <&k3_clks 193 1>; 501 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 502 }; 503 504 main_sdhci0: mmc@4f80000 { 505 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 506 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 507 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 508 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 509 clock-names = "clk_ahb", "clk_xin"; 510 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 511 ti,otap-del-sel-legacy = <0x0>; 512 ti,otap-del-sel-mmc-hs = <0x0>; 513 ti,otap-del-sel-ddr52 = <0x6>; 514 ti,otap-del-sel-hs200 = <0x8>; 515 ti,otap-del-sel-hs400 = <0x0>; 516 ti,strobe-sel = <0x77>; 517 ti,trm-icp = <0x8>; 518 bus-width = <8>; 519 mmc-ddr-1_8v; 520 dma-coherent; 521 }; 522 523 main_sdhci1: mmc@4fb0000 { 524 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 525 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 526 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 527 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 528 clock-names = "clk_ahb", "clk_xin"; 529 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 530 ti,otap-del-sel-legacy = <0x0>; 531 ti,otap-del-sel-sd-hs = <0x0>; 532 ti,otap-del-sel-sdr12 = <0xf>; 533 ti,otap-del-sel-sdr25 = <0xf>; 534 ti,otap-del-sel-sdr50 = <0xc>; 535 ti,otap-del-sel-sdr104 = <0x5>; 536 ti,otap-del-sel-ddr50 = <0xc>; 537 no-1-8-v; 538 dma-coherent; 539 }; 540 541 serdes_wiz0: wiz@5060000 { 542 compatible = "ti,j721e-wiz-10g"; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 546 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 547 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 548 num-lanes = <4>; 549 #reset-cells = <1>; 550 ranges = <0x5060000 0x0 0x5060000 0x10000>; 551 552 assigned-clocks = <&k3_clks 292 85>; 553 assigned-clock-parents = <&k3_clks 292 89>; 554 555 wiz0_pll0_refclk: pll0-refclk { 556 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 557 clock-output-names = "wiz0_pll0_refclk"; 558 #clock-cells = <0>; 559 assigned-clocks = <&wiz0_pll0_refclk>; 560 assigned-clock-parents = <&k3_clks 292 85>; 561 }; 562 563 wiz0_pll1_refclk: pll1-refclk { 564 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 565 clock-output-names = "wiz0_pll1_refclk"; 566 #clock-cells = <0>; 567 assigned-clocks = <&wiz0_pll1_refclk>; 568 assigned-clock-parents = <&k3_clks 292 85>; 569 }; 570 571 wiz0_refclk_dig: refclk-dig { 572 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 573 clock-output-names = "wiz0_refclk_dig"; 574 #clock-cells = <0>; 575 assigned-clocks = <&wiz0_refclk_dig>; 576 assigned-clock-parents = <&k3_clks 292 85>; 577 }; 578 579 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 580 clocks = <&wiz0_refclk_dig>; 581 #clock-cells = <0>; 582 }; 583 584 serdes0: serdes@5060000 { 585 compatible = "ti,j721e-serdes-10g"; 586 reg = <0x05060000 0x00010000>; 587 reg-names = "torrent_phy"; 588 resets = <&serdes_wiz0 0>; 589 reset-names = "torrent_reset"; 590 clocks = <&wiz0_pll0_refclk>; 591 clock-names = "refclk"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 }; 595 }; 596 597 pcie1_rc: pcie@2910000 { 598 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 599 reg = <0x00 0x02910000 0x00 0x1000>, 600 <0x00 0x02917000 0x00 0x400>, 601 <0x00 0x0d800000 0x00 0x00800000>, 602 <0x00 0x18000000 0x00 0x00001000>; 603 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 604 interrupt-names = "link_state"; 605 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 606 device_type = "pci"; 607 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 608 max-link-speed = <3>; 609 num-lanes = <4>; 610 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 611 clocks = <&k3_clks 240 6>; 612 clock-names = "fck"; 613 #address-cells = <3>; 614 #size-cells = <2>; 615 bus-range = <0x0 0xf>; 616 cdns,no-bar-match-nbits = <64>; 617 vendor-id = /bits/ 16 <0x104c>; 618 device-id = /bits/ 16 <0xb00f>; 619 msi-map = <0x0 &gic_its 0x0 0x10000>; 620 dma-coherent; 621 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 622 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 623 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 624 }; 625 626 pcie1_ep: pcie-ep@2910000 { 627 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 628 reg = <0x00 0x02910000 0x00 0x1000>, 629 <0x00 0x02917000 0x00 0x400>, 630 <0x00 0x0d800000 0x00 0x00800000>, 631 <0x00 0x18000000 0x00 0x08000000>; 632 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 633 interrupt-names = "link_state"; 634 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 635 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 636 max-link-speed = <3>; 637 num-lanes = <4>; 638 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 639 clocks = <&k3_clks 240 6>; 640 clock-names = "fck"; 641 max-functions = /bits/ 8 <6>; 642 dma-coherent; 643 }; 644 645 usbss0: cdns-usb@4104000 { 646 compatible = "ti,j721e-usb"; 647 reg = <0x00 0x4104000 0x00 0x100>; 648 dma-coherent; 649 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 650 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 651 clock-names = "ref", "lpm"; 652 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 653 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 654 #address-cells = <2>; 655 #size-cells = <2>; 656 ranges; 657 658 usb0: usb@6000000 { 659 compatible = "cdns,usb3"; 660 reg = <0x00 0x6000000 0x00 0x10000>, 661 <0x00 0x6010000 0x00 0x10000>, 662 <0x00 0x6020000 0x00 0x10000>; 663 reg-names = "otg", "xhci", "dev"; 664 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 665 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 666 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 667 interrupt-names = "host", 668 "peripheral", 669 "otg"; 670 maximum-speed = "super-speed"; 671 dr_mode = "otg"; 672 }; 673 }; 674 675 main_r5fss0: r5fss@5c00000 { 676 compatible = "ti,j7200-r5fss"; 677 ti,cluster-mode = <1>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 681 <0x5d00000 0x00 0x5d00000 0x20000>; 682 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 683 684 main_r5fss0_core0: r5f@5c00000 { 685 compatible = "ti,j7200-r5f"; 686 reg = <0x5c00000 0x00010000>, 687 <0x5c10000 0x00010000>; 688 reg-names = "atcm", "btcm"; 689 ti,sci = <&dmsc>; 690 ti,sci-dev-id = <245>; 691 ti,sci-proc-ids = <0x06 0xff>; 692 resets = <&k3_reset 245 1>; 693 firmware-name = "j7200-main-r5f0_0-fw"; 694 ti,atcm-enable = <1>; 695 ti,btcm-enable = <1>; 696 ti,loczrama = <1>; 697 }; 698 699 main_r5fss0_core1: r5f@5d00000 { 700 compatible = "ti,j7200-r5f"; 701 reg = <0x5d00000 0x00008000>, 702 <0x5d10000 0x00008000>; 703 reg-names = "atcm", "btcm"; 704 ti,sci = <&dmsc>; 705 ti,sci-dev-id = <246>; 706 ti,sci-proc-ids = <0x07 0xff>; 707 resets = <&k3_reset 246 1>; 708 firmware-name = "j7200-main-r5f0_1-fw"; 709 ti,atcm-enable = <1>; 710 ti,btcm-enable = <1>; 711 ti,loczrama = <1>; 712 }; 713 }; 714}; 715