1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/net/ti-dp83867.h>
10#include <dt-bindings/mux/ti-serdes.h>
11
12/ {
13	chosen {
14		stdout-path = "serial2:115200n8";
15		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
16	};
17};
18
19&wkup_pmx0 {
20	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
21		pinctrl-single,pins = <
22			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
23			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
24			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
25			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
26			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
27			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
28			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
29			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
30			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
31			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
32			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
33			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
34		>;
35	};
36
37	mcu_mdio_pins_default: mcu-mdio1-pins-default {
38		pinctrl-single,pins = <
39			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
40			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
41		>;
42	};
43};
44
45&main_pmx0 {
46	main_i2c1_pins_default: main-i2c1-pins-default {
47		pinctrl-single,pins = <
48			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
49			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
50		>;
51	};
52
53	main_mmc1_pins_default: main-mmc1-pins-default {
54		pinctrl-single,pins = <
55			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
56			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
57			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
58			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
59			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
60			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
61			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
62			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
63		>;
64	};
65
66	main_usbss0_pins_default: main-usbss0-pins-default {
67		pinctrl-single,pins = <
68			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
69		>;
70	};
71};
72
73&wkup_uart0 {
74	/* Wakeup UART is used by System firmware */
75	status = "reserved";
76};
77
78&main_uart0 {
79	/* Shared with ATF on this platform */
80	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
81};
82
83&main_uart2 {
84	/* MAIN UART 2 is used by R5F firmware */
85	status = "reserved";
86};
87
88&main_uart3 {
89	/* UART not brought out */
90	status = "disabled";
91};
92
93&main_uart4 {
94	/* UART not brought out */
95	status = "disabled";
96};
97
98&main_uart5 {
99	/* UART not brought out */
100	status = "disabled";
101};
102
103&main_uart6 {
104	/* UART not brought out */
105	status = "disabled";
106};
107
108&main_uart7 {
109	/* UART not brought out */
110	status = "disabled";
111};
112
113&main_uart8 {
114	/* UART not brought out */
115	status = "disabled";
116};
117
118&main_uart9 {
119	/* UART not brought out */
120	status = "disabled";
121};
122
123&mcu_cpsw {
124	pinctrl-names = "default";
125	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
126};
127
128&davinci_mdio {
129	phy0: ethernet-phy@0 {
130		reg = <0>;
131		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
132		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
133	};
134};
135
136&cpsw_port1 {
137	phy-mode = "rgmii-rxid";
138	phy-handle = <&phy0>;
139};
140
141&main_i2c0 {
142	exp1: gpio@20 {
143		compatible = "ti,tca6416";
144		reg = <0x20>;
145		gpio-controller;
146		#gpio-cells = <2>;
147	};
148
149	exp2: gpio@22 {
150		compatible = "ti,tca6424";
151		reg = <0x22>;
152		gpio-controller;
153		#gpio-cells = <2>;
154	};
155};
156
157/*
158 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
159 * swapped on the CPB.
160 *
161 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
162 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
163 */
164&main_i2c1 {
165	pinctrl-names = "default";
166	pinctrl-0 = <&main_i2c1_pins_default>;
167	clock-frequency = <400000>;
168
169	exp3: gpio@20 {
170		compatible = "ti,tca6408";
171		reg = <0x20>;
172		gpio-controller;
173		#gpio-cells = <2>;
174		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
175				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
176				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
177	};
178};
179
180&main_sdhci0 {
181	/* eMMC */
182	non-removable;
183	ti,driver-strength-ohm = <50>;
184	disable-wp;
185};
186
187&main_sdhci1 {
188	/* SD card */
189	pinctrl-0 = <&main_mmc1_pins_default>;
190	pinctrl-names = "default";
191	ti,driver-strength-ohm = <50>;
192	disable-wp;
193};
194
195&serdes_ln_ctrl {
196	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
197		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
198};
199
200&usb_serdes_mux {
201	idle-states = <1>; /* USB0 to SERDES lane 3 */
202};
203
204&usbss0 {
205	pinctrl-names = "default";
206	pinctrl-0 = <&main_usbss0_pins_default>;
207	ti,vbus-divider;
208	ti,usb2-only;
209};
210
211&usb0 {
212	dr_mode = "otg";
213	maximum-speed = "high-speed";
214};
215
216&tscadc0 {
217	adc {
218		ti,adc-channels = <0 1 2 3 4 5 6 7>;
219	};
220};
221