1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/k3.h> 12#include <dt-bindings/soc/ti,sci_pm_domain.h> 13 14/ { 15 model = "Texas Instruments K3 AM654 SoC"; 16 compatible = "ti,am654"; 17 interrupt-parent = <&gic500>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 serial0 = &wkup_uart0; 23 serial1 = &mcu_uart0; 24 serial2 = &main_uart0; 25 serial3 = &main_uart1; 26 serial4 = &main_uart2; 27 i2c0 = &wkup_i2c0; 28 i2c1 = &mcu_i2c0; 29 i2c2 = &main_i2c0; 30 i2c3 = &main_i2c1; 31 i2c4 = &main_i2c2; 32 i2c5 = &main_i2c3; 33 ethernet0 = &cpsw_port1; 34 }; 35 36 chosen { }; 37 38 firmware { 39 optee { 40 compatible = "linaro,optee-tz"; 41 method = "smc"; 42 }; 43 44 psci: psci { 45 compatible = "arm,psci-1.0"; 46 method = "smc"; 47 }; 48 }; 49 50 a53_timer0: timer-cl0-cpu0 { 51 compatible = "arm,armv8-timer"; 52 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 53 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 54 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 55 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 56 }; 57 58 pmu: pmu { 59 compatible = "arm,cortex-a53-pmu"; 60 /* Recommendation from GIC500 TRM Table A.3 */ 61 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 62 }; 63 64 cbass_main: bus@100000 { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ 74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 75 /* MCUSS Range */ 76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, 78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 79 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 80 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 81 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, 82 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 83 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 84 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 85 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 86 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, 87 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, 88 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, 89 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; 90 91 cbass_mcu: bus@28380000 { 92 compatible = "simple-bus"; 93 #address-cells = <2>; 94 #size-cells = <2>; 95 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 96 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ 97 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 98 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 99 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 100 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ 101 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ 102 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 103 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 104 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */ 105 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */ 106 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ 107 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ 108 109 cbass_wakeup: bus@42040000 { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 /* WKUP Basic peripherals */ 114 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; 115 }; 116 }; 117 }; 118}; 119 120/* Now include the peripherals for each bus segments */ 121#include "k3-am65-main.dtsi" 122#include "k3-am65-mcu.dtsi" 123#include "k3-am65-wakeup.dtsi" 124