1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/k3.h> 12 13/ { 14 model = "Texas Instruments K3 AM654 SoC"; 15 compatible = "ti,am654"; 16 interrupt-parent = <&gic500>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 i2c0 = &wkup_i2c0; 27 i2c1 = &mcu_i2c0; 28 i2c2 = &main_i2c0; 29 i2c3 = &main_i2c1; 30 i2c4 = &main_i2c2; 31 i2c5 = &main_i2c3; 32 }; 33 34 chosen { }; 35 36 firmware { 37 optee { 38 compatible = "linaro,optee-tz"; 39 method = "smc"; 40 }; 41 42 psci: psci { 43 compatible = "arm,psci-1.0"; 44 method = "smc"; 45 }; 46 }; 47 48 a53_timer0: timer-cl0-cpu0 { 49 compatible = "arm,armv8-timer"; 50 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 51 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 52 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 53 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 54 }; 55 56 pmu: pmu { 57 compatible = "arm,armv8-pmuv3"; 58 /* Recommendation from GIC500 TRM Table A.3 */ 59 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 60 }; 61 62 cbass_main: interconnect@100000 { 63 compatible = "simple-bus"; 64 #address-cells = <2>; 65 #size-cells = <2>; 66 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 67 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 68 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 69 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 70 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 71 /* MCUSS Range */ 72 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 73 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, 74 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 75 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 76 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 77 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; 78 79 cbass_mcu: interconnect@28380000 { 80 compatible = "simple-bus"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 84 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ 85 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ 86 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 87 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 88 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */ 89 90 cbass_wakeup: interconnect@42040000 { 91 compatible = "simple-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 /* WKUP Basic peripherals */ 95 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; 96 }; 97 }; 98 }; 99}; 100 101/* Now include the peripherals for each bus segments */ 102#include "k3-am65-main.dtsi" 103#include "k3-am65-mcu.dtsi" 104#include "k3-am65-wakeup.dtsi" 105