1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu {
9	mcu_conf: scm-conf@40f00000 {
10		compatible = "syscon", "simple-mfd";
11		reg = <0x0 0x40f00000 0x0 0x20000>;
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges = <0x0 0x0 0x40f00000 0x20000>;
15
16		phy_gmii_sel: phy@4040 {
17			compatible = "ti,am654-phy-gmii-sel";
18			reg = <0x4040 0x4>;
19			#phy-cells = <1>;
20		};
21	};
22
23	mcu_uart0: serial@40a00000 {
24		compatible = "ti,am654-uart";
25			reg = <0x00 0x40a00000 0x00 0x100>;
26			interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
27			clock-frequency = <96000000>;
28			current-speed = <115200>;
29			power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
30	};
31
32	mcu_ram: sram@41c00000 {
33		compatible = "mmio-sram";
34		reg = <0x00 0x41c00000 0x00 0x80000>;
35		ranges = <0x0 0x00 0x41c00000 0x80000>;
36		#address-cells = <1>;
37		#size-cells = <1>;
38	};
39
40	mcu_i2c0: i2c@40b00000 {
41		compatible = "ti,am654-i2c", "ti,omap4-i2c";
42		reg = <0x0 0x40b00000 0x0 0x100>;
43		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
44		#address-cells = <1>;
45		#size-cells = <0>;
46		clock-names = "fck";
47		clocks = <&k3_clks 114 1>;
48		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
49	};
50
51	mcu_spi0: spi@40300000 {
52		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
53		reg = <0x0 0x40300000 0x0 0x400>;
54		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
55		clocks = <&k3_clks 142 1>;
56		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
57		#address-cells = <1>;
58		#size-cells = <0>;
59	};
60
61	mcu_spi1: spi@40310000 {
62		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
63		reg = <0x0 0x40310000 0x0 0x400>;
64		interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
65		clocks = <&k3_clks 143 1>;
66		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
67		#address-cells = <1>;
68		#size-cells = <0>;
69	};
70
71	mcu_spi2: spi@40320000 {
72		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
73		reg = <0x0 0x40320000 0x0 0x400>;
74		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
75		clocks = <&k3_clks 144 1>;
76		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
77		#address-cells = <1>;
78		#size-cells = <0>;
79	};
80
81	tscadc0: tscadc@40200000 {
82		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
83		reg = <0x0 0x40200000 0x0 0x1000>;
84		interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
85		clocks = <&k3_clks 0 2>;
86		assigned-clocks = <&k3_clks 0 2>;
87		assigned-clock-rates = <60000000>;
88		clock-names = "adc_tsc_fck";
89		dmas = <&mcu_udmap 0x7100>,
90			<&mcu_udmap 0x7101 >;
91		dma-names = "fifo0", "fifo1";
92
93		adc {
94			#io-channel-cells = <1>;
95			compatible = "ti,am654-adc", "ti,am3359-adc";
96		};
97	};
98
99	tscadc1: tscadc@40210000 {
100		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
101		reg = <0x0 0x40210000 0x0 0x1000>;
102		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
103		clocks = <&k3_clks 1 2>;
104		assigned-clocks = <&k3_clks 1 2>;
105		assigned-clock-rates = <60000000>;
106		clock-names = "adc_tsc_fck";
107		dmas = <&mcu_udmap 0x7102>,
108			<&mcu_udmap 0x7103>;
109		dma-names = "fifo0", "fifo1";
110
111		adc {
112			#io-channel-cells = <1>;
113			compatible = "ti,am654-adc", "ti,am3359-adc";
114		};
115	};
116
117	mcu_navss: bus@28380000 {
118		compatible = "simple-mfd";
119		#address-cells = <2>;
120		#size-cells = <2>;
121		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
122		dma-coherent;
123		dma-ranges;
124
125		ti,sci-dev-id = <119>;
126
127		mcu_ringacc: ringacc@2b800000 {
128			compatible = "ti,am654-navss-ringacc";
129			reg =	<0x0 0x2b800000 0x0 0x400000>,
130				<0x0 0x2b000000 0x0 0x400000>,
131				<0x0 0x28590000 0x0 0x100>,
132				<0x0 0x2a500000 0x0 0x40000>;
133			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
134			ti,num-rings = <286>;
135			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
136			ti,sci = <&dmsc>;
137			ti,sci-dev-id = <195>;
138			msi-parent = <&inta_main_udmass>;
139		};
140
141		mcu_udmap: dma-controller@285c0000 {
142			compatible = "ti,am654-navss-mcu-udmap";
143			reg =	<0x0 0x285c0000 0x0 0x100>,
144				<0x0 0x2a800000 0x0 0x40000>,
145				<0x0 0x2aa00000 0x0 0x40000>;
146			reg-names = "gcfg", "rchanrt", "tchanrt";
147			msi-parent = <&inta_main_udmass>;
148			#dma-cells = <1>;
149
150			ti,sci = <&dmsc>;
151			ti,sci-dev-id = <194>;
152			ti,ringacc = <&mcu_ringacc>;
153
154			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
155						<0xd>; /* TX_CHAN */
156			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
157						<0xa>; /* RX_CHAN */
158			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
159		};
160	};
161
162	fss: fss@47000000 {
163		compatible = "simple-bus";
164		#address-cells = <2>;
165		#size-cells = <2>;
166		ranges;
167
168		ospi0: spi@47040000 {
169			compatible = "ti,am654-ospi", "cdns,qspi-nor";
170			reg = <0x0 0x47040000 0x0 0x100>,
171				<0x5 0x00000000 0x1 0x0000000>;
172			interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
173			cdns,fifo-depth = <256>;
174			cdns,fifo-width = <4>;
175			cdns,trigger-address = <0x0>;
176			clocks = <&k3_clks 248 0>;
177			assigned-clocks = <&k3_clks 248 0>;
178			assigned-clock-parents = <&k3_clks 248 2>;
179			assigned-clock-rates = <166666666>;
180			power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
181			#address-cells = <1>;
182			#size-cells = <0>;
183		};
184
185		ospi1: spi@47050000 {
186			compatible = "ti,am654-ospi", "cdns,qspi-nor";
187			reg = <0x0 0x47050000 0x0 0x100>,
188				<0x7 0x00000000 0x1 0x00000000>;
189			interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
190			cdns,fifo-depth = <256>;
191			cdns,fifo-width = <4>;
192			cdns,trigger-address = <0x0>;
193			clocks = <&k3_clks 249 6>;
194			power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
195			#address-cells = <1>;
196			#size-cells = <0>;
197		};
198	};
199
200	mcu_cpsw: ethernet@46000000 {
201		compatible = "ti,am654-cpsw-nuss";
202		#address-cells = <2>;
203		#size-cells = <2>;
204		reg = <0x0 0x46000000 0x0 0x200000>;
205		reg-names = "cpsw_nuss";
206		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
207		dma-coherent;
208		clocks = <&k3_clks 5 10>;
209		clock-names = "fck";
210		power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
211
212		dmas = <&mcu_udmap 0xf000>,
213		       <&mcu_udmap 0xf001>,
214		       <&mcu_udmap 0xf002>,
215		       <&mcu_udmap 0xf003>,
216		       <&mcu_udmap 0xf004>,
217		       <&mcu_udmap 0xf005>,
218		       <&mcu_udmap 0xf006>,
219		       <&mcu_udmap 0xf007>,
220		       <&mcu_udmap 0x7000>;
221		dma-names = "tx0", "tx1", "tx2", "tx3",
222			    "tx4", "tx5", "tx6", "tx7",
223			    "rx";
224
225		ethernet-ports {
226			#address-cells = <1>;
227			#size-cells = <0>;
228
229			cpsw_port1: port@1 {
230				reg = <1>;
231				ti,mac-only;
232				label = "port1";
233				ti,syscon-efuse = <&mcu_conf 0x200>;
234				phys = <&phy_gmii_sel 1>;
235			};
236		};
237
238		davinci_mdio: mdio@f00 {
239			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
240			reg = <0x0 0xf00 0x0 0x100>;
241			#address-cells = <1>;
242			#size-cells = <0>;
243			clocks = <&k3_clks 5 10>;
244			clock-names = "fck";
245			bus_freq = <1000000>;
246		};
247
248		cpts@3d000 {
249			compatible = "ti,am65-cpts";
250			reg = <0x0 0x3d000 0x0 0x400>;
251			clocks = <&mcu_cpsw_cpts_mux>;
252			clock-names = "cpts";
253			interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
254			interrupt-names = "cpts";
255			ti,cpts-ext-ts-inputs = <4>;
256			ti,cpts-periodic-outputs = <2>;
257
258			mcu_cpsw_cpts_mux: refclk-mux {
259				#clock-cells = <0>;
260				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
261					<&k3_clks 118 6>, <&k3_clks 118 3>,
262					<&k3_clks 118 8>, <&k3_clks 118 14>,
263					<&k3_clks 120 3>, <&k3_clks 121 3>;
264				assigned-clocks = <&mcu_cpsw_cpts_mux>;
265				assigned-clock-parents = <&k3_clks 118 5>;
266			};
267		};
268	};
269
270	mcu_r5fss0: r5fss@41000000 {
271		compatible = "ti,am654-r5fss";
272		ti,cluster-mode = <1>;
273		#address-cells = <1>;
274		#size-cells = <1>;
275		ranges = <0x41000000 0x00 0x41000000 0x20000>,
276			 <0x41400000 0x00 0x41400000 0x20000>;
277		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
278
279		mcu_r5fss0_core0: r5f@41000000 {
280			compatible = "ti,am654-r5f";
281			reg = <0x41000000 0x00008000>,
282			      <0x41010000 0x00008000>;
283			reg-names = "atcm", "btcm";
284			ti,sci = <&dmsc>;
285			ti,sci-dev-id = <159>;
286			ti,sci-proc-ids = <0x01 0xff>;
287			resets = <&k3_reset 159 1>;
288			firmware-name = "am65x-mcu-r5f0_0-fw";
289			ti,atcm-enable = <1>;
290			ti,btcm-enable = <1>;
291			ti,loczrama = <1>;
292		};
293
294		mcu_r5fss0_core1: r5f@41400000 {
295			compatible = "ti,am654-r5f";
296			reg = <0x41400000 0x00008000>,
297			      <0x41410000 0x00008000>;
298			reg-names = "atcm", "btcm";
299			ti,sci = <&dmsc>;
300			ti,sci-dev-id = <245>;
301			ti,sci-proc-ids = <0x02 0xff>;
302			resets = <&k3_reset 245 1>;
303			firmware-name = "am65x-mcu-r5f0_1-fw";
304			ti,atcm-enable = <1>;
305			ti,btcm-enable = <1>;
306			ti,loczrama = <1>;
307		};
308	};
309
310	mcu_rti1: watchdog@40610000 {
311		compatible = "ti,j7-rti-wdt";
312		reg = <0x0 0x40610000 0x0 0x100>;
313		clocks = <&k3_clks 135 0>;
314		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
315		assigned-clocks = <&k3_clks 135 0>;
316		assigned-clock-parents = <&k3_clks 135 4>;
317	};
318};
319