1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <48000000>; 92 current-speed = <115200>; 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 status = "disabled"; 95 }; 96 97 main_uart1: serial@2810000 { 98 compatible = "ti,am654-uart"; 99 reg = <0x00 0x02810000 0x00 0x100>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 status = "disabled"; 104 }; 105 106 main_uart2: serial@2820000 { 107 compatible = "ti,am654-uart"; 108 reg = <0x00 0x02820000 0x00 0x100>; 109 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 110 clock-frequency = <48000000>; 111 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 112 status = "disabled"; 113 }; 114 115 crypto: crypto@4e00000 { 116 compatible = "ti,am654-sa2ul"; 117 reg = <0x0 0x4e00000 0x0 0x1200>; 118 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 122 123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, 124 <&main_udmap 0x4003>; 125 dma-names = "tx", "rx1", "rx2"; 126 127 rng: rng@4e10000 { 128 compatible = "inside-secure,safexcel-eip76"; 129 reg = <0x0 0x4e10000 0x0 0x7d>; 130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; /* Used by OP-TEE */ 132 }; 133 }; 134 135 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 136 main_timerio_input: pinctrl@104200 { 137 compatible = "pinctrl-single"; 138 reg = <0x0 0x104200 0x0 0x30>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001ff>; 142 }; 143 144 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 145 main_timerio_output: pinctrl@104280 { 146 compatible = "pinctrl-single"; 147 reg = <0x0 0x104280 0x0 0x20>; 148 #pinctrl-cells = <1>; 149 pinctrl-single,register-width = <32>; 150 pinctrl-single,function-mask = <0x0000000f>; 151 }; 152 153 main_pmx0: pinctrl@11c000 { 154 compatible = "pinctrl-single"; 155 reg = <0x0 0x11c000 0x0 0x2e4>; 156 #pinctrl-cells = <1>; 157 pinctrl-single,register-width = <32>; 158 pinctrl-single,function-mask = <0xffffffff>; 159 }; 160 161 main_pmx1: pinctrl@11c2e8 { 162 compatible = "pinctrl-single"; 163 reg = <0x0 0x11c2e8 0x0 0x24>; 164 #pinctrl-cells = <1>; 165 pinctrl-single,register-width = <32>; 166 pinctrl-single,function-mask = <0xffffffff>; 167 }; 168 169 main_i2c0: i2c@2000000 { 170 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 171 reg = <0x0 0x2000000 0x0 0x100>; 172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 clock-names = "fck"; 176 clocks = <&k3_clks 110 1>; 177 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 178 status = "disabled"; 179 }; 180 181 main_i2c1: i2c@2010000 { 182 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 183 reg = <0x0 0x2010000 0x0 0x100>; 184 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 clock-names = "fck"; 188 clocks = <&k3_clks 111 1>; 189 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 190 status = "disabled"; 191 }; 192 193 main_i2c2: i2c@2020000 { 194 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 195 reg = <0x0 0x2020000 0x0 0x100>; 196 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clock-names = "fck"; 200 clocks = <&k3_clks 112 1>; 201 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 202 status = "disabled"; 203 }; 204 205 main_i2c3: i2c@2030000 { 206 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 207 reg = <0x0 0x2030000 0x0 0x100>; 208 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 clock-names = "fck"; 212 clocks = <&k3_clks 113 1>; 213 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 214 status = "disabled"; 215 }; 216 217 ecap0: pwm@3100000 { 218 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 219 #pwm-cells = <3>; 220 reg = <0x0 0x03100000 0x0 0x60>; 221 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 222 clocks = <&k3_clks 39 0>; 223 clock-names = "fck"; 224 status = "disabled"; 225 }; 226 227 main_spi0: spi@2100000 { 228 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 229 reg = <0x0 0x2100000 0x0 0x400>; 230 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 137 1>; 232 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 236 dma-names = "tx0", "rx0"; 237 status = "disabled"; 238 }; 239 240 main_spi1: spi@2110000 { 241 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 242 reg = <0x0 0x2110000 0x0 0x400>; 243 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&k3_clks 138 1>; 245 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 assigned-clocks = <&k3_clks 137 1>; 249 assigned-clock-rates = <48000000>; 250 status = "disabled"; 251 }; 252 253 main_spi2: spi@2120000 { 254 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 255 reg = <0x0 0x2120000 0x0 0x400>; 256 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&k3_clks 139 1>; 258 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 status = "disabled"; 262 }; 263 264 main_spi3: spi@2130000 { 265 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 266 reg = <0x0 0x2130000 0x0 0x400>; 267 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&k3_clks 140 1>; 269 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 status = "disabled"; 273 }; 274 275 main_spi4: spi@2140000 { 276 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 277 reg = <0x0 0x2140000 0x0 0x400>; 278 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 141 1>; 280 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 main_timer0: timer@2400000 { 287 compatible = "ti,am654-timer"; 288 reg = <0x00 0x2400000 0x00 0x400>; 289 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&k3_clks 23 0>; 291 clock-names = "fck"; 292 assigned-clocks = <&k3_clks 23 0>; 293 assigned-clock-parents = <&k3_clks 23 1>; 294 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; 295 ti,timer-pwm; 296 }; 297 298 main_timer1: timer@2410000 { 299 compatible = "ti,am654-timer"; 300 reg = <0x00 0x2410000 0x00 0x400>; 301 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&k3_clks 24 0>; 303 clock-names = "fck"; 304 assigned-clocks = <&k3_clks 24 0>; 305 assigned-clock-parents = <&k3_clks 24 1>; 306 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; 307 ti,timer-pwm; 308 }; 309 310 main_timer2: timer@2420000 { 311 compatible = "ti,am654-timer"; 312 reg = <0x00 0x2420000 0x00 0x400>; 313 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&k3_clks 27 0>; 315 clock-names = "fck"; 316 assigned-clocks = <&k3_clks 27 0>; 317 assigned-clock-parents = <&k3_clks 27 1>; 318 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 319 ti,timer-pwm; 320 }; 321 322 main_timer3: timer@2430000 { 323 compatible = "ti,am654-timer"; 324 reg = <0x00 0x2430000 0x00 0x400>; 325 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&k3_clks 28 0>; 327 clock-names = "fck"; 328 assigned-clocks = <&k3_clks 28 0>; 329 assigned-clock-parents = <&k3_clks 28 1>; 330 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 331 ti,timer-pwm; 332 }; 333 334 main_timer4: timer@2440000 { 335 compatible = "ti,am654-timer"; 336 reg = <0x00 0x2440000 0x00 0x400>; 337 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&k3_clks 29 0>; 339 clock-names = "fck"; 340 assigned-clocks = <&k3_clks 29 0>; 341 assigned-clock-parents = <&k3_clks 29 1>; 342 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 343 ti,timer-pwm; 344 }; 345 346 main_timer5: timer@2450000 { 347 compatible = "ti,am654-timer"; 348 reg = <0x00 0x2450000 0x00 0x400>; 349 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&k3_clks 30 0>; 351 clock-names = "fck"; 352 assigned-clocks = <&k3_clks 30 0>; 353 assigned-clock-parents = <&k3_clks 30 1>; 354 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; 355 ti,timer-pwm; 356 }; 357 358 main_timer6: timer@2460000 { 359 compatible = "ti,am654-timer"; 360 reg = <0x00 0x2460000 0x00 0x400>; 361 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&k3_clks 31 0>; 363 assigned-clocks = <&k3_clks 31 0>; 364 assigned-clock-parents = <&k3_clks 31 1>; 365 clock-names = "fck"; 366 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; 367 ti,timer-pwm; 368 }; 369 370 main_timer7: timer@2470000 { 371 compatible = "ti,am654-timer"; 372 reg = <0x00 0x2470000 0x00 0x400>; 373 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&k3_clks 32 0>; 375 clock-names = "fck"; 376 assigned-clocks = <&k3_clks 32 0>; 377 assigned-clock-parents = <&k3_clks 32 1>; 378 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; 379 ti,timer-pwm; 380 }; 381 382 main_timer8: timer@2480000 { 383 compatible = "ti,am654-timer"; 384 reg = <0x00 0x2480000 0x00 0x400>; 385 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&k3_clks 33 0>; 387 clock-names = "fck"; 388 assigned-clocks = <&k3_clks 33 0>; 389 assigned-clock-parents = <&k3_clks 33 1>; 390 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; 391 ti,timer-pwm; 392 }; 393 394 main_timer9: timer@2490000 { 395 compatible = "ti,am654-timer"; 396 reg = <0x00 0x2490000 0x00 0x400>; 397 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&k3_clks 34 0>; 399 clock-names = "fck"; 400 assigned-clocks = <&k3_clks 34 0>; 401 assigned-clock-parents = <&k3_clks 34 1>; 402 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; 403 ti,timer-pwm; 404 }; 405 406 main_timer10: timer@24a0000 { 407 compatible = "ti,am654-timer"; 408 reg = <0x00 0x24a0000 0x00 0x400>; 409 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&k3_clks 25 0>; 411 clock-names = "fck"; 412 assigned-clocks = <&k3_clks 25 0>; 413 assigned-clock-parents = <&k3_clks 25 1>; 414 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; 415 ti,timer-pwm; 416 }; 417 418 main_timer11: timer@24b0000 { 419 compatible = "ti,am654-timer"; 420 reg = <0x00 0x24b0000 0x00 0x400>; 421 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&k3_clks 26 0>; 423 clock-names = "fck"; 424 assigned-clocks = <&k3_clks 26 0>; 425 assigned-clock-parents = <&k3_clks 26 1>; 426 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 427 ti,timer-pwm; 428 }; 429 430 sdhci0: mmc@4f80000 { 431 compatible = "ti,am654-sdhci-5.1"; 432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 433 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 435 clock-names = "clk_ahb", "clk_xin"; 436 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 437 mmc-ddr-1_8v; 438 mmc-hs200-1_8v; 439 ti,otap-del-sel-legacy = <0x0>; 440 ti,otap-del-sel-mmc-hs = <0x0>; 441 ti,otap-del-sel-sd-hs = <0x0>; 442 ti,otap-del-sel-sdr12 = <0x0>; 443 ti,otap-del-sel-sdr25 = <0x0>; 444 ti,otap-del-sel-sdr50 = <0x8>; 445 ti,otap-del-sel-sdr104 = <0x7>; 446 ti,otap-del-sel-ddr50 = <0x5>; 447 ti,otap-del-sel-ddr52 = <0x5>; 448 ti,otap-del-sel-hs200 = <0x5>; 449 ti,otap-del-sel-hs400 = <0x0>; 450 ti,trm-icp = <0x8>; 451 dma-coherent; 452 }; 453 454 sdhci1: mmc@4fa0000 { 455 compatible = "ti,am654-sdhci-5.1"; 456 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 457 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 458 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 459 clock-names = "clk_ahb", "clk_xin"; 460 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 461 ti,otap-del-sel-legacy = <0x0>; 462 ti,otap-del-sel-mmc-hs = <0x0>; 463 ti,otap-del-sel-sd-hs = <0x0>; 464 ti,otap-del-sel-sdr12 = <0x0>; 465 ti,otap-del-sel-sdr25 = <0x0>; 466 ti,otap-del-sel-sdr50 = <0x8>; 467 ti,otap-del-sel-sdr104 = <0x7>; 468 ti,otap-del-sel-ddr50 = <0x4>; 469 ti,otap-del-sel-ddr52 = <0x4>; 470 ti,otap-del-sel-hs200 = <0x7>; 471 ti,clkbuf-sel = <0x7>; 472 ti,otap-del-sel = <0x2>; 473 ti,trm-icp = <0x8>; 474 dma-coherent; 475 }; 476 477 scm_conf: scm-conf@100000 { 478 compatible = "syscon", "simple-mfd"; 479 reg = <0 0x00100000 0 0x1c000>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 ranges = <0x0 0x0 0x00100000 0x1c000>; 483 484 pcie0_mode: pcie-mode@4060 { 485 compatible = "syscon"; 486 reg = <0x00004060 0x4>; 487 }; 488 489 pcie1_mode: pcie-mode@4070 { 490 compatible = "syscon"; 491 reg = <0x00004070 0x4>; 492 }; 493 494 pcie_devid: pcie-devid@210 { 495 compatible = "syscon"; 496 reg = <0x00000210 0x4>; 497 }; 498 499 serdes0_clk: clock@4080 { 500 compatible = "syscon"; 501 reg = <0x00004080 0x4>; 502 }; 503 504 serdes1_clk: clock@4090 { 505 compatible = "syscon"; 506 reg = <0x00004090 0x4>; 507 }; 508 509 serdes_mux: mux-controller { 510 compatible = "mmio-mux"; 511 #mux-control-cells = <1>; 512 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 513 <0x4090 0x3>; /* SERDES1 lane select */ 514 }; 515 516 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 517 compatible = "syscon"; 518 reg = <0x000041e0 0x14>; 519 }; 520 521 ehrpwm_tbclk: clock@4140 { 522 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 523 reg = <0x4140 0x18>; 524 #clock-cells = <1>; 525 }; 526 }; 527 528 dwc3_0: dwc3@4000000 { 529 compatible = "ti,am654-dwc3"; 530 reg = <0x0 0x4000000 0x0 0x4000>; 531 #address-cells = <1>; 532 #size-cells = <1>; 533 ranges = <0x0 0x0 0x4000000 0x20000>; 534 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 535 dma-coherent; 536 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 537 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 538 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 539 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 540 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 541 542 usb0: usb@10000 { 543 compatible = "snps,dwc3"; 544 reg = <0x10000 0x10000>; 545 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "peripheral", 549 "host", 550 "otg"; 551 maximum-speed = "high-speed"; 552 dr_mode = "otg"; 553 phys = <&usb0_phy>; 554 phy-names = "usb2-phy"; 555 snps,dis_u3_susphy_quirk; 556 }; 557 }; 558 559 usb0_phy: phy@4100000 { 560 compatible = "ti,am654-usb2", "ti,omap-usb2"; 561 reg = <0x0 0x4100000 0x0 0x54>; 562 syscon-phy-power = <&scm_conf 0x4000>; 563 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 564 clock-names = "wkupclk", "refclk"; 565 #phy-cells = <0>; 566 }; 567 568 dwc3_1: dwc3@4020000 { 569 compatible = "ti,am654-dwc3"; 570 reg = <0x0 0x4020000 0x0 0x4000>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 ranges = <0x0 0x0 0x4020000 0x20000>; 574 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 575 dma-coherent; 576 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 577 clocks = <&k3_clks 152 2>; 578 assigned-clocks = <&k3_clks 152 2>; 579 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 580 581 usb1: usb@10000 { 582 compatible = "snps,dwc3"; 583 reg = <0x10000 0x10000>; 584 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "peripheral", 588 "host", 589 "otg"; 590 maximum-speed = "high-speed"; 591 dr_mode = "otg"; 592 phys = <&usb1_phy>; 593 phy-names = "usb2-phy"; 594 }; 595 }; 596 597 usb1_phy: phy@4110000 { 598 compatible = "ti,am654-usb2", "ti,omap-usb2"; 599 reg = <0x0 0x4110000 0x0 0x54>; 600 syscon-phy-power = <&scm_conf 0x4020>; 601 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 602 clock-names = "wkupclk", "refclk"; 603 #phy-cells = <0>; 604 }; 605 606 intr_main_gpio: interrupt-controller@a00000 { 607 compatible = "ti,sci-intr"; 608 reg = <0x0 0x00a00000 0x0 0x400>; 609 ti,intr-trigger-type = <1>; 610 interrupt-controller; 611 interrupt-parent = <&gic500>; 612 #interrupt-cells = <1>; 613 ti,sci = <&dmsc>; 614 ti,sci-dev-id = <100>; 615 ti,interrupt-ranges = <0 392 32>; 616 }; 617 618 main_navss: bus@30800000 { 619 compatible = "simple-mfd"; 620 #address-cells = <2>; 621 #size-cells = <2>; 622 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 623 dma-coherent; 624 dma-ranges; 625 626 ti,sci-dev-id = <118>; 627 628 intr_main_navss: interrupt-controller@310e0000 { 629 compatible = "ti,sci-intr"; 630 reg = <0x0 0x310e0000 0x0 0x2000>; 631 ti,intr-trigger-type = <4>; 632 interrupt-controller; 633 interrupt-parent = <&gic500>; 634 #interrupt-cells = <1>; 635 ti,sci = <&dmsc>; 636 ti,sci-dev-id = <182>; 637 ti,interrupt-ranges = <0 64 64>, 638 <64 448 64>; 639 }; 640 641 inta_main_udmass: interrupt-controller@33d00000 { 642 compatible = "ti,sci-inta"; 643 reg = <0x0 0x33d00000 0x0 0x100000>; 644 interrupt-controller; 645 interrupt-parent = <&intr_main_navss>; 646 msi-controller; 647 #interrupt-cells = <0>; 648 ti,sci = <&dmsc>; 649 ti,sci-dev-id = <179>; 650 ti,interrupt-ranges = <0 0 256>; 651 }; 652 653 secure_proxy_main: mailbox@32c00000 { 654 compatible = "ti,am654-secure-proxy"; 655 #mbox-cells = <1>; 656 reg-names = "target_data", "rt", "scfg"; 657 reg = <0x00 0x32c00000 0x00 0x100000>, 658 <0x00 0x32400000 0x00 0x100000>, 659 <0x00 0x32800000 0x00 0x100000>; 660 interrupt-names = "rx_011"; 661 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 662 }; 663 664 hwspinlock: spinlock@30e00000 { 665 compatible = "ti,am654-hwspinlock"; 666 reg = <0x00 0x30e00000 0x00 0x1000>; 667 #hwlock-cells = <1>; 668 }; 669 670 mailbox0_cluster0: mailbox@31f80000 { 671 compatible = "ti,am654-mailbox"; 672 reg = <0x00 0x31f80000 0x00 0x200>; 673 #mbox-cells = <1>; 674 ti,mbox-num-users = <4>; 675 ti,mbox-num-fifos = <16>; 676 interrupt-parent = <&intr_main_navss>; 677 status = "disabled"; 678 }; 679 680 mailbox0_cluster1: mailbox@31f81000 { 681 compatible = "ti,am654-mailbox"; 682 reg = <0x00 0x31f81000 0x00 0x200>; 683 #mbox-cells = <1>; 684 ti,mbox-num-users = <4>; 685 ti,mbox-num-fifos = <16>; 686 interrupt-parent = <&intr_main_navss>; 687 status = "disabled"; 688 }; 689 690 mailbox0_cluster2: mailbox@31f82000 { 691 compatible = "ti,am654-mailbox"; 692 reg = <0x00 0x31f82000 0x00 0x200>; 693 #mbox-cells = <1>; 694 ti,mbox-num-users = <4>; 695 ti,mbox-num-fifos = <16>; 696 interrupt-parent = <&intr_main_navss>; 697 status = "disabled"; 698 }; 699 700 mailbox0_cluster3: mailbox@31f83000 { 701 compatible = "ti,am654-mailbox"; 702 reg = <0x00 0x31f83000 0x00 0x200>; 703 #mbox-cells = <1>; 704 ti,mbox-num-users = <4>; 705 ti,mbox-num-fifos = <16>; 706 interrupt-parent = <&intr_main_navss>; 707 status = "disabled"; 708 }; 709 710 mailbox0_cluster4: mailbox@31f84000 { 711 compatible = "ti,am654-mailbox"; 712 reg = <0x00 0x31f84000 0x00 0x200>; 713 #mbox-cells = <1>; 714 ti,mbox-num-users = <4>; 715 ti,mbox-num-fifos = <16>; 716 interrupt-parent = <&intr_main_navss>; 717 status = "disabled"; 718 }; 719 720 mailbox0_cluster5: mailbox@31f85000 { 721 compatible = "ti,am654-mailbox"; 722 reg = <0x00 0x31f85000 0x00 0x200>; 723 #mbox-cells = <1>; 724 ti,mbox-num-users = <4>; 725 ti,mbox-num-fifos = <16>; 726 interrupt-parent = <&intr_main_navss>; 727 status = "disabled"; 728 }; 729 730 mailbox0_cluster6: mailbox@31f86000 { 731 compatible = "ti,am654-mailbox"; 732 reg = <0x00 0x31f86000 0x00 0x200>; 733 #mbox-cells = <1>; 734 ti,mbox-num-users = <4>; 735 ti,mbox-num-fifos = <16>; 736 interrupt-parent = <&intr_main_navss>; 737 status = "disabled"; 738 }; 739 740 mailbox0_cluster7: mailbox@31f87000 { 741 compatible = "ti,am654-mailbox"; 742 reg = <0x00 0x31f87000 0x00 0x200>; 743 #mbox-cells = <1>; 744 ti,mbox-num-users = <4>; 745 ti,mbox-num-fifos = <16>; 746 interrupt-parent = <&intr_main_navss>; 747 status = "disabled"; 748 }; 749 750 mailbox0_cluster8: mailbox@31f88000 { 751 compatible = "ti,am654-mailbox"; 752 reg = <0x00 0x31f88000 0x00 0x200>; 753 #mbox-cells = <1>; 754 ti,mbox-num-users = <4>; 755 ti,mbox-num-fifos = <16>; 756 interrupt-parent = <&intr_main_navss>; 757 status = "disabled"; 758 }; 759 760 mailbox0_cluster9: mailbox@31f89000 { 761 compatible = "ti,am654-mailbox"; 762 reg = <0x00 0x31f89000 0x00 0x200>; 763 #mbox-cells = <1>; 764 ti,mbox-num-users = <4>; 765 ti,mbox-num-fifos = <16>; 766 interrupt-parent = <&intr_main_navss>; 767 status = "disabled"; 768 }; 769 770 mailbox0_cluster10: mailbox@31f8a000 { 771 compatible = "ti,am654-mailbox"; 772 reg = <0x00 0x31f8a000 0x00 0x200>; 773 #mbox-cells = <1>; 774 ti,mbox-num-users = <4>; 775 ti,mbox-num-fifos = <16>; 776 interrupt-parent = <&intr_main_navss>; 777 status = "disabled"; 778 }; 779 780 mailbox0_cluster11: mailbox@31f8b000 { 781 compatible = "ti,am654-mailbox"; 782 reg = <0x00 0x31f8b000 0x00 0x200>; 783 #mbox-cells = <1>; 784 ti,mbox-num-users = <4>; 785 ti,mbox-num-fifos = <16>; 786 interrupt-parent = <&intr_main_navss>; 787 status = "disabled"; 788 }; 789 790 ringacc: ringacc@3c000000 { 791 compatible = "ti,am654-navss-ringacc"; 792 reg = <0x0 0x3c000000 0x0 0x400000>, 793 <0x0 0x38000000 0x0 0x400000>, 794 <0x0 0x31120000 0x0 0x100>, 795 <0x0 0x33000000 0x0 0x40000>; 796 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 797 ti,num-rings = <818>; 798 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 799 ti,sci = <&dmsc>; 800 ti,sci-dev-id = <187>; 801 msi-parent = <&inta_main_udmass>; 802 }; 803 804 main_udmap: dma-controller@31150000 { 805 compatible = "ti,am654-navss-main-udmap"; 806 reg = <0x0 0x31150000 0x0 0x100>, 807 <0x0 0x34000000 0x0 0x100000>, 808 <0x0 0x35000000 0x0 0x100000>; 809 reg-names = "gcfg", "rchanrt", "tchanrt"; 810 msi-parent = <&inta_main_udmass>; 811 #dma-cells = <1>; 812 813 ti,sci = <&dmsc>; 814 ti,sci-dev-id = <188>; 815 ti,ringacc = <&ringacc>; 816 817 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 818 <0xd>; /* TX_CHAN */ 819 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 820 <0xa>; /* RX_CHAN */ 821 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 822 }; 823 824 cpts@310d0000 { 825 compatible = "ti,am65-cpts"; 826 reg = <0x0 0x310d0000 0x0 0x400>; 827 reg-names = "cpts"; 828 clocks = <&main_cpts_mux>; 829 clock-names = "cpts"; 830 interrupts-extended = <&intr_main_navss 391>; 831 interrupt-names = "cpts"; 832 ti,cpts-periodic-outputs = <6>; 833 ti,cpts-ext-ts-inputs = <8>; 834 835 main_cpts_mux: refclk-mux { 836 #clock-cells = <0>; 837 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 838 <&k3_clks 118 6>, <&k3_clks 118 3>, 839 <&k3_clks 118 8>, <&k3_clks 118 14>, 840 <&k3_clks 120 3>, <&k3_clks 121 3>; 841 assigned-clocks = <&main_cpts_mux>; 842 assigned-clock-parents = <&k3_clks 118 5>; 843 }; 844 }; 845 }; 846 847 main_gpio0: gpio@600000 { 848 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 849 reg = <0x0 0x600000 0x0 0x100>; 850 gpio-controller; 851 #gpio-cells = <2>; 852 interrupt-parent = <&intr_main_gpio>; 853 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 854 interrupt-controller; 855 #interrupt-cells = <2>; 856 ti,ngpio = <96>; 857 ti,davinci-gpio-unbanked = <0>; 858 clocks = <&k3_clks 57 0>; 859 clock-names = "gpio"; 860 }; 861 862 main_gpio1: gpio@601000 { 863 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 864 reg = <0x0 0x601000 0x0 0x100>; 865 gpio-controller; 866 #gpio-cells = <2>; 867 interrupt-parent = <&intr_main_gpio>; 868 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 869 interrupt-controller; 870 #interrupt-cells = <2>; 871 ti,ngpio = <90>; 872 ti,davinci-gpio-unbanked = <0>; 873 clocks = <&k3_clks 58 0>; 874 clock-names = "gpio"; 875 }; 876 877 pcie0_rc: pcie@5500000 { 878 compatible = "ti,am654-pcie-rc"; 879 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 880 reg-names = "app", "dbics", "config", "atu"; 881 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 882 #address-cells = <3>; 883 #size-cells = <2>; 884 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, 885 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 886 ti,syscon-pcie-id = <&pcie_devid>; 887 ti,syscon-pcie-mode = <&pcie0_mode>; 888 bus-range = <0x0 0xff>; 889 num-viewport = <16>; 890 max-link-speed = <2>; 891 dma-coherent; 892 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 893 msi-map = <0x0 &gic_its 0x0 0x10000>; 894 device_type = "pci"; 895 status = "disabled"; 896 }; 897 898 pcie0_ep: pcie-ep@5500000 { 899 compatible = "ti,am654-pcie-ep"; 900 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 901 reg-names = "app", "dbics", "addr_space", "atu"; 902 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 903 ti,syscon-pcie-mode = <&pcie0_mode>; 904 num-ib-windows = <16>; 905 num-ob-windows = <16>; 906 max-link-speed = <2>; 907 dma-coherent; 908 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 909 status = "disabled"; 910 }; 911 912 pcie1_rc: pcie@5600000 { 913 compatible = "ti,am654-pcie-rc"; 914 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 915 reg-names = "app", "dbics", "config", "atu"; 916 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 917 #address-cells = <3>; 918 #size-cells = <2>; 919 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, 920 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 921 ti,syscon-pcie-id = <&pcie_devid>; 922 ti,syscon-pcie-mode = <&pcie1_mode>; 923 bus-range = <0x0 0xff>; 924 num-viewport = <16>; 925 max-link-speed = <2>; 926 dma-coherent; 927 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 928 msi-map = <0x0 &gic_its 0x10000 0x10000>; 929 device_type = "pci"; 930 status = "disabled"; 931 }; 932 933 pcie1_ep: pcie-ep@5600000 { 934 compatible = "ti,am654-pcie-ep"; 935 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 936 reg-names = "app", "dbics", "addr_space", "atu"; 937 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 938 ti,syscon-pcie-mode = <&pcie1_mode>; 939 num-ib-windows = <16>; 940 num-ob-windows = <16>; 941 max-link-speed = <2>; 942 dma-coherent; 943 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 944 status = "disabled"; 945 }; 946 947 mcasp0: mcasp@2b00000 { 948 compatible = "ti,am33xx-mcasp-audio"; 949 reg = <0x0 0x02b00000 0x0 0x2000>, 950 <0x0 0x02b08000 0x0 0x1000>; 951 reg-names = "mpu","dat"; 952 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 954 interrupt-names = "tx", "rx"; 955 956 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 957 dma-names = "tx", "rx"; 958 959 clocks = <&k3_clks 104 0>; 960 clock-names = "fck"; 961 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 962 status = "disabled"; 963 }; 964 965 mcasp1: mcasp@2b10000 { 966 compatible = "ti,am33xx-mcasp-audio"; 967 reg = <0x0 0x02b10000 0x0 0x2000>, 968 <0x0 0x02b18000 0x0 0x1000>; 969 reg-names = "mpu","dat"; 970 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "tx", "rx"; 973 974 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 975 dma-names = "tx", "rx"; 976 977 clocks = <&k3_clks 105 0>; 978 clock-names = "fck"; 979 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 980 status = "disabled"; 981 }; 982 983 mcasp2: mcasp@2b20000 { 984 compatible = "ti,am33xx-mcasp-audio"; 985 reg = <0x0 0x02b20000 0x0 0x2000>, 986 <0x0 0x02b28000 0x0 0x1000>; 987 reg-names = "mpu","dat"; 988 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 990 interrupt-names = "tx", "rx"; 991 992 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 993 dma-names = "tx", "rx"; 994 995 clocks = <&k3_clks 106 0>; 996 clock-names = "fck"; 997 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 998 status = "disabled"; 999 }; 1000 1001 cal: cal@6f03000 { 1002 compatible = "ti,am654-cal"; 1003 reg = <0x0 0x06f03000 0x0 0x400>, 1004 <0x0 0x06f03800 0x0 0x40>; 1005 reg-names = "cal_top", 1006 "cal_rx_core0"; 1007 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1008 ti,camerrx-control = <&scm_conf 0x40c0>; 1009 clock-names = "fck"; 1010 clocks = <&k3_clks 2 0>; 1011 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 1012 1013 ports { 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 csi2_0: port@0 { 1018 reg = <0>; 1019 }; 1020 }; 1021 }; 1022 1023 dss: dss@4a00000 { 1024 compatible = "ti,am65x-dss"; 1025 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 1026 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 1027 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 1028 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 1029 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 1030 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 1031 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 1032 reg-names = "common", "vidl1", "vid", 1033 "ovr1", "ovr2", "vp1", "vp2"; 1034 1035 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 1036 1037 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1038 1039 clocks = <&k3_clks 67 1>, 1040 <&k3_clks 216 1>, 1041 <&k3_clks 67 2>; 1042 clock-names = "fck", "vp1", "vp2"; 1043 1044 /* 1045 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 1046 * DIV1. See "Figure 12-3365. DSS Integration" 1047 * in AM65x TRM for details. 1048 */ 1049 assigned-clocks = <&k3_clks 67 2>; 1050 assigned-clock-parents = <&k3_clks 67 5>; 1051 1052 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 1053 1054 dma-coherent; 1055 1056 dss_ports: ports { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 }; 1060 }; 1061 1062 ehrpwm0: pwm@3000000 { 1063 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1064 #pwm-cells = <3>; 1065 reg = <0x0 0x3000000 0x0 0x100>; 1066 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 1067 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 1068 clock-names = "tbclk", "fck"; 1069 status = "disabled"; 1070 }; 1071 1072 ehrpwm1: pwm@3010000 { 1073 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1074 #pwm-cells = <3>; 1075 reg = <0x0 0x3010000 0x0 0x100>; 1076 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 1077 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 1078 clock-names = "tbclk", "fck"; 1079 status = "disabled"; 1080 }; 1081 1082 ehrpwm2: pwm@3020000 { 1083 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1084 #pwm-cells = <3>; 1085 reg = <0x0 0x3020000 0x0 0x100>; 1086 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 1087 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 1088 clock-names = "tbclk", "fck"; 1089 status = "disabled"; 1090 }; 1091 1092 ehrpwm3: pwm@3030000 { 1093 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1094 #pwm-cells = <3>; 1095 reg = <0x0 0x3030000 0x0 0x100>; 1096 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 1097 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 1098 clock-names = "tbclk", "fck"; 1099 status = "disabled"; 1100 }; 1101 1102 ehrpwm4: pwm@3040000 { 1103 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1104 #pwm-cells = <3>; 1105 reg = <0x0 0x3040000 0x0 0x100>; 1106 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 1107 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 1108 clock-names = "tbclk", "fck"; 1109 status = "disabled"; 1110 }; 1111 1112 ehrpwm5: pwm@3050000 { 1113 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1114 #pwm-cells = <3>; 1115 reg = <0x0 0x3050000 0x0 0x100>; 1116 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 1117 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 1118 clock-names = "tbclk", "fck"; 1119 status = "disabled"; 1120 }; 1121 1122 icssg0: icssg@b000000 { 1123 compatible = "ti,am654-icssg"; 1124 reg = <0x00 0xb000000 0x00 0x80000>; 1125 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1126 #address-cells = <1>; 1127 #size-cells = <1>; 1128 ranges = <0x0 0x00 0xb000000 0x80000>; 1129 1130 icssg0_mem: memories@0 { 1131 reg = <0x0 0x2000>, 1132 <0x2000 0x2000>, 1133 <0x10000 0x10000>; 1134 reg-names = "dram0", "dram1", 1135 "shrdram2"; 1136 }; 1137 1138 icssg0_cfg: cfg@26000 { 1139 compatible = "ti,pruss-cfg", "syscon"; 1140 reg = <0x26000 0x200>; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges = <0x0 0x26000 0x2000>; 1144 1145 clocks { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 icssg0_coreclk_mux: coreclk-mux@3c { 1150 reg = <0x3c>; 1151 #clock-cells = <0>; 1152 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 1153 <&k3_clks 62 3>; /* icssg0_iclk */ 1154 assigned-clocks = <&icssg0_coreclk_mux>; 1155 assigned-clock-parents = <&k3_clks 62 3>; 1156 }; 1157 1158 icssg0_iepclk_mux: iepclk-mux@30 { 1159 reg = <0x30>; 1160 #clock-cells = <0>; 1161 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 1162 <&icssg0_coreclk_mux>; /* core_clk */ 1163 assigned-clocks = <&icssg0_iepclk_mux>; 1164 assigned-clock-parents = <&icssg0_coreclk_mux>; 1165 }; 1166 }; 1167 }; 1168 1169 icssg0_mii_rt: mii-rt@32000 { 1170 compatible = "ti,pruss-mii", "syscon"; 1171 reg = <0x32000 0x100>; 1172 }; 1173 1174 icssg0_mii_g_rt: mii-g-rt@33000 { 1175 compatible = "ti,pruss-mii-g", "syscon"; 1176 reg = <0x33000 0x1000>; 1177 }; 1178 1179 icssg0_intc: interrupt-controller@20000 { 1180 compatible = "ti,icssg-intc"; 1181 reg = <0x20000 0x2000>; 1182 interrupt-controller; 1183 #interrupt-cells = <3>; 1184 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1192 interrupt-names = "host_intr0", "host_intr1", 1193 "host_intr2", "host_intr3", 1194 "host_intr4", "host_intr5", 1195 "host_intr6", "host_intr7"; 1196 }; 1197 1198 pru0_0: pru@34000 { 1199 compatible = "ti,am654-pru"; 1200 reg = <0x34000 0x4000>, 1201 <0x22000 0x100>, 1202 <0x22400 0x100>; 1203 reg-names = "iram", "control", "debug"; 1204 firmware-name = "am65x-pru0_0-fw"; 1205 }; 1206 1207 rtu0_0: rtu@4000 { 1208 compatible = "ti,am654-rtu"; 1209 reg = <0x4000 0x2000>, 1210 <0x23000 0x100>, 1211 <0x23400 0x100>; 1212 reg-names = "iram", "control", "debug"; 1213 firmware-name = "am65x-rtu0_0-fw"; 1214 }; 1215 1216 tx_pru0_0: txpru@a000 { 1217 compatible = "ti,am654-tx-pru"; 1218 reg = <0xa000 0x1800>, 1219 <0x25000 0x100>, 1220 <0x25400 0x100>; 1221 reg-names = "iram", "control", "debug"; 1222 firmware-name = "am65x-txpru0_0-fw"; 1223 }; 1224 1225 pru0_1: pru@38000 { 1226 compatible = "ti,am654-pru"; 1227 reg = <0x38000 0x4000>, 1228 <0x24000 0x100>, 1229 <0x24400 0x100>; 1230 reg-names = "iram", "control", "debug"; 1231 firmware-name = "am65x-pru0_1-fw"; 1232 }; 1233 1234 rtu0_1: rtu@6000 { 1235 compatible = "ti,am654-rtu"; 1236 reg = <0x6000 0x2000>, 1237 <0x23800 0x100>, 1238 <0x23c00 0x100>; 1239 reg-names = "iram", "control", "debug"; 1240 firmware-name = "am65x-rtu0_1-fw"; 1241 }; 1242 1243 tx_pru0_1: txpru@c000 { 1244 compatible = "ti,am654-tx-pru"; 1245 reg = <0xc000 0x1800>, 1246 <0x25800 0x100>, 1247 <0x25c00 0x100>; 1248 reg-names = "iram", "control", "debug"; 1249 firmware-name = "am65x-txpru0_1-fw"; 1250 }; 1251 1252 icssg0_mdio: mdio@32400 { 1253 compatible = "ti,davinci_mdio"; 1254 reg = <0x32400 0x100>; 1255 clocks = <&k3_clks 62 3>; 1256 clock-names = "fck"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 bus_freq = <1000000>; 1260 status = "disabled"; 1261 }; 1262 }; 1263 1264 icssg1: icssg@b100000 { 1265 compatible = "ti,am654-icssg"; 1266 reg = <0x00 0xb100000 0x00 0x80000>; 1267 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1268 #address-cells = <1>; 1269 #size-cells = <1>; 1270 ranges = <0x0 0x00 0xb100000 0x80000>; 1271 1272 icssg1_mem: memories@0 { 1273 reg = <0x0 0x2000>, 1274 <0x2000 0x2000>, 1275 <0x10000 0x10000>; 1276 reg-names = "dram0", "dram1", 1277 "shrdram2"; 1278 }; 1279 1280 icssg1_cfg: cfg@26000 { 1281 compatible = "ti,pruss-cfg", "syscon"; 1282 reg = <0x26000 0x200>; 1283 #address-cells = <1>; 1284 #size-cells = <1>; 1285 ranges = <0x0 0x26000 0x2000>; 1286 1287 clocks { 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 1291 icssg1_coreclk_mux: coreclk-mux@3c { 1292 reg = <0x3c>; 1293 #clock-cells = <0>; 1294 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1295 <&k3_clks 63 3>; /* icssg1_iclk */ 1296 assigned-clocks = <&icssg1_coreclk_mux>; 1297 assigned-clock-parents = <&k3_clks 63 3>; 1298 }; 1299 1300 icssg1_iepclk_mux: iepclk-mux@30 { 1301 reg = <0x30>; 1302 #clock-cells = <0>; 1303 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1304 <&icssg1_coreclk_mux>; /* core_clk */ 1305 assigned-clocks = <&icssg1_iepclk_mux>; 1306 assigned-clock-parents = <&icssg1_coreclk_mux>; 1307 }; 1308 }; 1309 }; 1310 1311 icssg1_mii_rt: mii-rt@32000 { 1312 compatible = "ti,pruss-mii", "syscon"; 1313 reg = <0x32000 0x100>; 1314 }; 1315 1316 icssg1_mii_g_rt: mii-g-rt@33000 { 1317 compatible = "ti,pruss-mii-g", "syscon"; 1318 reg = <0x33000 0x1000>; 1319 }; 1320 1321 icssg1_intc: interrupt-controller@20000 { 1322 compatible = "ti,icssg-intc"; 1323 reg = <0x20000 0x2000>; 1324 interrupt-controller; 1325 #interrupt-cells = <3>; 1326 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1334 interrupt-names = "host_intr0", "host_intr1", 1335 "host_intr2", "host_intr3", 1336 "host_intr4", "host_intr5", 1337 "host_intr6", "host_intr7"; 1338 }; 1339 1340 pru1_0: pru@34000 { 1341 compatible = "ti,am654-pru"; 1342 reg = <0x34000 0x4000>, 1343 <0x22000 0x100>, 1344 <0x22400 0x100>; 1345 reg-names = "iram", "control", "debug"; 1346 firmware-name = "am65x-pru1_0-fw"; 1347 }; 1348 1349 rtu1_0: rtu@4000 { 1350 compatible = "ti,am654-rtu"; 1351 reg = <0x4000 0x2000>, 1352 <0x23000 0x100>, 1353 <0x23400 0x100>; 1354 reg-names = "iram", "control", "debug"; 1355 firmware-name = "am65x-rtu1_0-fw"; 1356 }; 1357 1358 tx_pru1_0: txpru@a000 { 1359 compatible = "ti,am654-tx-pru"; 1360 reg = <0xa000 0x1800>, 1361 <0x25000 0x100>, 1362 <0x25400 0x100>; 1363 reg-names = "iram", "control", "debug"; 1364 firmware-name = "am65x-txpru1_0-fw"; 1365 }; 1366 1367 pru1_1: pru@38000 { 1368 compatible = "ti,am654-pru"; 1369 reg = <0x38000 0x4000>, 1370 <0x24000 0x100>, 1371 <0x24400 0x100>; 1372 reg-names = "iram", "control", "debug"; 1373 firmware-name = "am65x-pru1_1-fw"; 1374 }; 1375 1376 rtu1_1: rtu@6000 { 1377 compatible = "ti,am654-rtu"; 1378 reg = <0x6000 0x2000>, 1379 <0x23800 0x100>, 1380 <0x23c00 0x100>; 1381 reg-names = "iram", "control", "debug"; 1382 firmware-name = "am65x-rtu1_1-fw"; 1383 }; 1384 1385 tx_pru1_1: txpru@c000 { 1386 compatible = "ti,am654-tx-pru"; 1387 reg = <0xc000 0x1800>, 1388 <0x25800 0x100>, 1389 <0x25c00 0x100>; 1390 reg-names = "iram", "control", "debug"; 1391 firmware-name = "am65x-txpru1_1-fw"; 1392 }; 1393 1394 icssg1_mdio: mdio@32400 { 1395 compatible = "ti,davinci_mdio"; 1396 reg = <0x32400 0x100>; 1397 clocks = <&k3_clks 63 3>; 1398 clock-names = "fck"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 bus_freq = <1000000>; 1402 status = "disabled"; 1403 }; 1404 }; 1405 1406 icssg2: icssg@b200000 { 1407 compatible = "ti,am654-icssg"; 1408 reg = <0x00 0xb200000 0x00 0x80000>; 1409 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1410 #address-cells = <1>; 1411 #size-cells = <1>; 1412 ranges = <0x0 0x00 0xb200000 0x80000>; 1413 1414 icssg2_mem: memories@0 { 1415 reg = <0x0 0x2000>, 1416 <0x2000 0x2000>, 1417 <0x10000 0x10000>; 1418 reg-names = "dram0", "dram1", 1419 "shrdram2"; 1420 }; 1421 1422 icssg2_cfg: cfg@26000 { 1423 compatible = "ti,pruss-cfg", "syscon"; 1424 reg = <0x26000 0x200>; 1425 #address-cells = <1>; 1426 #size-cells = <1>; 1427 ranges = <0x0 0x26000 0x2000>; 1428 1429 clocks { 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 icssg2_coreclk_mux: coreclk-mux@3c { 1434 reg = <0x3c>; 1435 #clock-cells = <0>; 1436 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1437 <&k3_clks 64 3>; /* icssg1_iclk */ 1438 assigned-clocks = <&icssg2_coreclk_mux>; 1439 assigned-clock-parents = <&k3_clks 64 3>; 1440 }; 1441 1442 icssg2_iepclk_mux: iepclk-mux@30 { 1443 reg = <0x30>; 1444 #clock-cells = <0>; 1445 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1446 <&icssg2_coreclk_mux>; /* core_clk */ 1447 assigned-clocks = <&icssg2_iepclk_mux>; 1448 assigned-clock-parents = <&icssg2_coreclk_mux>; 1449 }; 1450 }; 1451 }; 1452 1453 icssg2_mii_rt: mii-rt@32000 { 1454 compatible = "ti,pruss-mii", "syscon"; 1455 reg = <0x32000 0x100>; 1456 }; 1457 1458 icssg2_mii_g_rt: mii-g-rt@33000 { 1459 compatible = "ti,pruss-mii-g", "syscon"; 1460 reg = <0x33000 0x1000>; 1461 }; 1462 1463 icssg2_intc: interrupt-controller@20000 { 1464 compatible = "ti,icssg-intc"; 1465 reg = <0x20000 0x2000>; 1466 interrupt-controller; 1467 #interrupt-cells = <3>; 1468 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1476 interrupt-names = "host_intr0", "host_intr1", 1477 "host_intr2", "host_intr3", 1478 "host_intr4", "host_intr5", 1479 "host_intr6", "host_intr7"; 1480 }; 1481 1482 pru2_0: pru@34000 { 1483 compatible = "ti,am654-pru"; 1484 reg = <0x34000 0x4000>, 1485 <0x22000 0x100>, 1486 <0x22400 0x100>; 1487 reg-names = "iram", "control", "debug"; 1488 firmware-name = "am65x-pru2_0-fw"; 1489 }; 1490 1491 rtu2_0: rtu@4000 { 1492 compatible = "ti,am654-rtu"; 1493 reg = <0x4000 0x2000>, 1494 <0x23000 0x100>, 1495 <0x23400 0x100>; 1496 reg-names = "iram", "control", "debug"; 1497 firmware-name = "am65x-rtu2_0-fw"; 1498 }; 1499 1500 tx_pru2_0: txpru@a000 { 1501 compatible = "ti,am654-tx-pru"; 1502 reg = <0xa000 0x1800>, 1503 <0x25000 0x100>, 1504 <0x25400 0x100>; 1505 reg-names = "iram", "control", "debug"; 1506 firmware-name = "am65x-txpru2_0-fw"; 1507 }; 1508 1509 pru2_1: pru@38000 { 1510 compatible = "ti,am654-pru"; 1511 reg = <0x38000 0x4000>, 1512 <0x24000 0x100>, 1513 <0x24400 0x100>; 1514 reg-names = "iram", "control", "debug"; 1515 firmware-name = "am65x-pru2_1-fw"; 1516 }; 1517 1518 rtu2_1: rtu@6000 { 1519 compatible = "ti,am654-rtu"; 1520 reg = <0x6000 0x2000>, 1521 <0x23800 0x100>, 1522 <0x23c00 0x100>; 1523 reg-names = "iram", "control", "debug"; 1524 firmware-name = "am65x-rtu2_1-fw"; 1525 }; 1526 1527 tx_pru2_1: txpru@c000 { 1528 compatible = "ti,am654-tx-pru"; 1529 reg = <0xc000 0x1800>, 1530 <0x25800 0x100>, 1531 <0x25c00 0x100>; 1532 reg-names = "iram", "control", "debug"; 1533 firmware-name = "am65x-txpru2_1-fw"; 1534 }; 1535 1536 icssg2_mdio: mdio@32400 { 1537 compatible = "ti,davinci_mdio"; 1538 reg = <0x32400 0x100>; 1539 clocks = <&k3_clks 64 3>; 1540 clock-names = "fck"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 bus_freq = <1000000>; 1544 status = "disabled"; 1545 }; 1546 }; 1547}; 1548