1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <48000000>; 92 current-speed = <115200>; 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 status = "disabled"; 95 }; 96 97 main_uart1: serial@2810000 { 98 compatible = "ti,am654-uart"; 99 reg = <0x00 0x02810000 0x00 0x100>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 status = "disabled"; 104 }; 105 106 main_uart2: serial@2820000 { 107 compatible = "ti,am654-uart"; 108 reg = <0x00 0x02820000 0x00 0x100>; 109 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 110 clock-frequency = <48000000>; 111 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 112 status = "disabled"; 113 }; 114 115 crypto: crypto@4e00000 { 116 compatible = "ti,am654-sa2ul"; 117 reg = <0x0 0x4e00000 0x0 0x1200>; 118 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 122 123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, 124 <&main_udmap 0x4003>; 125 dma-names = "tx", "rx1", "rx2"; 126 127 rng: rng@4e10000 { 128 compatible = "inside-secure,safexcel-eip76"; 129 reg = <0x0 0x4e10000 0x0 0x7d>; 130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; /* Used by OP-TEE */ 132 }; 133 }; 134 135 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 136 main_timerio_input: pinctrl@104200 { 137 compatible = "pinctrl-single"; 138 reg = <0x0 0x104200 0x0 0x30>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001ff>; 142 }; 143 144 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 145 main_timerio_output: pinctrl@104280 { 146 compatible = "pinctrl-single"; 147 reg = <0x0 0x104280 0x0 0x20>; 148 #pinctrl-cells = <1>; 149 pinctrl-single,register-width = <32>; 150 pinctrl-single,function-mask = <0x0000000f>; 151 }; 152 153 main_pmx0: pinctrl@11c000 { 154 compatible = "pinctrl-single"; 155 reg = <0x0 0x11c000 0x0 0x2e4>; 156 #pinctrl-cells = <1>; 157 pinctrl-single,register-width = <32>; 158 pinctrl-single,function-mask = <0xffffffff>; 159 }; 160 161 main_pmx1: pinctrl@11c2e8 { 162 compatible = "pinctrl-single"; 163 reg = <0x0 0x11c2e8 0x0 0x24>; 164 #pinctrl-cells = <1>; 165 pinctrl-single,register-width = <32>; 166 pinctrl-single,function-mask = <0xffffffff>; 167 }; 168 169 main_i2c0: i2c@2000000 { 170 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 171 reg = <0x0 0x2000000 0x0 0x100>; 172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 clock-names = "fck"; 176 clocks = <&k3_clks 110 1>; 177 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 178 status = "disabled"; 179 }; 180 181 main_i2c1: i2c@2010000 { 182 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 183 reg = <0x0 0x2010000 0x0 0x100>; 184 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 clock-names = "fck"; 188 clocks = <&k3_clks 111 1>; 189 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 190 status = "disabled"; 191 }; 192 193 main_i2c2: i2c@2020000 { 194 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 195 reg = <0x0 0x2020000 0x0 0x100>; 196 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clock-names = "fck"; 200 clocks = <&k3_clks 112 1>; 201 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 202 status = "disabled"; 203 }; 204 205 main_i2c3: i2c@2030000 { 206 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 207 reg = <0x0 0x2030000 0x0 0x100>; 208 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 clock-names = "fck"; 212 clocks = <&k3_clks 113 1>; 213 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 214 status = "disabled"; 215 }; 216 217 ecap0: pwm@3100000 { 218 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 219 #pwm-cells = <3>; 220 reg = <0x0 0x03100000 0x0 0x60>; 221 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 222 clocks = <&k3_clks 39 0>; 223 clock-names = "fck"; 224 status = "disabled"; 225 }; 226 227 main_spi0: spi@2100000 { 228 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 229 reg = <0x0 0x2100000 0x0 0x400>; 230 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 137 1>; 232 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 236 dma-names = "tx0", "rx0"; 237 status = "disabled"; 238 }; 239 240 main_spi1: spi@2110000 { 241 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 242 reg = <0x0 0x2110000 0x0 0x400>; 243 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&k3_clks 138 1>; 245 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 assigned-clocks = <&k3_clks 137 1>; 249 assigned-clock-rates = <48000000>; 250 status = "disabled"; 251 }; 252 253 main_spi2: spi@2120000 { 254 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 255 reg = <0x0 0x2120000 0x0 0x400>; 256 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&k3_clks 139 1>; 258 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 status = "disabled"; 262 }; 263 264 main_spi3: spi@2130000 { 265 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 266 reg = <0x0 0x2130000 0x0 0x400>; 267 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&k3_clks 140 1>; 269 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 status = "disabled"; 273 }; 274 275 main_spi4: spi@2140000 { 276 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 277 reg = <0x0 0x2140000 0x0 0x400>; 278 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 141 1>; 280 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 main_timer0: timer@2400000 { 287 compatible = "ti,am654-timer"; 288 reg = <0x00 0x2400000 0x00 0x400>; 289 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&k3_clks 23 0>; 291 clock-names = "fck"; 292 assigned-clocks = <&k3_clks 23 0>; 293 assigned-clock-parents = <&k3_clks 23 1>; 294 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; 295 ti,timer-pwm; 296 }; 297 298 main_timer1: timer@2410000 { 299 compatible = "ti,am654-timer"; 300 reg = <0x00 0x2410000 0x00 0x400>; 301 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&k3_clks 24 0>; 303 clock-names = "fck"; 304 assigned-clocks = <&k3_clks 24 0>; 305 assigned-clock-parents = <&k3_clks 24 1>; 306 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; 307 ti,timer-pwm; 308 }; 309 310 main_timer2: timer@2420000 { 311 compatible = "ti,am654-timer"; 312 reg = <0x00 0x2420000 0x00 0x400>; 313 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&k3_clks 27 0>; 315 clock-names = "fck"; 316 assigned-clocks = <&k3_clks 27 0>; 317 assigned-clock-parents = <&k3_clks 27 1>; 318 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 319 ti,timer-pwm; 320 }; 321 322 main_timer3: timer@2430000 { 323 compatible = "ti,am654-timer"; 324 reg = <0x00 0x2430000 0x00 0x400>; 325 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&k3_clks 28 0>; 327 clock-names = "fck"; 328 assigned-clocks = <&k3_clks 28 0>; 329 assigned-clock-parents = <&k3_clks 28 1>; 330 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 331 ti,timer-pwm; 332 }; 333 334 main_timer4: timer@2440000 { 335 compatible = "ti,am654-timer"; 336 reg = <0x00 0x2440000 0x00 0x400>; 337 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&k3_clks 29 0>; 339 clock-names = "fck"; 340 assigned-clocks = <&k3_clks 29 0>; 341 assigned-clock-parents = <&k3_clks 29 1>; 342 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 343 ti,timer-pwm; 344 }; 345 346 main_timer5: timer@2450000 { 347 compatible = "ti,am654-timer"; 348 reg = <0x00 0x2450000 0x00 0x400>; 349 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&k3_clks 30 0>; 351 clock-names = "fck"; 352 assigned-clocks = <&k3_clks 30 0>; 353 assigned-clock-parents = <&k3_clks 30 1>; 354 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; 355 ti,timer-pwm; 356 }; 357 358 main_timer6: timer@2460000 { 359 compatible = "ti,am654-timer"; 360 reg = <0x00 0x2460000 0x00 0x400>; 361 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&k3_clks 31 0>; 363 assigned-clocks = <&k3_clks 31 0>; 364 assigned-clock-parents = <&k3_clks 31 1>; 365 clock-names = "fck"; 366 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; 367 ti,timer-pwm; 368 }; 369 370 main_timer7: timer@2470000 { 371 compatible = "ti,am654-timer"; 372 reg = <0x00 0x2470000 0x00 0x400>; 373 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&k3_clks 32 0>; 375 clock-names = "fck"; 376 assigned-clocks = <&k3_clks 32 0>; 377 assigned-clock-parents = <&k3_clks 32 1>; 378 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; 379 ti,timer-pwm; 380 }; 381 382 main_timer8: timer@2480000 { 383 compatible = "ti,am654-timer"; 384 reg = <0x00 0x2480000 0x00 0x400>; 385 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&k3_clks 33 0>; 387 clock-names = "fck"; 388 assigned-clocks = <&k3_clks 33 0>; 389 assigned-clock-parents = <&k3_clks 33 1>; 390 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; 391 ti,timer-pwm; 392 }; 393 394 main_timer9: timer@2490000 { 395 compatible = "ti,am654-timer"; 396 reg = <0x00 0x2490000 0x00 0x400>; 397 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&k3_clks 34 0>; 399 clock-names = "fck"; 400 assigned-clocks = <&k3_clks 34 0>; 401 assigned-clock-parents = <&k3_clks 34 1>; 402 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; 403 ti,timer-pwm; 404 }; 405 406 main_timer10: timer@24a0000 { 407 compatible = "ti,am654-timer"; 408 reg = <0x00 0x24a0000 0x00 0x400>; 409 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&k3_clks 25 0>; 411 clock-names = "fck"; 412 assigned-clocks = <&k3_clks 25 0>; 413 assigned-clock-parents = <&k3_clks 25 1>; 414 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; 415 ti,timer-pwm; 416 }; 417 418 main_timer11: timer@24b0000 { 419 compatible = "ti,am654-timer"; 420 reg = <0x00 0x24b0000 0x00 0x400>; 421 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&k3_clks 26 0>; 423 clock-names = "fck"; 424 assigned-clocks = <&k3_clks 26 0>; 425 assigned-clock-parents = <&k3_clks 26 1>; 426 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 427 ti,timer-pwm; 428 }; 429 430 sdhci0: mmc@4f80000 { 431 compatible = "ti,am654-sdhci-5.1"; 432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 433 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 435 clock-names = "clk_ahb", "clk_xin"; 436 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 437 mmc-ddr-1_8v; 438 mmc-hs200-1_8v; 439 ti,otap-del-sel-legacy = <0x0>; 440 ti,otap-del-sel-mmc-hs = <0x0>; 441 ti,otap-del-sel-sd-hs = <0x0>; 442 ti,otap-del-sel-sdr12 = <0x0>; 443 ti,otap-del-sel-sdr25 = <0x0>; 444 ti,otap-del-sel-sdr50 = <0x8>; 445 ti,otap-del-sel-sdr104 = <0x7>; 446 ti,otap-del-sel-ddr50 = <0x5>; 447 ti,otap-del-sel-ddr52 = <0x5>; 448 ti,otap-del-sel-hs200 = <0x5>; 449 ti,otap-del-sel-hs400 = <0x0>; 450 ti,trm-icp = <0x8>; 451 dma-coherent; 452 }; 453 454 sdhci1: mmc@4fa0000 { 455 compatible = "ti,am654-sdhci-5.1"; 456 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 457 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 458 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 459 clock-names = "clk_ahb", "clk_xin"; 460 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 461 ti,otap-del-sel-legacy = <0x0>; 462 ti,otap-del-sel-mmc-hs = <0x0>; 463 ti,otap-del-sel-sd-hs = <0x0>; 464 ti,otap-del-sel-sdr12 = <0x0>; 465 ti,otap-del-sel-sdr25 = <0x0>; 466 ti,otap-del-sel-sdr50 = <0x8>; 467 ti,otap-del-sel-sdr104 = <0x7>; 468 ti,otap-del-sel-ddr50 = <0x4>; 469 ti,otap-del-sel-ddr52 = <0x4>; 470 ti,otap-del-sel-hs200 = <0x7>; 471 ti,clkbuf-sel = <0x7>; 472 ti,trm-icp = <0x8>; 473 dma-coherent; 474 }; 475 476 scm_conf: scm-conf@100000 { 477 compatible = "syscon", "simple-mfd"; 478 reg = <0 0x00100000 0 0x1c000>; 479 #address-cells = <1>; 480 #size-cells = <1>; 481 ranges = <0x0 0x0 0x00100000 0x1c000>; 482 483 serdes0_clk: clock@4080 { 484 compatible = "syscon"; 485 reg = <0x00004080 0x4>; 486 }; 487 488 serdes1_clk: clock@4090 { 489 compatible = "syscon"; 490 reg = <0x00004090 0x4>; 491 }; 492 493 serdes_mux: mux-controller { 494 compatible = "mmio-mux"; 495 #mux-control-cells = <1>; 496 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 497 <0x4090 0x3>; /* SERDES1 lane select */ 498 }; 499 500 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 501 compatible = "syscon"; 502 reg = <0x000041e0 0x14>; 503 }; 504 505 ehrpwm_tbclk: clock-controller@4140 { 506 compatible = "ti,am654-ehrpwm-tbclk"; 507 reg = <0x4140 0x18>; 508 #clock-cells = <1>; 509 }; 510 }; 511 512 dwc3_0: dwc3@4000000 { 513 compatible = "ti,am654-dwc3"; 514 reg = <0x0 0x4000000 0x0 0x4000>; 515 #address-cells = <1>; 516 #size-cells = <1>; 517 ranges = <0x0 0x0 0x4000000 0x20000>; 518 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 519 dma-coherent; 520 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 521 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 522 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 523 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 524 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 525 526 usb0: usb@10000 { 527 compatible = "snps,dwc3"; 528 reg = <0x10000 0x10000>; 529 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 532 interrupt-names = "peripheral", 533 "host", 534 "otg"; 535 maximum-speed = "high-speed"; 536 dr_mode = "otg"; 537 phys = <&usb0_phy>; 538 phy-names = "usb2-phy"; 539 snps,dis_u3_susphy_quirk; 540 }; 541 }; 542 543 usb0_phy: phy@4100000 { 544 compatible = "ti,am654-usb2", "ti,omap-usb2"; 545 reg = <0x0 0x4100000 0x0 0x54>; 546 syscon-phy-power = <&scm_conf 0x4000>; 547 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 548 clock-names = "wkupclk", "refclk"; 549 #phy-cells = <0>; 550 }; 551 552 dwc3_1: dwc3@4020000 { 553 compatible = "ti,am654-dwc3"; 554 reg = <0x0 0x4020000 0x0 0x4000>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges = <0x0 0x0 0x4020000 0x20000>; 558 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 559 dma-coherent; 560 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 561 clocks = <&k3_clks 152 2>; 562 assigned-clocks = <&k3_clks 152 2>; 563 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 564 565 usb1: usb@10000 { 566 compatible = "snps,dwc3"; 567 reg = <0x10000 0x10000>; 568 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "peripheral", 572 "host", 573 "otg"; 574 maximum-speed = "high-speed"; 575 dr_mode = "otg"; 576 phys = <&usb1_phy>; 577 phy-names = "usb2-phy"; 578 }; 579 }; 580 581 usb1_phy: phy@4110000 { 582 compatible = "ti,am654-usb2", "ti,omap-usb2"; 583 reg = <0x0 0x4110000 0x0 0x54>; 584 syscon-phy-power = <&scm_conf 0x4020>; 585 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 586 clock-names = "wkupclk", "refclk"; 587 #phy-cells = <0>; 588 }; 589 590 intr_main_gpio: interrupt-controller@a00000 { 591 compatible = "ti,sci-intr"; 592 reg = <0x0 0x00a00000 0x0 0x400>; 593 ti,intr-trigger-type = <1>; 594 interrupt-controller; 595 interrupt-parent = <&gic500>; 596 #interrupt-cells = <1>; 597 ti,sci = <&dmsc>; 598 ti,sci-dev-id = <100>; 599 ti,interrupt-ranges = <0 392 32>; 600 }; 601 602 main_navss: bus@30800000 { 603 compatible = "simple-mfd"; 604 #address-cells = <2>; 605 #size-cells = <2>; 606 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 607 dma-coherent; 608 dma-ranges; 609 610 ti,sci-dev-id = <118>; 611 612 intr_main_navss: interrupt-controller@310e0000 { 613 compatible = "ti,sci-intr"; 614 reg = <0x0 0x310e0000 0x0 0x2000>; 615 ti,intr-trigger-type = <4>; 616 interrupt-controller; 617 interrupt-parent = <&gic500>; 618 #interrupt-cells = <1>; 619 ti,sci = <&dmsc>; 620 ti,sci-dev-id = <182>; 621 ti,interrupt-ranges = <0 64 64>, 622 <64 448 64>; 623 }; 624 625 inta_main_udmass: interrupt-controller@33d00000 { 626 compatible = "ti,sci-inta"; 627 reg = <0x0 0x33d00000 0x0 0x100000>; 628 interrupt-controller; 629 interrupt-parent = <&intr_main_navss>; 630 msi-controller; 631 #interrupt-cells = <0>; 632 ti,sci = <&dmsc>; 633 ti,sci-dev-id = <179>; 634 ti,interrupt-ranges = <0 0 256>; 635 }; 636 637 secure_proxy_main: mailbox@32c00000 { 638 compatible = "ti,am654-secure-proxy"; 639 #mbox-cells = <1>; 640 reg-names = "target_data", "rt", "scfg"; 641 reg = <0x00 0x32c00000 0x00 0x100000>, 642 <0x00 0x32400000 0x00 0x100000>, 643 <0x00 0x32800000 0x00 0x100000>; 644 interrupt-names = "rx_011"; 645 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 646 }; 647 648 hwspinlock: spinlock@30e00000 { 649 compatible = "ti,am654-hwspinlock"; 650 reg = <0x00 0x30e00000 0x00 0x1000>; 651 #hwlock-cells = <1>; 652 }; 653 654 mailbox0_cluster0: mailbox@31f80000 { 655 compatible = "ti,am654-mailbox"; 656 reg = <0x00 0x31f80000 0x00 0x200>; 657 #mbox-cells = <1>; 658 ti,mbox-num-users = <4>; 659 ti,mbox-num-fifos = <16>; 660 interrupt-parent = <&intr_main_navss>; 661 status = "disabled"; 662 }; 663 664 mailbox0_cluster1: mailbox@31f81000 { 665 compatible = "ti,am654-mailbox"; 666 reg = <0x00 0x31f81000 0x00 0x200>; 667 #mbox-cells = <1>; 668 ti,mbox-num-users = <4>; 669 ti,mbox-num-fifos = <16>; 670 interrupt-parent = <&intr_main_navss>; 671 status = "disabled"; 672 }; 673 674 mailbox0_cluster2: mailbox@31f82000 { 675 compatible = "ti,am654-mailbox"; 676 reg = <0x00 0x31f82000 0x00 0x200>; 677 #mbox-cells = <1>; 678 ti,mbox-num-users = <4>; 679 ti,mbox-num-fifos = <16>; 680 interrupt-parent = <&intr_main_navss>; 681 status = "disabled"; 682 }; 683 684 mailbox0_cluster3: mailbox@31f83000 { 685 compatible = "ti,am654-mailbox"; 686 reg = <0x00 0x31f83000 0x00 0x200>; 687 #mbox-cells = <1>; 688 ti,mbox-num-users = <4>; 689 ti,mbox-num-fifos = <16>; 690 interrupt-parent = <&intr_main_navss>; 691 status = "disabled"; 692 }; 693 694 mailbox0_cluster4: mailbox@31f84000 { 695 compatible = "ti,am654-mailbox"; 696 reg = <0x00 0x31f84000 0x00 0x200>; 697 #mbox-cells = <1>; 698 ti,mbox-num-users = <4>; 699 ti,mbox-num-fifos = <16>; 700 interrupt-parent = <&intr_main_navss>; 701 status = "disabled"; 702 }; 703 704 mailbox0_cluster5: mailbox@31f85000 { 705 compatible = "ti,am654-mailbox"; 706 reg = <0x00 0x31f85000 0x00 0x200>; 707 #mbox-cells = <1>; 708 ti,mbox-num-users = <4>; 709 ti,mbox-num-fifos = <16>; 710 interrupt-parent = <&intr_main_navss>; 711 status = "disabled"; 712 }; 713 714 mailbox0_cluster6: mailbox@31f86000 { 715 compatible = "ti,am654-mailbox"; 716 reg = <0x00 0x31f86000 0x00 0x200>; 717 #mbox-cells = <1>; 718 ti,mbox-num-users = <4>; 719 ti,mbox-num-fifos = <16>; 720 interrupt-parent = <&intr_main_navss>; 721 status = "disabled"; 722 }; 723 724 mailbox0_cluster7: mailbox@31f87000 { 725 compatible = "ti,am654-mailbox"; 726 reg = <0x00 0x31f87000 0x00 0x200>; 727 #mbox-cells = <1>; 728 ti,mbox-num-users = <4>; 729 ti,mbox-num-fifos = <16>; 730 interrupt-parent = <&intr_main_navss>; 731 status = "disabled"; 732 }; 733 734 mailbox0_cluster8: mailbox@31f88000 { 735 compatible = "ti,am654-mailbox"; 736 reg = <0x00 0x31f88000 0x00 0x200>; 737 #mbox-cells = <1>; 738 ti,mbox-num-users = <4>; 739 ti,mbox-num-fifos = <16>; 740 interrupt-parent = <&intr_main_navss>; 741 status = "disabled"; 742 }; 743 744 mailbox0_cluster9: mailbox@31f89000 { 745 compatible = "ti,am654-mailbox"; 746 reg = <0x00 0x31f89000 0x00 0x200>; 747 #mbox-cells = <1>; 748 ti,mbox-num-users = <4>; 749 ti,mbox-num-fifos = <16>; 750 interrupt-parent = <&intr_main_navss>; 751 status = "disabled"; 752 }; 753 754 mailbox0_cluster10: mailbox@31f8a000 { 755 compatible = "ti,am654-mailbox"; 756 reg = <0x00 0x31f8a000 0x00 0x200>; 757 #mbox-cells = <1>; 758 ti,mbox-num-users = <4>; 759 ti,mbox-num-fifos = <16>; 760 interrupt-parent = <&intr_main_navss>; 761 status = "disabled"; 762 }; 763 764 mailbox0_cluster11: mailbox@31f8b000 { 765 compatible = "ti,am654-mailbox"; 766 reg = <0x00 0x31f8b000 0x00 0x200>; 767 #mbox-cells = <1>; 768 ti,mbox-num-users = <4>; 769 ti,mbox-num-fifos = <16>; 770 interrupt-parent = <&intr_main_navss>; 771 status = "disabled"; 772 }; 773 774 ringacc: ringacc@3c000000 { 775 compatible = "ti,am654-navss-ringacc"; 776 reg = <0x0 0x3c000000 0x0 0x400000>, 777 <0x0 0x38000000 0x0 0x400000>, 778 <0x0 0x31120000 0x0 0x100>, 779 <0x0 0x33000000 0x0 0x40000>, 780 <0x0 0x31080000 0x0 0x40000>; 781 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 782 ti,num-rings = <818>; 783 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 784 ti,sci = <&dmsc>; 785 ti,sci-dev-id = <187>; 786 msi-parent = <&inta_main_udmass>; 787 }; 788 789 main_udmap: dma-controller@31150000 { 790 compatible = "ti,am654-navss-main-udmap"; 791 reg = <0x0 0x31150000 0x0 0x100>, 792 <0x0 0x34000000 0x0 0x100000>, 793 <0x0 0x35000000 0x0 0x100000>; 794 reg-names = "gcfg", "rchanrt", "tchanrt"; 795 msi-parent = <&inta_main_udmass>; 796 #dma-cells = <1>; 797 798 ti,sci = <&dmsc>; 799 ti,sci-dev-id = <188>; 800 ti,ringacc = <&ringacc>; 801 802 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 803 <0xd>; /* TX_CHAN */ 804 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 805 <0xa>; /* RX_CHAN */ 806 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 807 }; 808 809 cpts@310d0000 { 810 compatible = "ti,am65-cpts"; 811 reg = <0x0 0x310d0000 0x0 0x400>; 812 reg-names = "cpts"; 813 clocks = <&main_cpts_mux>; 814 clock-names = "cpts"; 815 interrupts-extended = <&intr_main_navss 391>; 816 interrupt-names = "cpts"; 817 ti,cpts-periodic-outputs = <6>; 818 ti,cpts-ext-ts-inputs = <8>; 819 820 main_cpts_mux: refclk-mux { 821 #clock-cells = <0>; 822 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 823 <&k3_clks 118 6>, <&k3_clks 118 3>, 824 <&k3_clks 118 8>, <&k3_clks 118 14>, 825 <&k3_clks 120 3>, <&k3_clks 121 3>; 826 assigned-clocks = <&main_cpts_mux>; 827 assigned-clock-parents = <&k3_clks 118 5>; 828 }; 829 }; 830 }; 831 832 main_gpio0: gpio@600000 { 833 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 834 reg = <0x0 0x600000 0x0 0x100>; 835 gpio-controller; 836 #gpio-cells = <2>; 837 interrupt-parent = <&intr_main_gpio>; 838 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 839 interrupt-controller; 840 #interrupt-cells = <2>; 841 ti,ngpio = <96>; 842 ti,davinci-gpio-unbanked = <0>; 843 clocks = <&k3_clks 57 0>; 844 clock-names = "gpio"; 845 }; 846 847 main_gpio1: gpio@601000 { 848 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 849 reg = <0x0 0x601000 0x0 0x100>; 850 gpio-controller; 851 #gpio-cells = <2>; 852 interrupt-parent = <&intr_main_gpio>; 853 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 854 interrupt-controller; 855 #interrupt-cells = <2>; 856 ti,ngpio = <90>; 857 ti,davinci-gpio-unbanked = <0>; 858 clocks = <&k3_clks 58 0>; 859 clock-names = "gpio"; 860 }; 861 862 pcie0_rc: pcie@5500000 { 863 compatible = "ti,am654-pcie-rc"; 864 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 865 reg-names = "app", "dbics", "config", "atu"; 866 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 867 #address-cells = <3>; 868 #size-cells = <2>; 869 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, 870 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 871 ti,syscon-pcie-id = <&scm_conf 0x210>; 872 ti,syscon-pcie-mode = <&scm_conf 0x4060>; 873 bus-range = <0x0 0xff>; 874 num-viewport = <16>; 875 max-link-speed = <2>; 876 dma-coherent; 877 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 878 msi-map = <0x0 &gic_its 0x0 0x10000>; 879 device_type = "pci"; 880 status = "disabled"; 881 }; 882 883 pcie0_ep: pcie-ep@5500000 { 884 compatible = "ti,am654-pcie-ep"; 885 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 886 reg-names = "app", "dbics", "addr_space", "atu"; 887 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 888 ti,syscon-pcie-mode = <&scm_conf 0x4060>; 889 num-ib-windows = <16>; 890 num-ob-windows = <16>; 891 max-link-speed = <2>; 892 dma-coherent; 893 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 894 status = "disabled"; 895 }; 896 897 pcie1_rc: pcie@5600000 { 898 compatible = "ti,am654-pcie-rc"; 899 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 900 reg-names = "app", "dbics", "config", "atu"; 901 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 902 #address-cells = <3>; 903 #size-cells = <2>; 904 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, 905 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 906 ti,syscon-pcie-id = <&scm_conf 0x210>; 907 ti,syscon-pcie-mode = <&scm_conf 0x4070>; 908 bus-range = <0x0 0xff>; 909 num-viewport = <16>; 910 max-link-speed = <2>; 911 dma-coherent; 912 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 913 msi-map = <0x0 &gic_its 0x10000 0x10000>; 914 device_type = "pci"; 915 status = "disabled"; 916 }; 917 918 pcie1_ep: pcie-ep@5600000 { 919 compatible = "ti,am654-pcie-ep"; 920 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 921 reg-names = "app", "dbics", "addr_space", "atu"; 922 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 923 ti,syscon-pcie-mode = <&scm_conf 0x4070>; 924 num-ib-windows = <16>; 925 num-ob-windows = <16>; 926 max-link-speed = <2>; 927 dma-coherent; 928 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 929 status = "disabled"; 930 }; 931 932 mcasp0: mcasp@2b00000 { 933 compatible = "ti,am33xx-mcasp-audio"; 934 reg = <0x0 0x02b00000 0x0 0x2000>, 935 <0x0 0x02b08000 0x0 0x1000>; 936 reg-names = "mpu","dat"; 937 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 939 interrupt-names = "tx", "rx"; 940 941 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 942 dma-names = "tx", "rx"; 943 944 clocks = <&k3_clks 104 0>; 945 clock-names = "fck"; 946 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 947 status = "disabled"; 948 }; 949 950 mcasp1: mcasp@2b10000 { 951 compatible = "ti,am33xx-mcasp-audio"; 952 reg = <0x0 0x02b10000 0x0 0x2000>, 953 <0x0 0x02b18000 0x0 0x1000>; 954 reg-names = "mpu","dat"; 955 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "tx", "rx"; 958 959 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 960 dma-names = "tx", "rx"; 961 962 clocks = <&k3_clks 105 0>; 963 clock-names = "fck"; 964 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 965 status = "disabled"; 966 }; 967 968 mcasp2: mcasp@2b20000 { 969 compatible = "ti,am33xx-mcasp-audio"; 970 reg = <0x0 0x02b20000 0x0 0x2000>, 971 <0x0 0x02b28000 0x0 0x1000>; 972 reg-names = "mpu","dat"; 973 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "tx", "rx"; 976 977 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 978 dma-names = "tx", "rx"; 979 980 clocks = <&k3_clks 106 0>; 981 clock-names = "fck"; 982 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 983 status = "disabled"; 984 }; 985 986 cal: cal@6f03000 { 987 compatible = "ti,am654-cal"; 988 reg = <0x0 0x06f03000 0x0 0x400>, 989 <0x0 0x06f03800 0x0 0x40>; 990 reg-names = "cal_top", 991 "cal_rx_core0"; 992 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 993 ti,camerrx-control = <&scm_conf 0x40c0>; 994 clock-names = "fck"; 995 clocks = <&k3_clks 2 0>; 996 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 997 998 ports { 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 csi2_0: port@0 { 1003 reg = <0>; 1004 }; 1005 }; 1006 }; 1007 1008 dss: dss@4a00000 { 1009 compatible = "ti,am65x-dss"; 1010 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 1011 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 1012 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 1013 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 1014 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 1015 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 1016 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ 1017 <0x0 0x04a01000 0x0 0x1000>; /* common1 */ 1018 reg-names = "common", "vidl1", "vid", 1019 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1020 1021 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 1022 1023 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1024 1025 clocks = <&k3_clks 67 1>, 1026 <&k3_clks 216 1>, 1027 <&k3_clks 67 2>; 1028 clock-names = "fck", "vp1", "vp2"; 1029 1030 /* 1031 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 1032 * DIV1. See "Figure 12-3365. DSS Integration" 1033 * in AM65x TRM for details. 1034 */ 1035 assigned-clocks = <&k3_clks 67 2>; 1036 assigned-clock-parents = <&k3_clks 67 5>; 1037 1038 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1039 1040 dma-coherent; 1041 1042 dss_ports: ports { 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 }; 1046 }; 1047 1048 ehrpwm0: pwm@3000000 { 1049 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1050 #pwm-cells = <3>; 1051 reg = <0x0 0x3000000 0x0 0x100>; 1052 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 1053 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 1054 clock-names = "tbclk", "fck"; 1055 status = "disabled"; 1056 }; 1057 1058 ehrpwm1: pwm@3010000 { 1059 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1060 #pwm-cells = <3>; 1061 reg = <0x0 0x3010000 0x0 0x100>; 1062 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 1063 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 1064 clock-names = "tbclk", "fck"; 1065 status = "disabled"; 1066 }; 1067 1068 ehrpwm2: pwm@3020000 { 1069 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1070 #pwm-cells = <3>; 1071 reg = <0x0 0x3020000 0x0 0x100>; 1072 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 1073 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 1074 clock-names = "tbclk", "fck"; 1075 status = "disabled"; 1076 }; 1077 1078 ehrpwm3: pwm@3030000 { 1079 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1080 #pwm-cells = <3>; 1081 reg = <0x0 0x3030000 0x0 0x100>; 1082 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 1083 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 1084 clock-names = "tbclk", "fck"; 1085 status = "disabled"; 1086 }; 1087 1088 ehrpwm4: pwm@3040000 { 1089 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1090 #pwm-cells = <3>; 1091 reg = <0x0 0x3040000 0x0 0x100>; 1092 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 1093 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 1094 clock-names = "tbclk", "fck"; 1095 status = "disabled"; 1096 }; 1097 1098 ehrpwm5: pwm@3050000 { 1099 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1100 #pwm-cells = <3>; 1101 reg = <0x0 0x3050000 0x0 0x100>; 1102 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 1103 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 1104 clock-names = "tbclk", "fck"; 1105 status = "disabled"; 1106 }; 1107 1108 icssg0: icssg@b000000 { 1109 compatible = "ti,am654-icssg"; 1110 reg = <0x00 0xb000000 0x00 0x80000>; 1111 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1112 #address-cells = <1>; 1113 #size-cells = <1>; 1114 ranges = <0x0 0x00 0xb000000 0x80000>; 1115 1116 icssg0_mem: memories@0 { 1117 reg = <0x0 0x2000>, 1118 <0x2000 0x2000>, 1119 <0x10000 0x10000>; 1120 reg-names = "dram0", "dram1", 1121 "shrdram2"; 1122 }; 1123 1124 icssg0_cfg: cfg@26000 { 1125 compatible = "ti,pruss-cfg", "syscon"; 1126 reg = <0x26000 0x200>; 1127 #address-cells = <1>; 1128 #size-cells = <1>; 1129 ranges = <0x0 0x26000 0x2000>; 1130 1131 clocks { 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 1135 icssg0_coreclk_mux: coreclk-mux@3c { 1136 reg = <0x3c>; 1137 #clock-cells = <0>; 1138 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 1139 <&k3_clks 62 3>; /* icssg0_iclk */ 1140 assigned-clocks = <&icssg0_coreclk_mux>; 1141 assigned-clock-parents = <&k3_clks 62 3>; 1142 }; 1143 1144 icssg0_iepclk_mux: iepclk-mux@30 { 1145 reg = <0x30>; 1146 #clock-cells = <0>; 1147 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 1148 <&icssg0_coreclk_mux>; /* core_clk */ 1149 assigned-clocks = <&icssg0_iepclk_mux>; 1150 assigned-clock-parents = <&icssg0_coreclk_mux>; 1151 }; 1152 }; 1153 }; 1154 1155 icssg0_mii_rt: mii-rt@32000 { 1156 compatible = "ti,pruss-mii", "syscon"; 1157 reg = <0x32000 0x100>; 1158 }; 1159 1160 icssg0_mii_g_rt: mii-g-rt@33000 { 1161 compatible = "ti,pruss-mii-g", "syscon"; 1162 reg = <0x33000 0x1000>; 1163 }; 1164 1165 icssg0_intc: interrupt-controller@20000 { 1166 compatible = "ti,icssg-intc"; 1167 reg = <0x20000 0x2000>; 1168 interrupt-controller; 1169 #interrupt-cells = <3>; 1170 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1178 interrupt-names = "host_intr0", "host_intr1", 1179 "host_intr2", "host_intr3", 1180 "host_intr4", "host_intr5", 1181 "host_intr6", "host_intr7"; 1182 }; 1183 1184 pru0_0: pru@34000 { 1185 compatible = "ti,am654-pru"; 1186 reg = <0x34000 0x4000>, 1187 <0x22000 0x100>, 1188 <0x22400 0x100>; 1189 reg-names = "iram", "control", "debug"; 1190 firmware-name = "am65x-pru0_0-fw"; 1191 }; 1192 1193 rtu0_0: rtu@4000 { 1194 compatible = "ti,am654-rtu"; 1195 reg = <0x4000 0x2000>, 1196 <0x23000 0x100>, 1197 <0x23400 0x100>; 1198 reg-names = "iram", "control", "debug"; 1199 firmware-name = "am65x-rtu0_0-fw"; 1200 }; 1201 1202 tx_pru0_0: txpru@a000 { 1203 compatible = "ti,am654-tx-pru"; 1204 reg = <0xa000 0x1800>, 1205 <0x25000 0x100>, 1206 <0x25400 0x100>; 1207 reg-names = "iram", "control", "debug"; 1208 firmware-name = "am65x-txpru0_0-fw"; 1209 }; 1210 1211 pru0_1: pru@38000 { 1212 compatible = "ti,am654-pru"; 1213 reg = <0x38000 0x4000>, 1214 <0x24000 0x100>, 1215 <0x24400 0x100>; 1216 reg-names = "iram", "control", "debug"; 1217 firmware-name = "am65x-pru0_1-fw"; 1218 }; 1219 1220 rtu0_1: rtu@6000 { 1221 compatible = "ti,am654-rtu"; 1222 reg = <0x6000 0x2000>, 1223 <0x23800 0x100>, 1224 <0x23c00 0x100>; 1225 reg-names = "iram", "control", "debug"; 1226 firmware-name = "am65x-rtu0_1-fw"; 1227 }; 1228 1229 tx_pru0_1: txpru@c000 { 1230 compatible = "ti,am654-tx-pru"; 1231 reg = <0xc000 0x1800>, 1232 <0x25800 0x100>, 1233 <0x25c00 0x100>; 1234 reg-names = "iram", "control", "debug"; 1235 firmware-name = "am65x-txpru0_1-fw"; 1236 }; 1237 1238 icssg0_mdio: mdio@32400 { 1239 compatible = "ti,davinci_mdio"; 1240 reg = <0x32400 0x100>; 1241 clocks = <&k3_clks 62 3>; 1242 clock-names = "fck"; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 bus_freq = <1000000>; 1246 status = "disabled"; 1247 }; 1248 }; 1249 1250 icssg1: icssg@b100000 { 1251 compatible = "ti,am654-icssg"; 1252 reg = <0x00 0xb100000 0x00 0x80000>; 1253 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1254 #address-cells = <1>; 1255 #size-cells = <1>; 1256 ranges = <0x0 0x00 0xb100000 0x80000>; 1257 1258 icssg1_mem: memories@0 { 1259 reg = <0x0 0x2000>, 1260 <0x2000 0x2000>, 1261 <0x10000 0x10000>; 1262 reg-names = "dram0", "dram1", 1263 "shrdram2"; 1264 }; 1265 1266 icssg1_cfg: cfg@26000 { 1267 compatible = "ti,pruss-cfg", "syscon"; 1268 reg = <0x26000 0x200>; 1269 #address-cells = <1>; 1270 #size-cells = <1>; 1271 ranges = <0x0 0x26000 0x2000>; 1272 1273 clocks { 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 1277 icssg1_coreclk_mux: coreclk-mux@3c { 1278 reg = <0x3c>; 1279 #clock-cells = <0>; 1280 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1281 <&k3_clks 63 3>; /* icssg1_iclk */ 1282 assigned-clocks = <&icssg1_coreclk_mux>; 1283 assigned-clock-parents = <&k3_clks 63 3>; 1284 }; 1285 1286 icssg1_iepclk_mux: iepclk-mux@30 { 1287 reg = <0x30>; 1288 #clock-cells = <0>; 1289 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1290 <&icssg1_coreclk_mux>; /* core_clk */ 1291 assigned-clocks = <&icssg1_iepclk_mux>; 1292 assigned-clock-parents = <&icssg1_coreclk_mux>; 1293 }; 1294 }; 1295 }; 1296 1297 icssg1_mii_rt: mii-rt@32000 { 1298 compatible = "ti,pruss-mii", "syscon"; 1299 reg = <0x32000 0x100>; 1300 }; 1301 1302 icssg1_mii_g_rt: mii-g-rt@33000 { 1303 compatible = "ti,pruss-mii-g", "syscon"; 1304 reg = <0x33000 0x1000>; 1305 }; 1306 1307 icssg1_intc: interrupt-controller@20000 { 1308 compatible = "ti,icssg-intc"; 1309 reg = <0x20000 0x2000>; 1310 interrupt-controller; 1311 #interrupt-cells = <3>; 1312 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1320 interrupt-names = "host_intr0", "host_intr1", 1321 "host_intr2", "host_intr3", 1322 "host_intr4", "host_intr5", 1323 "host_intr6", "host_intr7"; 1324 }; 1325 1326 pru1_0: pru@34000 { 1327 compatible = "ti,am654-pru"; 1328 reg = <0x34000 0x4000>, 1329 <0x22000 0x100>, 1330 <0x22400 0x100>; 1331 reg-names = "iram", "control", "debug"; 1332 firmware-name = "am65x-pru1_0-fw"; 1333 }; 1334 1335 rtu1_0: rtu@4000 { 1336 compatible = "ti,am654-rtu"; 1337 reg = <0x4000 0x2000>, 1338 <0x23000 0x100>, 1339 <0x23400 0x100>; 1340 reg-names = "iram", "control", "debug"; 1341 firmware-name = "am65x-rtu1_0-fw"; 1342 }; 1343 1344 tx_pru1_0: txpru@a000 { 1345 compatible = "ti,am654-tx-pru"; 1346 reg = <0xa000 0x1800>, 1347 <0x25000 0x100>, 1348 <0x25400 0x100>; 1349 reg-names = "iram", "control", "debug"; 1350 firmware-name = "am65x-txpru1_0-fw"; 1351 }; 1352 1353 pru1_1: pru@38000 { 1354 compatible = "ti,am654-pru"; 1355 reg = <0x38000 0x4000>, 1356 <0x24000 0x100>, 1357 <0x24400 0x100>; 1358 reg-names = "iram", "control", "debug"; 1359 firmware-name = "am65x-pru1_1-fw"; 1360 }; 1361 1362 rtu1_1: rtu@6000 { 1363 compatible = "ti,am654-rtu"; 1364 reg = <0x6000 0x2000>, 1365 <0x23800 0x100>, 1366 <0x23c00 0x100>; 1367 reg-names = "iram", "control", "debug"; 1368 firmware-name = "am65x-rtu1_1-fw"; 1369 }; 1370 1371 tx_pru1_1: txpru@c000 { 1372 compatible = "ti,am654-tx-pru"; 1373 reg = <0xc000 0x1800>, 1374 <0x25800 0x100>, 1375 <0x25c00 0x100>; 1376 reg-names = "iram", "control", "debug"; 1377 firmware-name = "am65x-txpru1_1-fw"; 1378 }; 1379 1380 icssg1_mdio: mdio@32400 { 1381 compatible = "ti,davinci_mdio"; 1382 reg = <0x32400 0x100>; 1383 clocks = <&k3_clks 63 3>; 1384 clock-names = "fck"; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 bus_freq = <1000000>; 1388 status = "disabled"; 1389 }; 1390 }; 1391 1392 icssg2: icssg@b200000 { 1393 compatible = "ti,am654-icssg"; 1394 reg = <0x00 0xb200000 0x00 0x80000>; 1395 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1396 #address-cells = <1>; 1397 #size-cells = <1>; 1398 ranges = <0x0 0x00 0xb200000 0x80000>; 1399 1400 icssg2_mem: memories@0 { 1401 reg = <0x0 0x2000>, 1402 <0x2000 0x2000>, 1403 <0x10000 0x10000>; 1404 reg-names = "dram0", "dram1", 1405 "shrdram2"; 1406 }; 1407 1408 icssg2_cfg: cfg@26000 { 1409 compatible = "ti,pruss-cfg", "syscon"; 1410 reg = <0x26000 0x200>; 1411 #address-cells = <1>; 1412 #size-cells = <1>; 1413 ranges = <0x0 0x26000 0x2000>; 1414 1415 clocks { 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 1419 icssg2_coreclk_mux: coreclk-mux@3c { 1420 reg = <0x3c>; 1421 #clock-cells = <0>; 1422 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1423 <&k3_clks 64 3>; /* icssg1_iclk */ 1424 assigned-clocks = <&icssg2_coreclk_mux>; 1425 assigned-clock-parents = <&k3_clks 64 3>; 1426 }; 1427 1428 icssg2_iepclk_mux: iepclk-mux@30 { 1429 reg = <0x30>; 1430 #clock-cells = <0>; 1431 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1432 <&icssg2_coreclk_mux>; /* core_clk */ 1433 assigned-clocks = <&icssg2_iepclk_mux>; 1434 assigned-clock-parents = <&icssg2_coreclk_mux>; 1435 }; 1436 }; 1437 }; 1438 1439 icssg2_mii_rt: mii-rt@32000 { 1440 compatible = "ti,pruss-mii", "syscon"; 1441 reg = <0x32000 0x100>; 1442 }; 1443 1444 icssg2_mii_g_rt: mii-g-rt@33000 { 1445 compatible = "ti,pruss-mii-g", "syscon"; 1446 reg = <0x33000 0x1000>; 1447 }; 1448 1449 icssg2_intc: interrupt-controller@20000 { 1450 compatible = "ti,icssg-intc"; 1451 reg = <0x20000 0x2000>; 1452 interrupt-controller; 1453 #interrupt-cells = <3>; 1454 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1462 interrupt-names = "host_intr0", "host_intr1", 1463 "host_intr2", "host_intr3", 1464 "host_intr4", "host_intr5", 1465 "host_intr6", "host_intr7"; 1466 }; 1467 1468 pru2_0: pru@34000 { 1469 compatible = "ti,am654-pru"; 1470 reg = <0x34000 0x4000>, 1471 <0x22000 0x100>, 1472 <0x22400 0x100>; 1473 reg-names = "iram", "control", "debug"; 1474 firmware-name = "am65x-pru2_0-fw"; 1475 }; 1476 1477 rtu2_0: rtu@4000 { 1478 compatible = "ti,am654-rtu"; 1479 reg = <0x4000 0x2000>, 1480 <0x23000 0x100>, 1481 <0x23400 0x100>; 1482 reg-names = "iram", "control", "debug"; 1483 firmware-name = "am65x-rtu2_0-fw"; 1484 }; 1485 1486 tx_pru2_0: txpru@a000 { 1487 compatible = "ti,am654-tx-pru"; 1488 reg = <0xa000 0x1800>, 1489 <0x25000 0x100>, 1490 <0x25400 0x100>; 1491 reg-names = "iram", "control", "debug"; 1492 firmware-name = "am65x-txpru2_0-fw"; 1493 }; 1494 1495 pru2_1: pru@38000 { 1496 compatible = "ti,am654-pru"; 1497 reg = <0x38000 0x4000>, 1498 <0x24000 0x100>, 1499 <0x24400 0x100>; 1500 reg-names = "iram", "control", "debug"; 1501 firmware-name = "am65x-pru2_1-fw"; 1502 }; 1503 1504 rtu2_1: rtu@6000 { 1505 compatible = "ti,am654-rtu"; 1506 reg = <0x6000 0x2000>, 1507 <0x23800 0x100>, 1508 <0x23c00 0x100>; 1509 reg-names = "iram", "control", "debug"; 1510 firmware-name = "am65x-rtu2_1-fw"; 1511 }; 1512 1513 tx_pru2_1: txpru@c000 { 1514 compatible = "ti,am654-tx-pru"; 1515 reg = <0xc000 0x1800>, 1516 <0x25800 0x100>, 1517 <0x25c00 0x100>; 1518 reg-names = "iram", "control", "debug"; 1519 firmware-name = "am65x-txpru2_1-fw"; 1520 }; 1521 1522 icssg2_mdio: mdio@32400 { 1523 compatible = "ti,davinci_mdio"; 1524 reg = <0x32400 0x100>; 1525 clocks = <&k3_clks 64 3>; 1526 clock-names = "fck"; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 bus_freq = <1000000>; 1530 status = "disabled"; 1531 }; 1532 }; 1533}; 1534