1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>; /* GICR */ 39 /* 40 * vcpumntirq: 41 * virtual CPU interface maintenance interrupt 42 */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: gic-its@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 serdes0: serdes@900000 { 55 compatible = "ti,phy-am654-serdes"; 56 reg = <0x0 0x900000 0x0 0x2000>; 57 reg-names = "serdes"; 58 #phy-cells = <2>; 59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 64 ti,serdes-clk = <&serdes0_clk>; 65 #clock-cells = <1>; 66 mux-controls = <&serdes_mux 0>; 67 }; 68 69 serdes1: serdes@910000 { 70 compatible = "ti,phy-am654-serdes"; 71 reg = <0x0 0x910000 0x0 0x2000>; 72 reg-names = "serdes"; 73 #phy-cells = <2>; 74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 75 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 79 ti,serdes-clk = <&serdes1_clk>; 80 #clock-cells = <1>; 81 mux-controls = <&serdes_mux 1>; 82 }; 83 84 main_uart0: serial@2800000 { 85 compatible = "ti,am654-uart"; 86 reg = <0x00 0x02800000 0x00 0x100>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 90 clock-frequency = <48000000>; 91 current-speed = <115200>; 92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 93 }; 94 95 main_uart1: serial@2810000 { 96 compatible = "ti,am654-uart"; 97 reg = <0x00 0x02810000 0x00 0x100>; 98 reg-shift = <2>; 99 reg-io-width = <4>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 }; 104 105 main_uart2: serial@2820000 { 106 compatible = "ti,am654-uart"; 107 reg = <0x00 0x02820000 0x00 0x100>; 108 reg-shift = <2>; 109 reg-io-width = <4>; 110 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 111 clock-frequency = <48000000>; 112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 113 }; 114 115 main_pmx0: pinmux@11c000 { 116 compatible = "pinctrl-single"; 117 reg = <0x0 0x11c000 0x0 0x2e4>; 118 #pinctrl-cells = <1>; 119 pinctrl-single,register-width = <32>; 120 pinctrl-single,function-mask = <0xffffffff>; 121 }; 122 123 main_pmx1: pinmux@11c2e8 { 124 compatible = "pinctrl-single"; 125 reg = <0x0 0x11c2e8 0x0 0x24>; 126 #pinctrl-cells = <1>; 127 pinctrl-single,register-width = <32>; 128 pinctrl-single,function-mask = <0xffffffff>; 129 }; 130 131 main_i2c0: i2c@2000000 { 132 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 133 reg = <0x0 0x2000000 0x0 0x100>; 134 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 clock-names = "fck"; 138 clocks = <&k3_clks 110 1>; 139 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 140 }; 141 142 main_i2c1: i2c@2010000 { 143 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 144 reg = <0x0 0x2010000 0x0 0x100>; 145 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clock-names = "fck"; 149 clocks = <&k3_clks 111 1>; 150 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 151 }; 152 153 main_i2c2: i2c@2020000 { 154 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 155 reg = <0x0 0x2020000 0x0 0x100>; 156 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clock-names = "fck"; 160 clocks = <&k3_clks 112 1>; 161 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 162 }; 163 164 main_i2c3: i2c@2030000 { 165 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 166 reg = <0x0 0x2030000 0x0 0x100>; 167 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clock-names = "fck"; 171 clocks = <&k3_clks 113 1>; 172 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 173 }; 174 175 ecap0: pwm@3100000 { 176 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 177 #pwm-cells = <3>; 178 reg = <0x0 0x03100000 0x0 0x60>; 179 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 180 clocks = <&k3_clks 39 0>; 181 clock-names = "fck"; 182 }; 183 184 main_spi0: spi@2100000 { 185 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 186 reg = <0x0 0x2100000 0x0 0x400>; 187 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&k3_clks 137 1>; 189 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 }; 193 194 main_spi1: spi@2110000 { 195 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 196 reg = <0x0 0x2110000 0x0 0x400>; 197 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&k3_clks 138 1>; 199 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 assigned-clocks = <&k3_clks 137 1>; 203 assigned-clock-rates = <48000000>; 204 }; 205 206 main_spi2: spi@2120000 { 207 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 208 reg = <0x0 0x2120000 0x0 0x400>; 209 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&k3_clks 139 1>; 211 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 }; 215 216 main_spi3: spi@2130000 { 217 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 218 reg = <0x0 0x2130000 0x0 0x400>; 219 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&k3_clks 140 1>; 221 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 }; 225 226 main_spi4: spi@2140000 { 227 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 228 reg = <0x0 0x2140000 0x0 0x400>; 229 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&k3_clks 141 1>; 231 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 }; 235 236 sdhci0: sdhci@4f80000 { 237 compatible = "ti,am654-sdhci-5.1"; 238 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 239 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 240 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 241 clock-names = "clk_ahb", "clk_xin"; 242 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 243 mmc-ddr-1_8v; 244 mmc-hs200-1_8v; 245 ti,otap-del-sel = <0x2>; 246 ti,trm-icp = <0x8>; 247 dma-coherent; 248 }; 249 250 scm_conf: scm_conf@100000 { 251 compatible = "syscon", "simple-mfd"; 252 reg = <0 0x00100000 0 0x1c000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0x0 0x0 0x00100000 0x1c000>; 256 257 pcie0_mode: pcie-mode@4060 { 258 compatible = "syscon"; 259 reg = <0x00004060 0x4>; 260 }; 261 262 pcie1_mode: pcie-mode@4070 { 263 compatible = "syscon"; 264 reg = <0x00004070 0x4>; 265 }; 266 267 pcie_devid: pcie-devid@210 { 268 compatible = "syscon"; 269 reg = <0x00000210 0x4>; 270 }; 271 272 serdes0_clk: serdes_clk@4080 { 273 compatible = "syscon"; 274 reg = <0x00004080 0x4>; 275 }; 276 277 serdes1_clk: serdes_clk@4090 { 278 compatible = "syscon"; 279 reg = <0x00004090 0x4>; 280 }; 281 282 serdes_mux: mux-controller { 283 compatible = "mmio-mux"; 284 #mux-control-cells = <1>; 285 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 286 <0x4090 0x3>; /* SERDES1 lane select */ 287 }; 288 }; 289 290 dwc3_0: dwc3@4000000 { 291 compatible = "ti,am654-dwc3"; 292 reg = <0x0 0x4000000 0x0 0x4000>; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 ranges = <0x0 0x0 0x4000000 0x20000>; 296 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 297 dma-coherent; 298 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 299 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 300 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 301 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 302 303 usb0: usb@10000 { 304 compatible = "snps,dwc3"; 305 reg = <0x10000 0x10000>; 306 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 309 interrupt-names = "peripheral", 310 "host", 311 "otg"; 312 maximum-speed = "high-speed"; 313 dr_mode = "otg"; 314 phys = <&usb0_phy>; 315 phy-names = "usb2-phy"; 316 snps,dis_u3_susphy_quirk; 317 }; 318 }; 319 320 usb0_phy: phy@4100000 { 321 compatible = "ti,am654-usb2", "ti,omap-usb2"; 322 reg = <0x0 0x4100000 0x0 0x54>; 323 syscon-phy-power = <&scm_conf 0x4000>; 324 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 325 clock-names = "wkupclk", "refclk"; 326 #phy-cells = <0>; 327 }; 328 329 dwc3_1: dwc3@4020000 { 330 compatible = "ti,am654-dwc3"; 331 reg = <0x0 0x4020000 0x0 0x4000>; 332 #address-cells = <1>; 333 #size-cells = <1>; 334 ranges = <0x0 0x0 0x4020000 0x20000>; 335 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 336 dma-coherent; 337 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 338 assigned-clocks = <&k3_clks 152 2>; 339 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 340 341 usb1: usb@10000 { 342 compatible = "snps,dwc3"; 343 reg = <0x10000 0x10000>; 344 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 347 interrupt-names = "peripheral", 348 "host", 349 "otg"; 350 maximum-speed = "high-speed"; 351 dr_mode = "otg"; 352 phys = <&usb1_phy>; 353 phy-names = "usb2-phy"; 354 }; 355 }; 356 357 usb1_phy: phy@4110000 { 358 compatible = "ti,am654-usb2", "ti,omap-usb2"; 359 reg = <0x0 0x4110000 0x0 0x54>; 360 syscon-phy-power = <&scm_conf 0x4020>; 361 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 362 clock-names = "wkupclk", "refclk"; 363 #phy-cells = <0>; 364 }; 365 366 intr_main_gpio: interrupt-controller0 { 367 compatible = "ti,sci-intr"; 368 ti,intr-trigger-type = <1>; 369 interrupt-controller; 370 interrupt-parent = <&gic500>; 371 #interrupt-cells = <2>; 372 ti,sci = <&dmsc>; 373 ti,sci-dst-id = <56>; 374 ti,sci-rm-range-girq = <0x1>; 375 }; 376 377 main_navss { 378 compatible = "simple-mfd"; 379 #address-cells = <2>; 380 #size-cells = <2>; 381 ranges; 382 dma-coherent; 383 dma-ranges; 384 385 ti,sci-dev-id = <118>; 386 387 intr_main_navss: interrupt-controller1 { 388 compatible = "ti,sci-intr"; 389 ti,intr-trigger-type = <4>; 390 interrupt-controller; 391 interrupt-parent = <&gic500>; 392 #interrupt-cells = <2>; 393 ti,sci = <&dmsc>; 394 ti,sci-dst-id = <56>; 395 ti,sci-rm-range-girq = <0x0>, <0x2>; 396 }; 397 398 inta_main_udmass: interrupt-controller@33d00000 { 399 compatible = "ti,sci-inta"; 400 reg = <0x0 0x33d00000 0x0 0x100000>; 401 interrupt-controller; 402 interrupt-parent = <&intr_main_navss>; 403 msi-controller; 404 ti,sci = <&dmsc>; 405 ti,sci-dev-id = <179>; 406 ti,sci-rm-range-vint = <0x0>; 407 ti,sci-rm-range-global-event = <0x1>; 408 }; 409 410 secure_proxy_main: mailbox@32c00000 { 411 compatible = "ti,am654-secure-proxy"; 412 #mbox-cells = <1>; 413 reg-names = "target_data", "rt", "scfg"; 414 reg = <0x00 0x32c00000 0x00 0x100000>, 415 <0x00 0x32400000 0x00 0x100000>, 416 <0x00 0x32800000 0x00 0x100000>; 417 interrupt-names = "rx_011"; 418 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 419 }; 420 421 hwspinlock: spinlock@30e00000 { 422 compatible = "ti,am654-hwspinlock"; 423 reg = <0x00 0x30e00000 0x00 0x1000>; 424 #hwlock-cells = <1>; 425 }; 426 427 mailbox0_cluster0: mailbox@31f80000 { 428 compatible = "ti,am654-mailbox"; 429 reg = <0x00 0x31f80000 0x00 0x200>; 430 #mbox-cells = <1>; 431 ti,mbox-num-users = <4>; 432 ti,mbox-num-fifos = <16>; 433 interrupt-parent = <&intr_main_navss>; 434 }; 435 436 mailbox0_cluster1: mailbox@31f81000 { 437 compatible = "ti,am654-mailbox"; 438 reg = <0x00 0x31f81000 0x00 0x200>; 439 #mbox-cells = <1>; 440 ti,mbox-num-users = <4>; 441 ti,mbox-num-fifos = <16>; 442 interrupt-parent = <&intr_main_navss>; 443 }; 444 445 mailbox0_cluster2: mailbox@31f82000 { 446 compatible = "ti,am654-mailbox"; 447 reg = <0x00 0x31f82000 0x00 0x200>; 448 #mbox-cells = <1>; 449 ti,mbox-num-users = <4>; 450 ti,mbox-num-fifos = <16>; 451 interrupt-parent = <&intr_main_navss>; 452 }; 453 454 mailbox0_cluster3: mailbox@31f83000 { 455 compatible = "ti,am654-mailbox"; 456 reg = <0x00 0x31f83000 0x00 0x200>; 457 #mbox-cells = <1>; 458 ti,mbox-num-users = <4>; 459 ti,mbox-num-fifos = <16>; 460 interrupt-parent = <&intr_main_navss>; 461 }; 462 463 mailbox0_cluster4: mailbox@31f84000 { 464 compatible = "ti,am654-mailbox"; 465 reg = <0x00 0x31f84000 0x00 0x200>; 466 #mbox-cells = <1>; 467 ti,mbox-num-users = <4>; 468 ti,mbox-num-fifos = <16>; 469 interrupt-parent = <&intr_main_navss>; 470 }; 471 472 mailbox0_cluster5: mailbox@31f85000 { 473 compatible = "ti,am654-mailbox"; 474 reg = <0x00 0x31f85000 0x00 0x200>; 475 #mbox-cells = <1>; 476 ti,mbox-num-users = <4>; 477 ti,mbox-num-fifos = <16>; 478 interrupt-parent = <&intr_main_navss>; 479 }; 480 481 mailbox0_cluster6: mailbox@31f86000 { 482 compatible = "ti,am654-mailbox"; 483 reg = <0x00 0x31f86000 0x00 0x200>; 484 #mbox-cells = <1>; 485 ti,mbox-num-users = <4>; 486 ti,mbox-num-fifos = <16>; 487 interrupt-parent = <&intr_main_navss>; 488 }; 489 490 mailbox0_cluster7: mailbox@31f87000 { 491 compatible = "ti,am654-mailbox"; 492 reg = <0x00 0x31f87000 0x00 0x200>; 493 #mbox-cells = <1>; 494 ti,mbox-num-users = <4>; 495 ti,mbox-num-fifos = <16>; 496 interrupt-parent = <&intr_main_navss>; 497 }; 498 499 mailbox0_cluster8: mailbox@31f88000 { 500 compatible = "ti,am654-mailbox"; 501 reg = <0x00 0x31f88000 0x00 0x200>; 502 #mbox-cells = <1>; 503 ti,mbox-num-users = <4>; 504 ti,mbox-num-fifos = <16>; 505 interrupt-parent = <&intr_main_navss>; 506 }; 507 508 mailbox0_cluster9: mailbox@31f89000 { 509 compatible = "ti,am654-mailbox"; 510 reg = <0x00 0x31f89000 0x00 0x200>; 511 #mbox-cells = <1>; 512 ti,mbox-num-users = <4>; 513 ti,mbox-num-fifos = <16>; 514 interrupt-parent = <&intr_main_navss>; 515 }; 516 517 mailbox0_cluster10: mailbox@31f8a000 { 518 compatible = "ti,am654-mailbox"; 519 reg = <0x00 0x31f8a000 0x00 0x200>; 520 #mbox-cells = <1>; 521 ti,mbox-num-users = <4>; 522 ti,mbox-num-fifos = <16>; 523 interrupt-parent = <&intr_main_navss>; 524 }; 525 526 mailbox0_cluster11: mailbox@31f8b000 { 527 compatible = "ti,am654-mailbox"; 528 reg = <0x00 0x31f8b000 0x00 0x200>; 529 #mbox-cells = <1>; 530 ti,mbox-num-users = <4>; 531 ti,mbox-num-fifos = <16>; 532 interrupt-parent = <&intr_main_navss>; 533 }; 534 535 ringacc: ringacc@3c000000 { 536 compatible = "ti,am654-navss-ringacc"; 537 reg = <0x0 0x3c000000 0x0 0x400000>, 538 <0x0 0x38000000 0x0 0x400000>, 539 <0x0 0x31120000 0x0 0x100>, 540 <0x0 0x33000000 0x0 0x40000>; 541 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 542 ti,num-rings = <818>; 543 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ 544 ti,dma-ring-reset-quirk; 545 ti,sci = <&dmsc>; 546 ti,sci-dev-id = <187>; 547 msi-parent = <&inta_main_udmass>; 548 }; 549 550 main_udmap: dma-controller@31150000 { 551 compatible = "ti,am654-navss-main-udmap"; 552 reg = <0x0 0x31150000 0x0 0x100>, 553 <0x0 0x34000000 0x0 0x100000>, 554 <0x0 0x35000000 0x0 0x100000>; 555 reg-names = "gcfg", "rchanrt", "tchanrt"; 556 msi-parent = <&inta_main_udmass>; 557 #dma-cells = <1>; 558 559 ti,sci = <&dmsc>; 560 ti,sci-dev-id = <188>; 561 ti,ringacc = <&ringacc>; 562 563 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ 564 <0x2>; /* TX_CHAN */ 565 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */ 566 <0x5>; /* RX_CHAN */ 567 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */ 568 }; 569 }; 570 571 main_gpio0: main_gpio0@600000 { 572 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 573 reg = <0x0 0x600000 0x0 0x100>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-parent = <&intr_main_gpio>; 577 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>, 578 <57 261>; 579 interrupt-controller; 580 #interrupt-cells = <2>; 581 ti,ngpio = <96>; 582 ti,davinci-gpio-unbanked = <0>; 583 clocks = <&k3_clks 57 0>; 584 clock-names = "gpio"; 585 }; 586 587 main_gpio1: main_gpio1@601000 { 588 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 589 reg = <0x0 0x601000 0x0 0x100>; 590 gpio-controller; 591 #gpio-cells = <2>; 592 interrupt-parent = <&intr_main_gpio>; 593 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>, 594 <58 261>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 ti,ngpio = <90>; 598 ti,davinci-gpio-unbanked = <0>; 599 clocks = <&k3_clks 58 0>; 600 clock-names = "gpio"; 601 }; 602 603 pcie0_rc: pcie@5500000 { 604 compatible = "ti,am654-pcie-rc"; 605 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 606 reg-names = "app", "dbics", "config", "atu"; 607 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 608 #address-cells = <3>; 609 #size-cells = <2>; 610 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 611 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 612 ti,syscon-pcie-id = <&pcie_devid>; 613 ti,syscon-pcie-mode = <&pcie0_mode>; 614 bus-range = <0x0 0xff>; 615 num-viewport = <16>; 616 max-link-speed = <3>; 617 dma-coherent; 618 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 619 msi-map = <0x0 &gic_its 0x0 0x10000>; 620 }; 621 622 pcie0_ep: pcie-ep@5500000 { 623 compatible = "ti,am654-pcie-ep"; 624 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 625 reg-names = "app", "dbics", "addr_space", "atu"; 626 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 627 ti,syscon-pcie-mode = <&pcie0_mode>; 628 num-ib-windows = <16>; 629 num-ob-windows = <16>; 630 max-link-speed = <3>; 631 dma-coherent; 632 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 633 }; 634 635 pcie1_rc: pcie@5600000 { 636 compatible = "ti,am654-pcie-rc"; 637 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 638 reg-names = "app", "dbics", "config", "atu"; 639 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 640 #address-cells = <3>; 641 #size-cells = <2>; 642 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 643 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 644 ti,syscon-pcie-id = <&pcie_devid>; 645 ti,syscon-pcie-mode = <&pcie1_mode>; 646 bus-range = <0x0 0xff>; 647 num-viewport = <16>; 648 max-link-speed = <3>; 649 dma-coherent; 650 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 651 msi-map = <0x0 &gic_its 0x10000 0x10000>; 652 }; 653 654 pcie1_ep: pcie-ep@5600000 { 655 compatible = "ti,am654-pcie-ep"; 656 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 657 reg-names = "app", "dbics", "addr_space", "atu"; 658 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 659 ti,syscon-pcie-mode = <&pcie1_mode>; 660 num-ib-windows = <16>; 661 num-ob-windows = <16>; 662 max-link-speed = <3>; 663 dma-coherent; 664 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 665 }; 666 667 mcasp0: mcasp@2b00000 { 668 compatible = "ti,am33xx-mcasp-audio"; 669 reg = <0x0 0x02b00000 0x0 0x2000>, 670 <0x0 0x02b08000 0x0 0x1000>; 671 reg-names = "mpu","dat"; 672 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 674 interrupt-names = "tx", "rx"; 675 676 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 677 dma-names = "tx", "rx"; 678 679 clocks = <&k3_clks 104 0>; 680 clock-names = "fck"; 681 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 682 683 status = "disabled"; 684 }; 685 686 mcasp1: mcasp@2b10000 { 687 compatible = "ti,am33xx-mcasp-audio"; 688 reg = <0x0 0x02b10000 0x0 0x2000>, 689 <0x0 0x02b18000 0x0 0x1000>; 690 reg-names = "mpu","dat"; 691 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 693 interrupt-names = "tx", "rx"; 694 695 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 696 dma-names = "tx", "rx"; 697 698 clocks = <&k3_clks 105 0>; 699 clock-names = "fck"; 700 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 701 702 status = "disabled"; 703 }; 704 705 mcasp2: mcasp@2b20000 { 706 compatible = "ti,am33xx-mcasp-audio"; 707 reg = <0x0 0x02b20000 0x0 0x2000>, 708 <0x0 0x02b28000 0x0 0x1000>; 709 reg-names = "mpu","dat"; 710 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 712 interrupt-names = "tx", "rx"; 713 714 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 715 dma-names = "tx", "rx"; 716 717 clocks = <&k3_clks 106 0>; 718 clock-names = "fck"; 719 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 720 721 status = "disabled"; 722 }; 723 724 cal: cal@6f03000 { 725 compatible = "ti,am654-cal"; 726 reg = <0x0 0x06f03000 0x0 0x400>, 727 <0x0 0x06f03800 0x0 0x40>; 728 reg-names = "cal_top", 729 "cal_rx_core0"; 730 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 731 ti,camerrx-control = <&scm_conf 0x40c0>; 732 clock-names = "fck"; 733 clocks = <&k3_clks 2 0>; 734 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 735 736 ports { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 740 csi2_0: port@0 { 741 reg = <0>; 742 }; 743 }; 744 }; 745}; 746