1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>; /* GICR */ 39 /* 40 * vcpumntirq: 41 * virtual CPU interface maintenance interrupt 42 */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: msi-controller@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 serdes0: serdes@900000 { 55 compatible = "ti,phy-am654-serdes"; 56 reg = <0x0 0x900000 0x0 0x2000>; 57 reg-names = "serdes"; 58 #phy-cells = <2>; 59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 64 ti,serdes-clk = <&serdes0_clk>; 65 #clock-cells = <1>; 66 mux-controls = <&serdes_mux 0>; 67 }; 68 69 serdes1: serdes@910000 { 70 compatible = "ti,phy-am654-serdes"; 71 reg = <0x0 0x910000 0x0 0x2000>; 72 reg-names = "serdes"; 73 #phy-cells = <2>; 74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 75 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 79 ti,serdes-clk = <&serdes1_clk>; 80 #clock-cells = <1>; 81 mux-controls = <&serdes_mux 1>; 82 }; 83 84 main_uart0: serial@2800000 { 85 compatible = "ti,am654-uart"; 86 reg = <0x00 0x02800000 0x00 0x100>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 90 clock-frequency = <48000000>; 91 current-speed = <115200>; 92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 93 }; 94 95 main_uart1: serial@2810000 { 96 compatible = "ti,am654-uart"; 97 reg = <0x00 0x02810000 0x00 0x100>; 98 reg-shift = <2>; 99 reg-io-width = <4>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 }; 104 105 main_uart2: serial@2820000 { 106 compatible = "ti,am654-uart"; 107 reg = <0x00 0x02820000 0x00 0x100>; 108 reg-shift = <2>; 109 reg-io-width = <4>; 110 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 111 clock-frequency = <48000000>; 112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 113 }; 114 115 crypto: crypto@4e00000 { 116 compatible = "ti,am654-sa2ul"; 117 reg = <0x0 0x4e00000 0x0 0x1200>; 118 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 122 123 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 124 <&main_udmap 0x4001>; 125 dma-names = "tx", "rx1", "rx2"; 126 dma-coherent; 127 128 rng: rng@4e10000 { 129 compatible = "inside-secure,safexcel-eip76"; 130 reg = <0x0 0x4e10000 0x0 0x7d>; 131 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&k3_clks 136 1>; 133 }; 134 }; 135 136 main_pmx0: pinctrl@11c000 { 137 compatible = "pinctrl-single"; 138 reg = <0x0 0x11c000 0x0 0x2e4>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0xffffffff>; 142 }; 143 144 main_pmx1: pinctrl@11c2e8 { 145 compatible = "pinctrl-single"; 146 reg = <0x0 0x11c2e8 0x0 0x24>; 147 #pinctrl-cells = <1>; 148 pinctrl-single,register-width = <32>; 149 pinctrl-single,function-mask = <0xffffffff>; 150 }; 151 152 main_i2c0: i2c@2000000 { 153 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 154 reg = <0x0 0x2000000 0x0 0x100>; 155 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 clock-names = "fck"; 159 clocks = <&k3_clks 110 1>; 160 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 161 }; 162 163 main_i2c1: i2c@2010000 { 164 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 165 reg = <0x0 0x2010000 0x0 0x100>; 166 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 clock-names = "fck"; 170 clocks = <&k3_clks 111 1>; 171 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 172 }; 173 174 main_i2c2: i2c@2020000 { 175 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 176 reg = <0x0 0x2020000 0x0 0x100>; 177 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clock-names = "fck"; 181 clocks = <&k3_clks 112 1>; 182 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 183 }; 184 185 main_i2c3: i2c@2030000 { 186 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 187 reg = <0x0 0x2030000 0x0 0x100>; 188 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 clock-names = "fck"; 192 clocks = <&k3_clks 113 1>; 193 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 194 }; 195 196 ecap0: pwm@3100000 { 197 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 198 #pwm-cells = <3>; 199 reg = <0x0 0x03100000 0x0 0x60>; 200 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 201 clocks = <&k3_clks 39 0>; 202 clock-names = "fck"; 203 }; 204 205 main_spi0: spi@2100000 { 206 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 207 reg = <0x0 0x2100000 0x0 0x400>; 208 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&k3_clks 137 1>; 210 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 214 dma-names = "tx0", "rx0"; 215 }; 216 217 main_spi1: spi@2110000 { 218 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 219 reg = <0x0 0x2110000 0x0 0x400>; 220 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&k3_clks 138 1>; 222 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 assigned-clocks = <&k3_clks 137 1>; 226 assigned-clock-rates = <48000000>; 227 }; 228 229 main_spi2: spi@2120000 { 230 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 231 reg = <0x0 0x2120000 0x0 0x400>; 232 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&k3_clks 139 1>; 234 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 239 main_spi3: spi@2130000 { 240 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 241 reg = <0x0 0x2130000 0x0 0x400>; 242 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&k3_clks 140 1>; 244 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 main_spi4: spi@2140000 { 250 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 251 reg = <0x0 0x2140000 0x0 0x400>; 252 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&k3_clks 141 1>; 254 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 sdhci0: mmc@4f80000 { 260 compatible = "ti,am654-sdhci-5.1"; 261 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 262 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 264 clock-names = "clk_ahb", "clk_xin"; 265 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 266 mmc-ddr-1_8v; 267 mmc-hs200-1_8v; 268 ti,otap-del-sel-legacy = <0x0>; 269 ti,otap-del-sel-mmc-hs = <0x0>; 270 ti,otap-del-sel-sd-hs = <0x0>; 271 ti,otap-del-sel-sdr12 = <0x0>; 272 ti,otap-del-sel-sdr25 = <0x0>; 273 ti,otap-del-sel-sdr50 = <0x8>; 274 ti,otap-del-sel-sdr104 = <0x7>; 275 ti,otap-del-sel-ddr50 = <0x5>; 276 ti,otap-del-sel-ddr52 = <0x5>; 277 ti,otap-del-sel-hs200 = <0x5>; 278 ti,otap-del-sel-hs400 = <0x0>; 279 ti,trm-icp = <0x8>; 280 dma-coherent; 281 }; 282 283 sdhci1: mmc@4fa0000 { 284 compatible = "ti,am654-sdhci-5.1"; 285 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 286 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 287 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 288 clock-names = "clk_ahb", "clk_xin"; 289 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 290 ti,otap-del-sel-legacy = <0x0>; 291 ti,otap-del-sel-mmc-hs = <0x0>; 292 ti,otap-del-sel-sd-hs = <0x0>; 293 ti,otap-del-sel-sdr12 = <0x0>; 294 ti,otap-del-sel-sdr25 = <0x0>; 295 ti,otap-del-sel-sdr50 = <0x8>; 296 ti,otap-del-sel-sdr104 = <0x7>; 297 ti,otap-del-sel-ddr50 = <0x4>; 298 ti,otap-del-sel-ddr52 = <0x4>; 299 ti,otap-del-sel-hs200 = <0x7>; 300 ti,clkbuf-sel = <0x7>; 301 ti,otap-del-sel = <0x2>; 302 ti,trm-icp = <0x8>; 303 dma-coherent; 304 no-1-8-v; 305 }; 306 307 scm_conf: scm-conf@100000 { 308 compatible = "syscon", "simple-mfd"; 309 reg = <0 0x00100000 0 0x1c000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges = <0x0 0x0 0x00100000 0x1c000>; 313 314 pcie0_mode: pcie-mode@4060 { 315 compatible = "syscon"; 316 reg = <0x00004060 0x4>; 317 }; 318 319 pcie1_mode: pcie-mode@4070 { 320 compatible = "syscon"; 321 reg = <0x00004070 0x4>; 322 }; 323 324 pcie_devid: pcie-devid@210 { 325 compatible = "syscon"; 326 reg = <0x00000210 0x4>; 327 }; 328 329 serdes0_clk: clock@4080 { 330 compatible = "syscon"; 331 reg = <0x00004080 0x4>; 332 }; 333 334 serdes1_clk: clock@4090 { 335 compatible = "syscon"; 336 reg = <0x00004090 0x4>; 337 }; 338 339 serdes_mux: mux-controller { 340 compatible = "mmio-mux"; 341 #mux-control-cells = <1>; 342 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 343 <0x4090 0x3>; /* SERDES1 lane select */ 344 }; 345 346 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 347 compatible = "syscon"; 348 reg = <0x0000041e0 0x14>; 349 }; 350 351 ehrpwm_tbclk: clock@4140 { 352 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 353 reg = <0x4140 0x18>; 354 #clock-cells = <1>; 355 }; 356 }; 357 358 dwc3_0: dwc3@4000000 { 359 compatible = "ti,am654-dwc3"; 360 reg = <0x0 0x4000000 0x0 0x4000>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 ranges = <0x0 0x0 0x4000000 0x20000>; 364 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 365 dma-coherent; 366 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 367 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 368 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 369 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 370 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 371 372 usb0: usb@10000 { 373 compatible = "snps,dwc3"; 374 reg = <0x10000 0x10000>; 375 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "peripheral", 379 "host", 380 "otg"; 381 maximum-speed = "high-speed"; 382 dr_mode = "otg"; 383 phys = <&usb0_phy>; 384 phy-names = "usb2-phy"; 385 snps,dis_u3_susphy_quirk; 386 }; 387 }; 388 389 usb0_phy: phy@4100000 { 390 compatible = "ti,am654-usb2", "ti,omap-usb2"; 391 reg = <0x0 0x4100000 0x0 0x54>; 392 syscon-phy-power = <&scm_conf 0x4000>; 393 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 394 clock-names = "wkupclk", "refclk"; 395 #phy-cells = <0>; 396 }; 397 398 dwc3_1: dwc3@4020000 { 399 compatible = "ti,am654-dwc3"; 400 reg = <0x0 0x4020000 0x0 0x4000>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges = <0x0 0x0 0x4020000 0x20000>; 404 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 405 dma-coherent; 406 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 152 2>; 408 assigned-clocks = <&k3_clks 152 2>; 409 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 410 411 usb1: usb@10000 { 412 compatible = "snps,dwc3"; 413 reg = <0x10000 0x10000>; 414 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "peripheral", 418 "host", 419 "otg"; 420 maximum-speed = "high-speed"; 421 dr_mode = "otg"; 422 phys = <&usb1_phy>; 423 phy-names = "usb2-phy"; 424 }; 425 }; 426 427 usb1_phy: phy@4110000 { 428 compatible = "ti,am654-usb2", "ti,omap-usb2"; 429 reg = <0x0 0x4110000 0x0 0x54>; 430 syscon-phy-power = <&scm_conf 0x4020>; 431 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 432 clock-names = "wkupclk", "refclk"; 433 #phy-cells = <0>; 434 }; 435 436 intr_main_gpio: interrupt-controller0 { 437 compatible = "ti,sci-intr"; 438 ti,intr-trigger-type = <1>; 439 interrupt-controller; 440 interrupt-parent = <&gic500>; 441 #interrupt-cells = <1>; 442 ti,sci = <&dmsc>; 443 ti,sci-dev-id = <100>; 444 ti,interrupt-ranges = <0 392 32>; 445 }; 446 447 main-navss { 448 compatible = "simple-mfd"; 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 dma-coherent; 453 dma-ranges; 454 455 ti,sci-dev-id = <118>; 456 457 intr_main_navss: interrupt-controller1 { 458 compatible = "ti,sci-intr"; 459 ti,intr-trigger-type = <4>; 460 interrupt-controller; 461 interrupt-parent = <&gic500>; 462 #interrupt-cells = <1>; 463 ti,sci = <&dmsc>; 464 ti,sci-dev-id = <182>; 465 ti,interrupt-ranges = <0 64 64>, 466 <64 448 64>; 467 }; 468 469 inta_main_udmass: interrupt-controller@33d00000 { 470 compatible = "ti,sci-inta"; 471 reg = <0x0 0x33d00000 0x0 0x100000>; 472 interrupt-controller; 473 interrupt-parent = <&intr_main_navss>; 474 msi-controller; 475 #interrupt-cells = <0>; 476 ti,sci = <&dmsc>; 477 ti,sci-dev-id = <179>; 478 ti,interrupt-ranges = <0 0 256>; 479 }; 480 481 secure_proxy_main: mailbox@32c00000 { 482 compatible = "ti,am654-secure-proxy"; 483 #mbox-cells = <1>; 484 reg-names = "target_data", "rt", "scfg"; 485 reg = <0x00 0x32c00000 0x00 0x100000>, 486 <0x00 0x32400000 0x00 0x100000>, 487 <0x00 0x32800000 0x00 0x100000>; 488 interrupt-names = "rx_011"; 489 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 490 }; 491 492 hwspinlock: spinlock@30e00000 { 493 compatible = "ti,am654-hwspinlock"; 494 reg = <0x00 0x30e00000 0x00 0x1000>; 495 #hwlock-cells = <1>; 496 }; 497 498 mailbox0_cluster0: mailbox@31f80000 { 499 compatible = "ti,am654-mailbox"; 500 reg = <0x00 0x31f80000 0x00 0x200>; 501 #mbox-cells = <1>; 502 ti,mbox-num-users = <4>; 503 ti,mbox-num-fifos = <16>; 504 interrupt-parent = <&intr_main_navss>; 505 }; 506 507 mailbox0_cluster1: mailbox@31f81000 { 508 compatible = "ti,am654-mailbox"; 509 reg = <0x00 0x31f81000 0x00 0x200>; 510 #mbox-cells = <1>; 511 ti,mbox-num-users = <4>; 512 ti,mbox-num-fifos = <16>; 513 interrupt-parent = <&intr_main_navss>; 514 }; 515 516 mailbox0_cluster2: mailbox@31f82000 { 517 compatible = "ti,am654-mailbox"; 518 reg = <0x00 0x31f82000 0x00 0x200>; 519 #mbox-cells = <1>; 520 ti,mbox-num-users = <4>; 521 ti,mbox-num-fifos = <16>; 522 interrupt-parent = <&intr_main_navss>; 523 }; 524 525 mailbox0_cluster3: mailbox@31f83000 { 526 compatible = "ti,am654-mailbox"; 527 reg = <0x00 0x31f83000 0x00 0x200>; 528 #mbox-cells = <1>; 529 ti,mbox-num-users = <4>; 530 ti,mbox-num-fifos = <16>; 531 interrupt-parent = <&intr_main_navss>; 532 }; 533 534 mailbox0_cluster4: mailbox@31f84000 { 535 compatible = "ti,am654-mailbox"; 536 reg = <0x00 0x31f84000 0x00 0x200>; 537 #mbox-cells = <1>; 538 ti,mbox-num-users = <4>; 539 ti,mbox-num-fifos = <16>; 540 interrupt-parent = <&intr_main_navss>; 541 }; 542 543 mailbox0_cluster5: mailbox@31f85000 { 544 compatible = "ti,am654-mailbox"; 545 reg = <0x00 0x31f85000 0x00 0x200>; 546 #mbox-cells = <1>; 547 ti,mbox-num-users = <4>; 548 ti,mbox-num-fifos = <16>; 549 interrupt-parent = <&intr_main_navss>; 550 }; 551 552 mailbox0_cluster6: mailbox@31f86000 { 553 compatible = "ti,am654-mailbox"; 554 reg = <0x00 0x31f86000 0x00 0x200>; 555 #mbox-cells = <1>; 556 ti,mbox-num-users = <4>; 557 ti,mbox-num-fifos = <16>; 558 interrupt-parent = <&intr_main_navss>; 559 }; 560 561 mailbox0_cluster7: mailbox@31f87000 { 562 compatible = "ti,am654-mailbox"; 563 reg = <0x00 0x31f87000 0x00 0x200>; 564 #mbox-cells = <1>; 565 ti,mbox-num-users = <4>; 566 ti,mbox-num-fifos = <16>; 567 interrupt-parent = <&intr_main_navss>; 568 }; 569 570 mailbox0_cluster8: mailbox@31f88000 { 571 compatible = "ti,am654-mailbox"; 572 reg = <0x00 0x31f88000 0x00 0x200>; 573 #mbox-cells = <1>; 574 ti,mbox-num-users = <4>; 575 ti,mbox-num-fifos = <16>; 576 interrupt-parent = <&intr_main_navss>; 577 }; 578 579 mailbox0_cluster9: mailbox@31f89000 { 580 compatible = "ti,am654-mailbox"; 581 reg = <0x00 0x31f89000 0x00 0x200>; 582 #mbox-cells = <1>; 583 ti,mbox-num-users = <4>; 584 ti,mbox-num-fifos = <16>; 585 interrupt-parent = <&intr_main_navss>; 586 }; 587 588 mailbox0_cluster10: mailbox@31f8a000 { 589 compatible = "ti,am654-mailbox"; 590 reg = <0x00 0x31f8a000 0x00 0x200>; 591 #mbox-cells = <1>; 592 ti,mbox-num-users = <4>; 593 ti,mbox-num-fifos = <16>; 594 interrupt-parent = <&intr_main_navss>; 595 }; 596 597 mailbox0_cluster11: mailbox@31f8b000 { 598 compatible = "ti,am654-mailbox"; 599 reg = <0x00 0x31f8b000 0x00 0x200>; 600 #mbox-cells = <1>; 601 ti,mbox-num-users = <4>; 602 ti,mbox-num-fifos = <16>; 603 interrupt-parent = <&intr_main_navss>; 604 }; 605 606 ringacc: ringacc@3c000000 { 607 compatible = "ti,am654-navss-ringacc"; 608 reg = <0x0 0x3c000000 0x0 0x400000>, 609 <0x0 0x38000000 0x0 0x400000>, 610 <0x0 0x31120000 0x0 0x100>, 611 <0x0 0x33000000 0x0 0x40000>; 612 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 613 ti,num-rings = <818>; 614 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 615 ti,sci = <&dmsc>; 616 ti,sci-dev-id = <187>; 617 msi-parent = <&inta_main_udmass>; 618 }; 619 620 main_udmap: dma-controller@31150000 { 621 compatible = "ti,am654-navss-main-udmap"; 622 reg = <0x0 0x31150000 0x0 0x100>, 623 <0x0 0x34000000 0x0 0x100000>, 624 <0x0 0x35000000 0x0 0x100000>; 625 reg-names = "gcfg", "rchanrt", "tchanrt"; 626 msi-parent = <&inta_main_udmass>; 627 #dma-cells = <1>; 628 629 ti,sci = <&dmsc>; 630 ti,sci-dev-id = <188>; 631 ti,ringacc = <&ringacc>; 632 633 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 634 <0xd>; /* TX_CHAN */ 635 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 636 <0xa>; /* RX_CHAN */ 637 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 638 }; 639 640 cpts@310d0000 { 641 compatible = "ti,am65-cpts"; 642 reg = <0x0 0x310d0000 0x0 0x400>; 643 reg-names = "cpts"; 644 clocks = <&main_cpts_mux>; 645 clock-names = "cpts"; 646 interrupts-extended = <&intr_main_navss 391>; 647 interrupt-names = "cpts"; 648 ti,cpts-periodic-outputs = <6>; 649 ti,cpts-ext-ts-inputs = <8>; 650 651 main_cpts_mux: refclk-mux { 652 #clock-cells = <0>; 653 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 654 <&k3_clks 118 6>, <&k3_clks 118 3>, 655 <&k3_clks 118 8>, <&k3_clks 118 14>, 656 <&k3_clks 120 3>, <&k3_clks 121 3>; 657 assigned-clocks = <&main_cpts_mux>; 658 assigned-clock-parents = <&k3_clks 118 5>; 659 }; 660 }; 661 }; 662 663 main_gpio0: gpio@600000 { 664 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 665 reg = <0x0 0x600000 0x0 0x100>; 666 gpio-controller; 667 #gpio-cells = <2>; 668 interrupt-parent = <&intr_main_gpio>; 669 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 670 interrupt-controller; 671 #interrupt-cells = <2>; 672 ti,ngpio = <96>; 673 ti,davinci-gpio-unbanked = <0>; 674 clocks = <&k3_clks 57 0>; 675 clock-names = "gpio"; 676 }; 677 678 main_gpio1: gpio@601000 { 679 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 680 reg = <0x0 0x601000 0x0 0x100>; 681 gpio-controller; 682 #gpio-cells = <2>; 683 interrupt-parent = <&intr_main_gpio>; 684 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 685 interrupt-controller; 686 #interrupt-cells = <2>; 687 ti,ngpio = <90>; 688 ti,davinci-gpio-unbanked = <0>; 689 clocks = <&k3_clks 58 0>; 690 clock-names = "gpio"; 691 }; 692 693 pcie0_rc: pcie@5500000 { 694 compatible = "ti,am654-pcie-rc"; 695 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 696 reg-names = "app", "dbics", "config", "atu"; 697 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 698 #address-cells = <3>; 699 #size-cells = <2>; 700 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 701 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 702 ti,syscon-pcie-id = <&pcie_devid>; 703 ti,syscon-pcie-mode = <&pcie0_mode>; 704 bus-range = <0x0 0xff>; 705 num-viewport = <16>; 706 max-link-speed = <2>; 707 dma-coherent; 708 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 709 msi-map = <0x0 &gic_its 0x0 0x10000>; 710 device_type = "pci"; 711 }; 712 713 pcie0_ep: pcie-ep@5500000 { 714 compatible = "ti,am654-pcie-ep"; 715 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 716 reg-names = "app", "dbics", "addr_space", "atu"; 717 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 718 ti,syscon-pcie-mode = <&pcie0_mode>; 719 num-ib-windows = <16>; 720 num-ob-windows = <16>; 721 max-link-speed = <2>; 722 dma-coherent; 723 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 724 }; 725 726 pcie1_rc: pcie@5600000 { 727 compatible = "ti,am654-pcie-rc"; 728 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 729 reg-names = "app", "dbics", "config", "atu"; 730 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 731 #address-cells = <3>; 732 #size-cells = <2>; 733 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 734 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 735 ti,syscon-pcie-id = <&pcie_devid>; 736 ti,syscon-pcie-mode = <&pcie1_mode>; 737 bus-range = <0x0 0xff>; 738 num-viewport = <16>; 739 max-link-speed = <2>; 740 dma-coherent; 741 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 742 msi-map = <0x0 &gic_its 0x10000 0x10000>; 743 device_type = "pci"; 744 }; 745 746 pcie1_ep: pcie-ep@5600000 { 747 compatible = "ti,am654-pcie-ep"; 748 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 749 reg-names = "app", "dbics", "addr_space", "atu"; 750 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 751 ti,syscon-pcie-mode = <&pcie1_mode>; 752 num-ib-windows = <16>; 753 num-ob-windows = <16>; 754 max-link-speed = <2>; 755 dma-coherent; 756 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 757 }; 758 759 mcasp0: mcasp@2b00000 { 760 compatible = "ti,am33xx-mcasp-audio"; 761 reg = <0x0 0x02b00000 0x0 0x2000>, 762 <0x0 0x02b08000 0x0 0x1000>; 763 reg-names = "mpu","dat"; 764 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-names = "tx", "rx"; 767 768 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 769 dma-names = "tx", "rx"; 770 771 clocks = <&k3_clks 104 0>; 772 clock-names = "fck"; 773 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 774 }; 775 776 mcasp1: mcasp@2b10000 { 777 compatible = "ti,am33xx-mcasp-audio"; 778 reg = <0x0 0x02b10000 0x0 0x2000>, 779 <0x0 0x02b18000 0x0 0x1000>; 780 reg-names = "mpu","dat"; 781 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 783 interrupt-names = "tx", "rx"; 784 785 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 786 dma-names = "tx", "rx"; 787 788 clocks = <&k3_clks 105 0>; 789 clock-names = "fck"; 790 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 791 }; 792 793 mcasp2: mcasp@2b20000 { 794 compatible = "ti,am33xx-mcasp-audio"; 795 reg = <0x0 0x02b20000 0x0 0x2000>, 796 <0x0 0x02b28000 0x0 0x1000>; 797 reg-names = "mpu","dat"; 798 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "tx", "rx"; 801 802 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 803 dma-names = "tx", "rx"; 804 805 clocks = <&k3_clks 106 0>; 806 clock-names = "fck"; 807 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 808 }; 809 810 cal: cal@6f03000 { 811 compatible = "ti,am654-cal"; 812 reg = <0x0 0x06f03000 0x0 0x400>, 813 <0x0 0x06f03800 0x0 0x40>; 814 reg-names = "cal_top", 815 "cal_rx_core0"; 816 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 817 ti,camerrx-control = <&scm_conf 0x40c0>; 818 clock-names = "fck"; 819 clocks = <&k3_clks 2 0>; 820 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 821 822 ports { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 826 csi2_0: port@0 { 827 reg = <0>; 828 }; 829 }; 830 }; 831 832 dss: dss@4a00000 { 833 compatible = "ti,am65x-dss"; 834 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 835 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 836 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 837 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 838 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 839 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 840 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 841 reg-names = "common", "vidl1", "vid", 842 "ovr1", "ovr2", "vp1", "vp2"; 843 844 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 845 846 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 847 848 clocks = <&k3_clks 67 1>, 849 <&k3_clks 216 1>, 850 <&k3_clks 67 2>; 851 clock-names = "fck", "vp1", "vp2"; 852 853 /* 854 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 855 * DIV1. See "Figure 12-3365. DSS Integration" 856 * in AM65x TRM for details. 857 */ 858 assigned-clocks = <&k3_clks 67 2>; 859 assigned-clock-parents = <&k3_clks 67 5>; 860 861 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 862 863 dma-coherent; 864 865 dss_ports: ports { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 }; 869 }; 870 871 ehrpwm0: pwm@3000000 { 872 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 873 #pwm-cells = <3>; 874 reg = <0x0 0x3000000 0x0 0x100>; 875 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 876 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 877 clock-names = "tbclk", "fck"; 878 }; 879 880 ehrpwm1: pwm@3010000 { 881 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 882 #pwm-cells = <3>; 883 reg = <0x0 0x3010000 0x0 0x100>; 884 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 885 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 886 clock-names = "tbclk", "fck"; 887 }; 888 889 ehrpwm2: pwm@3020000 { 890 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 891 #pwm-cells = <3>; 892 reg = <0x0 0x3020000 0x0 0x100>; 893 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 894 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 895 clock-names = "tbclk", "fck"; 896 }; 897 898 ehrpwm3: pwm@3030000 { 899 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 900 #pwm-cells = <3>; 901 reg = <0x0 0x3030000 0x0 0x100>; 902 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 903 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 904 clock-names = "tbclk", "fck"; 905 }; 906 907 ehrpwm4: pwm@3040000 { 908 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 909 #pwm-cells = <3>; 910 reg = <0x0 0x3040000 0x0 0x100>; 911 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 912 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 913 clock-names = "tbclk", "fck"; 914 }; 915 916 ehrpwm5: pwm@3050000 { 917 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 918 #pwm-cells = <3>; 919 reg = <0x0 0x3050000 0x0 0x100>; 920 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 921 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 922 clock-names = "tbclk", "fck"; 923 }; 924 925 icssg0: icssg@b000000 { 926 compatible = "ti,am654-icssg"; 927 reg = <0x00 0xb000000 0x00 0x80000>; 928 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 929 #address-cells = <1>; 930 #size-cells = <1>; 931 ranges = <0x0 0x00 0xb000000 0x80000>; 932 933 icssg0_mem: memories@0 { 934 reg = <0x0 0x2000>, 935 <0x2000 0x2000>, 936 <0x10000 0x10000>; 937 reg-names = "dram0", "dram1", 938 "shrdram2"; 939 }; 940 941 icssg0_cfg: cfg@26000 { 942 compatible = "ti,pruss-cfg", "syscon"; 943 reg = <0x26000 0x200>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 ranges = <0x0 0x26000 0x2000>; 947 948 clocks { 949 #address-cells = <1>; 950 #size-cells = <0>; 951 952 icssg0_coreclk_mux: coreclk-mux@3c { 953 reg = <0x3c>; 954 #clock-cells = <0>; 955 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 956 <&k3_clks 62 3>; /* icssg0_iclk */ 957 assigned-clocks = <&icssg0_coreclk_mux>; 958 assigned-clock-parents = <&k3_clks 62 3>; 959 }; 960 961 icssg0_iepclk_mux: iepclk-mux@30 { 962 reg = <0x30>; 963 #clock-cells = <0>; 964 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 965 <&icssg0_coreclk_mux>; /* core_clk */ 966 assigned-clocks = <&icssg0_iepclk_mux>; 967 assigned-clock-parents = <&icssg0_coreclk_mux>; 968 }; 969 }; 970 }; 971 972 icssg0_mii_rt: mii-rt@32000 { 973 compatible = "ti,pruss-mii", "syscon"; 974 reg = <0x32000 0x100>; 975 }; 976 977 icssg0_mii_g_rt: mii-g-rt@33000 { 978 compatible = "ti,pruss-mii-g", "syscon"; 979 reg = <0x33000 0x1000>; 980 }; 981 982 icssg0_intc: interrupt-controller@20000 { 983 compatible = "ti,icssg-intc"; 984 reg = <0x20000 0x2000>; 985 interrupt-controller; 986 #interrupt-cells = <3>; 987 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "host_intr0", "host_intr1", 996 "host_intr2", "host_intr3", 997 "host_intr4", "host_intr5", 998 "host_intr6", "host_intr7"; 999 }; 1000 1001 pru0_0: pru@34000 { 1002 compatible = "ti,am654-pru"; 1003 reg = <0x34000 0x4000>, 1004 <0x22000 0x100>, 1005 <0x22400 0x100>; 1006 reg-names = "iram", "control", "debug"; 1007 firmware-name = "am65x-pru0_0-fw"; 1008 }; 1009 1010 rtu0_0: rtu@4000 { 1011 compatible = "ti,am654-rtu"; 1012 reg = <0x4000 0x2000>, 1013 <0x23000 0x100>, 1014 <0x23400 0x100>; 1015 reg-names = "iram", "control", "debug"; 1016 firmware-name = "am65x-rtu0_0-fw"; 1017 }; 1018 1019 tx_pru0_0: txpru@a000 { 1020 compatible = "ti,am654-tx-pru"; 1021 reg = <0xa000 0x1800>, 1022 <0x25000 0x100>, 1023 <0x25400 0x100>; 1024 reg-names = "iram", "control", "debug"; 1025 firmware-name = "am65x-txpru0_0-fw"; 1026 }; 1027 1028 pru0_1: pru@38000 { 1029 compatible = "ti,am654-pru"; 1030 reg = <0x38000 0x4000>, 1031 <0x24000 0x100>, 1032 <0x24400 0x100>; 1033 reg-names = "iram", "control", "debug"; 1034 firmware-name = "am65x-pru0_1-fw"; 1035 }; 1036 1037 rtu0_1: rtu@6000 { 1038 compatible = "ti,am654-rtu"; 1039 reg = <0x6000 0x2000>, 1040 <0x23800 0x100>, 1041 <0x23c00 0x100>; 1042 reg-names = "iram", "control", "debug"; 1043 firmware-name = "am65x-rtu0_1-fw"; 1044 }; 1045 1046 tx_pru0_1: txpru@c000 { 1047 compatible = "ti,am654-tx-pru"; 1048 reg = <0xc000 0x1800>, 1049 <0x25800 0x100>, 1050 <0x25c00 0x100>; 1051 reg-names = "iram", "control", "debug"; 1052 firmware-name = "am65x-txpru0_1-fw"; 1053 }; 1054 }; 1055 1056 icssg1: icssg@b100000 { 1057 compatible = "ti,am654-icssg"; 1058 reg = <0x00 0xb100000 0x00 0x80000>; 1059 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1060 #address-cells = <1>; 1061 #size-cells = <1>; 1062 ranges = <0x0 0x00 0xb100000 0x80000>; 1063 1064 icssg1_mem: memories@0 { 1065 reg = <0x0 0x2000>, 1066 <0x2000 0x2000>, 1067 <0x10000 0x10000>; 1068 reg-names = "dram0", "dram1", 1069 "shrdram2"; 1070 }; 1071 1072 icssg1_cfg: cfg@26000 { 1073 compatible = "ti,pruss-cfg", "syscon"; 1074 reg = <0x26000 0x200>; 1075 #address-cells = <1>; 1076 #size-cells = <1>; 1077 ranges = <0x0 0x26000 0x2000>; 1078 1079 clocks { 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 1083 icssg1_coreclk_mux: coreclk-mux@3c { 1084 reg = <0x3c>; 1085 #clock-cells = <0>; 1086 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1087 <&k3_clks 63 3>; /* icssg1_iclk */ 1088 assigned-clocks = <&icssg1_coreclk_mux>; 1089 assigned-clock-parents = <&k3_clks 63 3>; 1090 }; 1091 1092 icssg1_iepclk_mux: iepclk-mux@30 { 1093 reg = <0x30>; 1094 #clock-cells = <0>; 1095 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1096 <&icssg1_coreclk_mux>; /* core_clk */ 1097 assigned-clocks = <&icssg1_iepclk_mux>; 1098 assigned-clock-parents = <&icssg1_coreclk_mux>; 1099 }; 1100 }; 1101 }; 1102 1103 icssg1_mii_rt: mii-rt@32000 { 1104 compatible = "ti,pruss-mii", "syscon"; 1105 reg = <0x32000 0x100>; 1106 }; 1107 1108 icssg1_mii_g_rt: mii-g-rt@33000 { 1109 compatible = "ti,pruss-mii-g", "syscon"; 1110 reg = <0x33000 0x1000>; 1111 }; 1112 1113 icssg1_intc: interrupt-controller@20000 { 1114 compatible = "ti,icssg-intc"; 1115 reg = <0x20000 0x2000>; 1116 interrupt-controller; 1117 #interrupt-cells = <3>; 1118 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1126 interrupt-names = "host_intr0", "host_intr1", 1127 "host_intr2", "host_intr3", 1128 "host_intr4", "host_intr5", 1129 "host_intr6", "host_intr7"; 1130 }; 1131 1132 pru1_0: pru@34000 { 1133 compatible = "ti,am654-pru"; 1134 reg = <0x34000 0x4000>, 1135 <0x22000 0x100>, 1136 <0x22400 0x100>; 1137 reg-names = "iram", "control", "debug"; 1138 firmware-name = "am65x-pru1_0-fw"; 1139 }; 1140 1141 rtu1_0: rtu@4000 { 1142 compatible = "ti,am654-rtu"; 1143 reg = <0x4000 0x2000>, 1144 <0x23000 0x100>, 1145 <0x23400 0x100>; 1146 reg-names = "iram", "control", "debug"; 1147 firmware-name = "am65x-rtu1_0-fw"; 1148 }; 1149 1150 tx_pru1_0: txpru@a000 { 1151 compatible = "ti,am654-tx-pru"; 1152 reg = <0xa000 0x1800>, 1153 <0x25000 0x100>, 1154 <0x25400 0x100>; 1155 reg-names = "iram", "control", "debug"; 1156 firmware-name = "am65x-txpru1_0-fw"; 1157 }; 1158 1159 pru1_1: pru@38000 { 1160 compatible = "ti,am654-pru"; 1161 reg = <0x38000 0x4000>, 1162 <0x24000 0x100>, 1163 <0x24400 0x100>; 1164 reg-names = "iram", "control", "debug"; 1165 firmware-name = "am65x-pru1_1-fw"; 1166 }; 1167 1168 rtu1_1: rtu@6000 { 1169 compatible = "ti,am654-rtu"; 1170 reg = <0x6000 0x2000>, 1171 <0x23800 0x100>, 1172 <0x23c00 0x100>; 1173 reg-names = "iram", "control", "debug"; 1174 firmware-name = "am65x-rtu1_1-fw"; 1175 }; 1176 1177 tx_pru1_1: txpru@c000 { 1178 compatible = "ti,am654-tx-pru"; 1179 reg = <0xc000 0x1800>, 1180 <0x25800 0x100>, 1181 <0x25c00 0x100>; 1182 reg-names = "iram", "control", "debug"; 1183 firmware-name = "am65x-txpru1_1-fw"; 1184 }; 1185 }; 1186 1187 icssg2: icssg@b200000 { 1188 compatible = "ti,am654-icssg"; 1189 reg = <0x00 0xb200000 0x00 0x80000>; 1190 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1191 #address-cells = <1>; 1192 #size-cells = <1>; 1193 ranges = <0x0 0x00 0xb200000 0x80000>; 1194 1195 icssg2_mem: memories@0 { 1196 reg = <0x0 0x2000>, 1197 <0x2000 0x2000>, 1198 <0x10000 0x10000>; 1199 reg-names = "dram0", "dram1", 1200 "shrdram2"; 1201 }; 1202 1203 icssg2_cfg: cfg@26000 { 1204 compatible = "ti,pruss-cfg", "syscon"; 1205 reg = <0x26000 0x200>; 1206 #address-cells = <1>; 1207 #size-cells = <1>; 1208 ranges = <0x0 0x26000 0x2000>; 1209 1210 clocks { 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 1214 icssg2_coreclk_mux: coreclk-mux@3c { 1215 reg = <0x3c>; 1216 #clock-cells = <0>; 1217 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1218 <&k3_clks 64 3>; /* icssg1_iclk */ 1219 assigned-clocks = <&icssg2_coreclk_mux>; 1220 assigned-clock-parents = <&k3_clks 64 3>; 1221 }; 1222 1223 icssg2_iepclk_mux: iepclk-mux@30 { 1224 reg = <0x30>; 1225 #clock-cells = <0>; 1226 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1227 <&icssg2_coreclk_mux>; /* core_clk */ 1228 assigned-clocks = <&icssg2_iepclk_mux>; 1229 assigned-clock-parents = <&icssg2_coreclk_mux>; 1230 }; 1231 }; 1232 }; 1233 1234 icssg2_mii_rt: mii-rt@32000 { 1235 compatible = "ti,pruss-mii", "syscon"; 1236 reg = <0x32000 0x100>; 1237 }; 1238 1239 icssg2_mii_g_rt: mii-g-rt@33000 { 1240 compatible = "ti,pruss-mii-g", "syscon"; 1241 reg = <0x33000 0x1000>; 1242 }; 1243 1244 icssg2_intc: interrupt-controller@20000 { 1245 compatible = "ti,icssg-intc"; 1246 reg = <0x20000 0x2000>; 1247 interrupt-controller; 1248 #interrupt-cells = <3>; 1249 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1257 interrupt-names = "host_intr0", "host_intr1", 1258 "host_intr2", "host_intr3", 1259 "host_intr4", "host_intr5", 1260 "host_intr6", "host_intr7"; 1261 }; 1262 1263 pru2_0: pru@34000 { 1264 compatible = "ti,am654-pru"; 1265 reg = <0x34000 0x4000>, 1266 <0x22000 0x100>, 1267 <0x22400 0x100>; 1268 reg-names = "iram", "control", "debug"; 1269 firmware-name = "am65x-pru2_0-fw"; 1270 }; 1271 1272 rtu2_0: rtu@4000 { 1273 compatible = "ti,am654-rtu"; 1274 reg = <0x4000 0x2000>, 1275 <0x23000 0x100>, 1276 <0x23400 0x100>; 1277 reg-names = "iram", "control", "debug"; 1278 firmware-name = "am65x-rtu2_0-fw"; 1279 }; 1280 1281 tx_pru2_0: txpru@a000 { 1282 compatible = "ti,am654-tx-pru"; 1283 reg = <0xa000 0x1800>, 1284 <0x25000 0x100>, 1285 <0x25400 0x100>; 1286 reg-names = "iram", "control", "debug"; 1287 firmware-name = "am65x-txpru2_0-fw"; 1288 }; 1289 1290 pru2_1: pru@38000 { 1291 compatible = "ti,am654-pru"; 1292 reg = <0x38000 0x4000>, 1293 <0x24000 0x100>, 1294 <0x24400 0x100>; 1295 reg-names = "iram", "control", "debug"; 1296 firmware-name = "am65x-pru2_1-fw"; 1297 }; 1298 1299 rtu2_1: rtu@6000 { 1300 compatible = "ti,am654-rtu"; 1301 reg = <0x6000 0x2000>, 1302 <0x23800 0x100>, 1303 <0x23c00 0x100>; 1304 reg-names = "iram", "control", "debug"; 1305 firmware-name = "am65x-rtu2_1-fw"; 1306 }; 1307 1308 tx_pru2_1: txpru@c000 { 1309 compatible = "ti,am654-tx-pru"; 1310 reg = <0xc000 0x1800>, 1311 <0x25800 0x100>, 1312 <0x25c00 0x100>; 1313 reg-names = "iram", "control", "debug"; 1314 firmware-name = "am65x-txpru2_1-fw"; 1315 }; 1316 }; 1317}; 1318