1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
5 */
6
7#include "k3-am642.dtsi"
8
9/ {
10	aliases {
11		i2c0 = &main_i2c0;
12		mmc0 = &sdhci0;
13		spi0 = &ospi0;
14	};
15
16	memory@80000000 {
17		device_type = "memory";
18		/* 1G RAM - default variant */
19		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
20
21	};
22
23	reserved-memory {
24		#address-cells = <2>;
25		#size-cells = <2>;
26		ranges;
27
28		secure_ddr: optee@9e800000 {
29			reg = <0x00 0x9e800000 0x00 0x01800000>;
30			alignment = <0x1000>;
31			no-map;
32		};
33
34		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
35			compatible = "shared-dma-pool";
36			reg = <0x00 0xa0000000 0x00 0x100000>;
37			no-map;
38		};
39
40		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
41			compatible = "shared-dma-pool";
42			reg = <0x00 0xa0100000 0x00 0xf00000>;
43			no-map;
44		};
45
46		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
47			compatible = "shared-dma-pool";
48			reg = <0x00 0xa1000000 0x00 0x100000>;
49			no-map;
50		};
51
52		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
53			compatible = "shared-dma-pool";
54			reg = <0x00 0xa1100000 0x00 0xf00000>;
55			no-map;
56		};
57
58		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
59			compatible = "shared-dma-pool";
60			reg = <0x00 0xa2000000 0x00 0x100000>;
61			no-map;
62		};
63
64		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
65			compatible = "shared-dma-pool";
66			reg = <0x00 0xa2100000 0x00 0xf00000>;
67			no-map;
68		};
69
70		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
71			compatible = "shared-dma-pool";
72			reg = <0x00 0xa3000000 0x00 0x100000>;
73			no-map;
74		};
75
76		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
77			compatible = "shared-dma-pool";
78			reg = <0x00 0xa3100000 0x00 0xf00000>;
79			no-map;
80		};
81
82		rtos_ipc_memory_region: ipc-memories@a5000000 {
83			reg = <0x00 0xa5000000 0x00 0x00800000>;
84			alignment = <0x1000>;
85			no-map;
86		};
87	};
88};
89
90&main_i2c0 {
91	pinctrl-names = "default";
92	pinctrl-0 = <&main_i2c0_pins>;
93	clock-frequency = <400000>;
94	status = "okay";
95
96	tmp1075: temperature-sensor@4a {
97		compatible = "ti,tmp1075";
98		reg = <0x4a>;
99	};
100
101	eeprom0: eeprom@50 {
102		compatible = "st,24c02", "atmel,24c02";
103		reg = <0x50>;
104		pagesize = <16>;
105		read-only;
106	};
107
108	pcf85063: rtc@51 {
109		compatible = "nxp,pcf85063a";
110		reg = <0x51>;
111		quartz-load-femtofarads = <12500>;
112	};
113
114	eeprom1: eeprom@54 {
115		compatible = "st,24c64", "atmel,24c64";
116		reg = <0x54>;
117		pagesize = <32>;
118	};
119};
120
121&mailbox0_cluster2 {
122	status = "okay";
123
124	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
125		ti,mbox-rx = <0 0 2>;
126		ti,mbox-tx = <1 0 2>;
127	};
128
129	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
130		ti,mbox-rx = <2 0 2>;
131		ti,mbox-tx = <3 0 2>;
132	};
133};
134
135&mailbox0_cluster4 {
136	status = "okay";
137
138	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
139		ti,mbox-rx = <0 0 2>;
140		ti,mbox-tx = <1 0 2>;
141	};
142
143	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
144		ti,mbox-rx = <2 0 2>;
145		ti,mbox-tx = <3 0 2>;
146	};
147};
148
149&mailbox0_cluster6 {
150	status = "okay";
151
152	mbox_m4_0: mbox-m4-0 {
153		ti,mbox-rx = <0 0 2>;
154		ti,mbox-tx = <1 0 2>;
155	};
156};
157
158&main_r5fss0_core0 {
159	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
160	memory-region = <&main_r5fss0_core0_dma_memory_region>,
161			<&main_r5fss0_core0_memory_region>;
162};
163
164&main_r5fss0_core1 {
165	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
166	memory-region = <&main_r5fss0_core1_dma_memory_region>,
167			<&main_r5fss0_core1_memory_region>;
168};
169
170&main_r5fss1_core0 {
171	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
172	memory-region = <&main_r5fss1_core0_dma_memory_region>,
173			<&main_r5fss1_core0_memory_region>;
174};
175
176&main_r5fss1_core1 {
177	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
178	memory-region = <&main_r5fss1_core1_dma_memory_region>,
179			<&main_r5fss1_core1_memory_region>;
180};
181
182&ospi0 {
183	status = "okay";
184	pinctrl-names = "default";
185	pinctrl-0 = <&ospi0_pins>;
186
187	flash@0 {
188		compatible = "jedec,spi-nor";
189		reg = <0>;
190		spi-tx-bus-width = <8>;
191		spi-rx-bus-width = <8>;
192		spi-max-frequency = <84000000>;
193		cdns,tshsl-ns = <60>;
194		cdns,tsd2d-ns = <60>;
195		cdns,tchsh-ns = <60>;
196		cdns,tslch-ns = <60>;
197		cdns,read-delay = <2>;
198
199		partitions {
200			compatible = "fixed-partitions";
201			#address-cells = <1>;
202			#size-cells = <1>;
203
204			/* Filled by bootloader */
205		};
206	};
207};
208
209&sdhci0 {
210	status = "okay";
211	non-removable;
212	disable-wp;
213	no-sdio;
214	no-sd;
215	ti,driver-strength-ohm = <50>;
216};
217
218&main_pmx0 {
219	main_i2c0_pins: main-i2c0-pins {
220		pinctrl-single,pins = <
221			/* (A18) I2C0_SCL */
222			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0)
223			/* (B18) I2C0_SDA */
224			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0)
225		>;
226	};
227
228	ospi0_pins: ospi0-pins {
229		pinctrl-single,pins = <
230			/* (N20) OSPI0_CLK */
231			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0)
232			/* (L19) OSPI0_CSn0 */
233			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0)
234			/* (M19) OSPI0_D0 */
235			AM64X_IOPAD(0x000c, PIN_INPUT, 0)
236			/* (M18) OSPI0_D1 */
237			AM64X_IOPAD(0x0010, PIN_INPUT, 0)
238			/* (M20) OSPI0_D2 */
239			AM64X_IOPAD(0x0014, PIN_INPUT, 0)
240			/* (M21) OSPI0_D3 */
241			AM64X_IOPAD(0x0018, PIN_INPUT, 0)
242			/* (P21) OSPI0_D4 */
243			AM64X_IOPAD(0x001c, PIN_INPUT, 0)
244			/* (P20) OSPI0_D5 */
245			AM64X_IOPAD(0x0020, PIN_INPUT, 0)
246			/* (N18) OSPI0_D6 */
247			AM64X_IOPAD(0x0024, PIN_INPUT, 0)
248			/* (M17) OSPI0_D7 */
249			AM64X_IOPAD(0x0028, PIN_INPUT, 0)
250			/* (N19) OSPI0_DQS */
251			AM64X_IOPAD(0x0008, PIN_INPUT, 0)
252		>;
253	};
254};
255