1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/mux/ti-serdes.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include "k3-am642.dtsi"
13
14/ {
15	compatible =  "ti,am642-sk", "ti,am642";
16	model = "Texas Instruments AM642 SK";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
21	};
22
23	memory@80000000 {
24		device_type = "memory";
25		/* 2G RAM */
26		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
27
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		secure_ddr: optee@9e800000 {
36			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
37			alignment = <0x1000>;
38			no-map;
39		};
40
41		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
42			compatible = "shared-dma-pool";
43			reg = <0x00 0xa0000000 0x00 0x100000>;
44			no-map;
45		};
46
47		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
48			compatible = "shared-dma-pool";
49			reg = <0x00 0xa0100000 0x00 0xf00000>;
50			no-map;
51		};
52
53		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
54			compatible = "shared-dma-pool";
55			reg = <0x00 0xa1000000 0x00 0x100000>;
56			no-map;
57		};
58
59		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
60			compatible = "shared-dma-pool";
61			reg = <0x00 0xa1100000 0x00 0xf00000>;
62			no-map;
63		};
64
65		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
66			compatible = "shared-dma-pool";
67			reg = <0x00 0xa2000000 0x00 0x100000>;
68			no-map;
69		};
70
71		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
72			compatible = "shared-dma-pool";
73			reg = <0x00 0xa2100000 0x00 0xf00000>;
74			no-map;
75		};
76
77		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
78			compatible = "shared-dma-pool";
79			reg = <0x00 0xa3000000 0x00 0x100000>;
80			no-map;
81		};
82
83		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
84			compatible = "shared-dma-pool";
85			reg = <0x00 0xa3100000 0x00 0xf00000>;
86			no-map;
87		};
88
89		rtos_ipc_memory_region: ipc-memories@a5000000 {
90			reg = <0x00 0xa5000000 0x00 0x00800000>;
91			alignment = <0x1000>;
92			no-map;
93		};
94	};
95
96	vusb_main: fixed-regulator-vusb-main5v0 {
97		/* USB MAIN INPUT 5V DC */
98		compatible = "regulator-fixed";
99		regulator-name = "vusb_main5v0";
100		regulator-min-microvolt = <5000000>;
101		regulator-max-microvolt = <5000000>;
102		regulator-always-on;
103		regulator-boot-on;
104	};
105
106	vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
107		/* output of LP8733xx */
108		compatible = "regulator-fixed";
109		regulator-name = "vcc_3v3_sys";
110		regulator-min-microvolt = <3300000>;
111		regulator-max-microvolt = <3300000>;
112		vin-supply = <&vusb_main>;
113		regulator-always-on;
114		regulator-boot-on;
115	};
116
117	vdd_mmc1: fixed-regulator-sd {
118		/* TPS2051BD */
119		compatible = "regulator-fixed";
120		regulator-name = "vdd_mmc1";
121		regulator-min-microvolt = <3300000>;
122		regulator-max-microvolt = <3300000>;
123		regulator-boot-on;
124		enable-active-high;
125		vin-supply = <&vcc_3v3_sys>;
126		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
127	};
128
129	com8_ls_en: regulator-1 {
130		compatible = "regulator-fixed";
131		regulator-name = "com8_ls_en";
132		regulator-min-microvolt = <3300000>;
133		regulator-max-microvolt = <3300000>;
134		regulator-always-on;
135		regulator-boot-on;
136		pinctrl-0 = <&main_com8_ls_en_pins_default>;
137		pinctrl-names = "default";
138		gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
139	};
140
141	wlan_en: regulator-2 {
142		/* output of SN74AVC4T245RSVR */
143		compatible = "regulator-fixed";
144		regulator-name = "wlan_en";
145		regulator-min-microvolt = <1800000>;
146		regulator-max-microvolt = <1800000>;
147		enable-active-high;
148		pinctrl-0 = <&main_wlan_en_pins_default>;
149		pinctrl-names = "default";
150		vin-supply = <&com8_ls_en>;
151		gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
152	};
153};
154
155&main_pmx0 {
156	main_mmc1_pins_default: main-mmc1-pins-default {
157		pinctrl-single,pins = <
158			AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
159			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
160			AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
161			AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
162			AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
163			AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
164			AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
165			AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
166		>;
167	};
168
169	main_usb0_pins_default: main-usb0-pins-default {
170		pinctrl-single,pins = <
171			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
172		>;
173	};
174
175	main_i2c1_pins_default: main-i2c1-pins-default {
176		pinctrl-single,pins = <
177			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
178			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
179		>;
180	};
181
182	mdio1_pins_default: mdio1-pins-default {
183		pinctrl-single,pins = <
184			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
185			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
186		>;
187	};
188
189	rgmii1_pins_default: rgmii1-pins-default {
190		pinctrl-single,pins = <
191			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
192			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
193			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
194			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
195			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
196			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
197			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
198			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
199			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
200			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
201			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
202			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
203		>;
204	};
205
206       rgmii2_pins_default: rgmii2-pins-default {
207		pinctrl-single,pins = <
208			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
209			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
210			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
211			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
212			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
213			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
214			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
215			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
216			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
217			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
218			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
219			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
220		>;
221	};
222
223	ospi0_pins_default: ospi0-pins-default {
224		pinctrl-single,pins = <
225			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
226			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
227			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
228			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
229			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
230			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
231			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
232			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
233			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
234			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
235			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
236		>;
237	};
238
239	main_ecap0_pins_default: main-ecap0-pins-default {
240		pinctrl-single,pins = <
241			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
242		>;
243	};
244	main_wlan_en_pins_default: main-wlan-en-pins-default {
245		pinctrl-single,pins = <
246			AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
247		>;
248	};
249
250	main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
251		pinctrl-single,pins = <
252			AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
253		>;
254	};
255
256	main_wlan_pins_default: main-wlan-pins-default {
257		pinctrl-single,pins = <
258			AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
259		>;
260	};
261};
262
263&mcu_uart0 {
264	status = "disabled";
265};
266
267&mcu_uart1 {
268	status = "disabled";
269};
270
271&main_uart1 {
272	/* main_uart1 is reserved for firmware usage */
273	status = "reserved";
274};
275
276&main_uart2 {
277	status = "disabled";
278};
279
280&main_uart3 {
281	status = "disabled";
282};
283
284&main_uart4 {
285	status = "disabled";
286};
287
288&main_uart5 {
289	status = "disabled";
290};
291
292&main_uart6 {
293	status = "disabled";
294};
295
296&mcu_i2c0 {
297	status = "disabled";
298};
299
300&mcu_i2c1 {
301	status = "disabled";
302};
303
304&main_i2c1 {
305	pinctrl-names = "default";
306	pinctrl-0 = <&main_i2c1_pins_default>;
307	clock-frequency = <400000>;
308
309	exp1: gpio@70 {
310		compatible = "nxp,pca9538";
311		reg = <0x70>;
312		gpio-controller;
313		#gpio-cells = <2>;
314		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
315				  "PRU_DETECT", "MMC1_SD_EN",
316				  "VPP_LDO_EN", "RPI_PS_3V3_En",
317				  "RPI_PS_5V0_En", "RPI_HAT_DETECT";
318	};
319};
320
321&main_i2c3 {
322	status = "disabled";
323};
324
325&mcu_spi0 {
326	status = "disabled";
327};
328
329&mcu_spi1 {
330	status = "disabled";
331};
332
333/* mcu_gpio0 is reserved for mcu firmware usage */
334&mcu_gpio0 {
335	status = "reserved";
336};
337
338&sdhci0 {
339	vmmc-supply = <&wlan_en>;
340	bus-width = <4>;
341	non-removable;
342	cap-power-off-card;
343	keep-power-in-suspend;
344	ti,driver-strength-ohm = <50>;
345
346	#address-cells = <1>;
347	#size-cells = <0>;
348	wlcore: wlcore@2 {
349		compatible = "ti,wl1837";
350		reg = <2>;
351		pinctrl-0 = <&main_wlan_pins_default>;
352		pinctrl-names = "default";
353		interrupt-parent = <&main_gpio0>;
354		interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
355	};
356};
357
358&sdhci1 {
359	/* SD/MMC */
360	vmmc-supply = <&vdd_mmc1>;
361	pinctrl-names = "default";
362	bus-width = <4>;
363	pinctrl-0 = <&main_mmc1_pins_default>;
364	ti,driver-strength-ohm = <50>;
365	disable-wp;
366};
367
368&serdes_ln_ctrl {
369	idle-states = <AM64_SERDES0_LANE0_USB>;
370};
371
372&serdes0 {
373	serdes0_usb_link: phy@0 {
374		reg = <0>;
375		cdns,num-lanes = <1>;
376		#phy-cells = <0>;
377		cdns,phy-type = <PHY_TYPE_USB3>;
378		resets = <&serdes_wiz0 1>;
379	};
380};
381
382&usbss0 {
383	ti,vbus-divider;
384};
385
386&usb0 {
387	dr_mode = "host";
388	maximum-speed = "super-speed";
389	pinctrl-names = "default";
390	pinctrl-0 = <&main_usb0_pins_default>;
391	phys = <&serdes0_usb_link>;
392	phy-names = "cdns3,usb3-phy";
393};
394
395&cpsw3g {
396	pinctrl-names = "default";
397	pinctrl-0 = <&mdio1_pins_default
398		     &rgmii1_pins_default
399		     &rgmii2_pins_default>;
400};
401
402&cpsw_port1 {
403	phy-mode = "rgmii-rxid";
404	phy-handle = <&cpsw3g_phy0>;
405};
406
407&cpsw_port2 {
408	phy-mode = "rgmii-rxid";
409	phy-handle = <&cpsw3g_phy1>;
410};
411
412&cpsw3g_mdio {
413	cpsw3g_phy0: ethernet-phy@0 {
414		reg = <0>;
415		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
416		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
417	};
418
419	cpsw3g_phy1: ethernet-phy@1 {
420		reg = <1>;
421		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
422		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
423	};
424};
425
426&tscadc0 {
427	status = "disabled";
428};
429
430&ospi0 {
431	pinctrl-names = "default";
432	pinctrl-0 = <&ospi0_pins_default>;
433
434	flash@0 {
435		compatible = "jedec,spi-nor";
436		reg = <0x0>;
437		spi-tx-bus-width = <8>;
438		spi-rx-bus-width = <8>;
439		spi-max-frequency = <25000000>;
440		cdns,tshsl-ns = <60>;
441		cdns,tsd2d-ns = <60>;
442		cdns,tchsh-ns = <60>;
443		cdns,tslch-ns = <60>;
444		cdns,read-delay = <4>;
445	};
446};
447
448&mailbox0_cluster2 {
449	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
450		ti,mbox-rx = <0 0 2>;
451		ti,mbox-tx = <1 0 2>;
452	};
453
454	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
455		ti,mbox-rx = <2 0 2>;
456		ti,mbox-tx = <3 0 2>;
457	};
458};
459
460&mailbox0_cluster3 {
461	status = "disabled";
462};
463
464&mailbox0_cluster4 {
465	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
466		ti,mbox-rx = <0 0 2>;
467		ti,mbox-tx = <1 0 2>;
468	};
469
470	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
471		ti,mbox-rx = <2 0 2>;
472		ti,mbox-tx = <3 0 2>;
473	};
474};
475
476&mailbox0_cluster5 {
477	status = "disabled";
478};
479
480&mailbox0_cluster6 {
481	mbox_m4_0: mbox-m4-0 {
482		ti,mbox-rx = <0 0 2>;
483		ti,mbox-tx = <1 0 2>;
484	};
485};
486
487&mailbox0_cluster7 {
488	status = "disabled";
489};
490
491&main_r5fss0_core0 {
492	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
493	memory-region = <&main_r5fss0_core0_dma_memory_region>,
494			<&main_r5fss0_core0_memory_region>;
495};
496
497&main_r5fss0_core1 {
498	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
499	memory-region = <&main_r5fss0_core1_dma_memory_region>,
500			<&main_r5fss0_core1_memory_region>;
501};
502
503&main_r5fss1_core0 {
504	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
505	memory-region = <&main_r5fss1_core0_dma_memory_region>,
506			<&main_r5fss1_core0_memory_region>;
507};
508
509&main_r5fss1_core1 {
510	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
511	memory-region = <&main_r5fss1_core1_dma_memory_region>,
512			<&main_r5fss1_core1_memory_region>;
513};
514
515&pcie0_rc {
516	status = "disabled";
517};
518
519&pcie0_ep {
520	status = "disabled";
521};
522
523&ecap0 {
524	/* PWM is available on Pin 1 of header J3 */
525	pinctrl-names = "default";
526	pinctrl-0 = <&main_ecap0_pins_default>;
527};
528
529&ecap1 {
530	status = "disabled";
531};
532
533&ecap2 {
534	status = "disabled";
535};
536
537&epwm0 {
538	status = "disabled";
539};
540
541&epwm1 {
542	status = "disabled";
543};
544
545&epwm2 {
546	status = "disabled";
547};
548
549&epwm3 {
550	status = "disabled";
551};
552
553&epwm4 {
554	/*
555	 * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat)
556	 * But RPi Hat will be used for other use cases, so marking epwm4 as disabled.
557	 */
558	status = "disabled";
559};
560
561&epwm5 {
562	/*
563	 * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat)
564	 * But RPi Hat will be used for other use cases, so marking epwm5 as disabled.
565	 */
566	status = "disabled";
567};
568
569&epwm6 {
570	status = "disabled";
571};
572
573&epwm7 {
574	status = "disabled";
575};
576
577&epwm8 {
578	status = "disabled";
579};
580
581&icssg0_mdio {
582	status = "disabled";
583};
584
585&icssg1_mdio {
586	status = "disabled";
587};
588
589&main_mcan0 {
590	status = "disabled";
591};
592
593&main_mcan1 {
594	status = "disabled";
595};
596