1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/mux/ti-serdes.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include "k3-am642.dtsi"
13
14/ {
15	compatible =  "ti,am642-sk", "ti,am642";
16	model = "Texas Instruments AM642 SK";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
21	};
22
23	memory@80000000 {
24		device_type = "memory";
25		/* 2G RAM */
26		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
27
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		secure_ddr: optee@9e800000 {
36			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
37			alignment = <0x1000>;
38			no-map;
39		};
40
41		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
42			compatible = "shared-dma-pool";
43			reg = <0x00 0xa0000000 0x00 0x100000>;
44			no-map;
45		};
46
47		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
48			compatible = "shared-dma-pool";
49			reg = <0x00 0xa0100000 0x00 0xf00000>;
50			no-map;
51		};
52
53		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
54			compatible = "shared-dma-pool";
55			reg = <0x00 0xa1000000 0x00 0x100000>;
56			no-map;
57		};
58
59		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
60			compatible = "shared-dma-pool";
61			reg = <0x00 0xa1100000 0x00 0xf00000>;
62			no-map;
63		};
64
65		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
66			compatible = "shared-dma-pool";
67			reg = <0x00 0xa2000000 0x00 0x100000>;
68			no-map;
69		};
70
71		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
72			compatible = "shared-dma-pool";
73			reg = <0x00 0xa2100000 0x00 0xf00000>;
74			no-map;
75		};
76
77		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
78			compatible = "shared-dma-pool";
79			reg = <0x00 0xa3000000 0x00 0x100000>;
80			no-map;
81		};
82
83		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
84			compatible = "shared-dma-pool";
85			reg = <0x00 0xa3100000 0x00 0xf00000>;
86			no-map;
87		};
88
89		rtos_ipc_memory_region: ipc-memories@a5000000 {
90			reg = <0x00 0xa5000000 0x00 0x00800000>;
91			alignment = <0x1000>;
92			no-map;
93		};
94	};
95
96	vusb_main: fixed-regulator-vusb-main5v0 {
97		/* USB MAIN INPUT 5V DC */
98		compatible = "regulator-fixed";
99		regulator-name = "vusb_main5v0";
100		regulator-min-microvolt = <5000000>;
101		regulator-max-microvolt = <5000000>;
102		regulator-always-on;
103		regulator-boot-on;
104	};
105
106	vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
107		/* output of LP8733xx */
108		compatible = "regulator-fixed";
109		regulator-name = "vcc_3v3_sys";
110		regulator-min-microvolt = <3300000>;
111		regulator-max-microvolt = <3300000>;
112		vin-supply = <&vusb_main>;
113		regulator-always-on;
114		regulator-boot-on;
115	};
116
117	vdd_mmc1: fixed-regulator-sd {
118		/* TPS2051BD */
119		compatible = "regulator-fixed";
120		regulator-name = "vdd_mmc1";
121		regulator-min-microvolt = <3300000>;
122		regulator-max-microvolt = <3300000>;
123		regulator-boot-on;
124		enable-active-high;
125		vin-supply = <&vcc_3v3_sys>;
126		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
127	};
128};
129
130&main_pmx0 {
131	main_mmc1_pins_default: main-mmc1-pins-default {
132		pinctrl-single,pins = <
133			AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
134			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
135			AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
136			AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
137			AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
138			AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
139			AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
140			AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
141		>;
142	};
143
144	main_usb0_pins_default: main-usb0-pins-default {
145		pinctrl-single,pins = <
146			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
147		>;
148	};
149
150	main_i2c1_pins_default: main-i2c1-pins-default {
151		pinctrl-single,pins = <
152			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
153			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
154		>;
155	};
156
157	mdio1_pins_default: mdio1-pins-default {
158		pinctrl-single,pins = <
159			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
160			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
161		>;
162	};
163
164	rgmii1_pins_default: rgmii1-pins-default {
165		pinctrl-single,pins = <
166			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
167			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
168			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
169			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
170			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
171			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
172			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
173			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
174			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
175			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
176			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
177			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
178		>;
179	};
180
181       rgmii2_pins_default: rgmii2-pins-default {
182		pinctrl-single,pins = <
183			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
184			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
185			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
186			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
187			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
188			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
189			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
190			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
191			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
192			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
193			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
194			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
195		>;
196	};
197
198	ospi0_pins_default: ospi0-pins-default {
199		pinctrl-single,pins = <
200			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
201			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
202			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
203			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
204			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
205			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
206			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
207			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
208			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
209			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
210			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
211		>;
212	};
213
214	main_ecap0_pins_default: main-ecap0-pins-default {
215		pinctrl-single,pins = <
216			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
217		>;
218	};
219};
220
221&mcu_uart0 {
222	status = "disabled";
223};
224
225&mcu_uart1 {
226	status = "disabled";
227};
228
229&main_uart1 {
230	/* main_uart1 is reserved for firmware usage */
231	status = "reserved";
232};
233
234&main_uart2 {
235	status = "disabled";
236};
237
238&main_uart3 {
239	status = "disabled";
240};
241
242&main_uart4 {
243	status = "disabled";
244};
245
246&main_uart5 {
247	status = "disabled";
248};
249
250&main_uart6 {
251	status = "disabled";
252};
253
254&mcu_i2c0 {
255	status = "disabled";
256};
257
258&mcu_i2c1 {
259	status = "disabled";
260};
261
262&main_i2c1 {
263	pinctrl-names = "default";
264	pinctrl-0 = <&main_i2c1_pins_default>;
265	clock-frequency = <400000>;
266
267	exp1: gpio@70 {
268		compatible = "nxp,pca9538";
269		reg = <0x70>;
270		gpio-controller;
271		#gpio-cells = <2>;
272		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
273				  "PRU_DETECT", "MMC1_SD_EN",
274				  "VPP_LDO_EN", "RPI_PS_3V3_En",
275				  "RPI_PS_5V0_En", "RPI_HAT_DETECT";
276	};
277};
278
279&main_i2c3 {
280	status = "disabled";
281};
282
283&mcu_spi0 {
284	status = "disabled";
285};
286
287&mcu_spi1 {
288	status = "disabled";
289};
290
291/* mcu_gpio0 is reserved for mcu firmware usage */
292&mcu_gpio0 {
293	status = "reserved";
294};
295
296&sdhci1 {
297	/* SD/MMC */
298	vmmc-supply = <&vdd_mmc1>;
299	pinctrl-names = "default";
300	bus-width = <4>;
301	pinctrl-0 = <&main_mmc1_pins_default>;
302	ti,driver-strength-ohm = <50>;
303	disable-wp;
304};
305
306&serdes_ln_ctrl {
307	idle-states = <AM64_SERDES0_LANE0_USB>;
308};
309
310&serdes0 {
311	serdes0_usb_link: phy@0 {
312		reg = <0>;
313		cdns,num-lanes = <1>;
314		#phy-cells = <0>;
315		cdns,phy-type = <PHY_TYPE_USB3>;
316		resets = <&serdes_wiz0 1>;
317	};
318};
319
320&usbss0 {
321	ti,vbus-divider;
322};
323
324&usb0 {
325	dr_mode = "host";
326	maximum-speed = "super-speed";
327	pinctrl-names = "default";
328	pinctrl-0 = <&main_usb0_pins_default>;
329	phys = <&serdes0_usb_link>;
330	phy-names = "cdns3,usb3-phy";
331};
332
333&cpsw3g {
334	pinctrl-names = "default";
335	pinctrl-0 = <&mdio1_pins_default
336		     &rgmii1_pins_default
337		     &rgmii2_pins_default>;
338};
339
340&cpsw_port1 {
341	phy-mode = "rgmii-rxid";
342	phy-handle = <&cpsw3g_phy0>;
343};
344
345&cpsw_port2 {
346	phy-mode = "rgmii-rxid";
347	phy-handle = <&cpsw3g_phy1>;
348};
349
350&cpsw3g_mdio {
351	cpsw3g_phy0: ethernet-phy@0 {
352		reg = <0>;
353		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
354		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
355	};
356
357	cpsw3g_phy1: ethernet-phy@1 {
358		reg = <1>;
359		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
360		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
361	};
362};
363
364&tscadc0 {
365	status = "disabled";
366};
367
368&ospi0 {
369	pinctrl-names = "default";
370	pinctrl-0 = <&ospi0_pins_default>;
371
372	flash@0 {
373		compatible = "jedec,spi-nor";
374		reg = <0x0>;
375		spi-tx-bus-width = <8>;
376		spi-rx-bus-width = <8>;
377		spi-max-frequency = <25000000>;
378		cdns,tshsl-ns = <60>;
379		cdns,tsd2d-ns = <60>;
380		cdns,tchsh-ns = <60>;
381		cdns,tslch-ns = <60>;
382		cdns,read-delay = <4>;
383	};
384};
385
386&mailbox0_cluster2 {
387	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
388		ti,mbox-rx = <0 0 2>;
389		ti,mbox-tx = <1 0 2>;
390	};
391
392	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
393		ti,mbox-rx = <2 0 2>;
394		ti,mbox-tx = <3 0 2>;
395	};
396};
397
398&mailbox0_cluster3 {
399	status = "disabled";
400};
401
402&mailbox0_cluster4 {
403	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
404		ti,mbox-rx = <0 0 2>;
405		ti,mbox-tx = <1 0 2>;
406	};
407
408	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
409		ti,mbox-rx = <2 0 2>;
410		ti,mbox-tx = <3 0 2>;
411	};
412};
413
414&mailbox0_cluster5 {
415	status = "disabled";
416};
417
418&mailbox0_cluster6 {
419	mbox_m4_0: mbox-m4-0 {
420		ti,mbox-rx = <0 0 2>;
421		ti,mbox-tx = <1 0 2>;
422	};
423};
424
425&mailbox0_cluster7 {
426	status = "disabled";
427};
428
429&main_r5fss0_core0 {
430	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
431	memory-region = <&main_r5fss0_core0_dma_memory_region>,
432			<&main_r5fss0_core0_memory_region>;
433};
434
435&main_r5fss0_core1 {
436	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
437	memory-region = <&main_r5fss0_core1_dma_memory_region>,
438			<&main_r5fss0_core1_memory_region>;
439};
440
441&main_r5fss1_core0 {
442	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
443	memory-region = <&main_r5fss1_core0_dma_memory_region>,
444			<&main_r5fss1_core0_memory_region>;
445};
446
447&main_r5fss1_core1 {
448	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
449	memory-region = <&main_r5fss1_core1_dma_memory_region>,
450			<&main_r5fss1_core1_memory_region>;
451};
452
453&pcie0_rc {
454	status = "disabled";
455};
456
457&pcie0_ep {
458	status = "disabled";
459};
460
461&ecap0 {
462	/* PWM is available on Pin 1 of header J3 */
463	pinctrl-names = "default";
464	pinctrl-0 = <&main_ecap0_pins_default>;
465};
466
467&ecap1 {
468	status = "disabled";
469};
470
471&ecap2 {
472	status = "disabled";
473};
474
475&epwm0 {
476	status = "disabled";
477};
478
479&epwm1 {
480	status = "disabled";
481};
482
483&epwm2 {
484	status = "disabled";
485};
486
487&epwm3 {
488	status = "disabled";
489};
490
491&epwm4 {
492	/*
493	 * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat)
494	 * But RPi Hat will be used for other use cases, so marking epwm4 as disabled.
495	 */
496	status = "disabled";
497};
498
499&epwm5 {
500	/*
501	 * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat)
502	 * But RPi Hat will be used for other use cases, so marking epwm5 as disabled.
503	 */
504	status = "disabled";
505};
506
507&epwm6 {
508	status = "disabled";
509};
510
511&epwm7 {
512	status = "disabled";
513};
514
515&epwm8 {
516	status = "disabled";
517};
518
519&icssg0_mdio {
520	status = "disabled";
521};
522
523&icssg1_mdio {
524	status = "disabled";
525};
526
527&main_mcan0 {
528	status = "disabled";
529};
530
531&main_mcan1 {
532	status = "disabled";
533};
534