1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/leds/common.h>
12#include "k3-am642.dtsi"
13
14#include "k3-serdes.h"
15
16/ {
17	compatible = "ti,am642-sk", "ti,am642";
18	model = "Texas Instruments AM642 SK";
19
20	chosen {
21		stdout-path = &main_uart0;
22	};
23
24	aliases {
25		serial0 = &mcu_uart0;
26		serial1 = &main_uart1;
27		serial2 = &main_uart0;
28		i2c0 = &main_i2c0;
29		i2c1 = &main_i2c1;
30		mmc0 = &sdhci0;
31		mmc1 = &sdhci1;
32		ethernet0 = &cpsw_port1;
33		ethernet1 = &cpsw_port2;
34	};
35
36	memory@80000000 {
37		device_type = "memory";
38		/* 2G RAM */
39		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
40	};
41
42	reserved-memory {
43		#address-cells = <2>;
44		#size-cells = <2>;
45		ranges;
46
47		secure_ddr: optee@9e800000 {
48			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
49			alignment = <0x1000>;
50			no-map;
51		};
52
53		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
54			compatible = "shared-dma-pool";
55			reg = <0x00 0xa0000000 0x00 0x100000>;
56			no-map;
57		};
58
59		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
60			compatible = "shared-dma-pool";
61			reg = <0x00 0xa0100000 0x00 0xf00000>;
62			no-map;
63		};
64
65		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
66			compatible = "shared-dma-pool";
67			reg = <0x00 0xa1000000 0x00 0x100000>;
68			no-map;
69		};
70
71		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
72			compatible = "shared-dma-pool";
73			reg = <0x00 0xa1100000 0x00 0xf00000>;
74			no-map;
75		};
76
77		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
78			compatible = "shared-dma-pool";
79			reg = <0x00 0xa2000000 0x00 0x100000>;
80			no-map;
81		};
82
83		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
84			compatible = "shared-dma-pool";
85			reg = <0x00 0xa2100000 0x00 0xf00000>;
86			no-map;
87		};
88
89		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
90			compatible = "shared-dma-pool";
91			reg = <0x00 0xa3000000 0x00 0x100000>;
92			no-map;
93		};
94
95		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
96			compatible = "shared-dma-pool";
97			reg = <0x00 0xa3100000 0x00 0xf00000>;
98			no-map;
99		};
100
101		rtos_ipc_memory_region: ipc-memories@a5000000 {
102			reg = <0x00 0xa5000000 0x00 0x00800000>;
103			alignment = <0x1000>;
104			no-map;
105		};
106	};
107
108	vusb_main: regulator-0 {
109		/* USB MAIN INPUT 5V DC */
110		compatible = "regulator-fixed";
111		regulator-name = "vusb_main5v0";
112		regulator-min-microvolt = <5000000>;
113		regulator-max-microvolt = <5000000>;
114		regulator-always-on;
115		regulator-boot-on;
116	};
117
118	vcc_3v3_sys: regulator-1 {
119		/* output of LP8733xx */
120		compatible = "regulator-fixed";
121		regulator-name = "vcc_3v3_sys";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		vin-supply = <&vusb_main>;
125		regulator-always-on;
126		regulator-boot-on;
127	};
128
129	vdd_mmc1: regulator-2 {
130		/* TPS2051BD */
131		compatible = "regulator-fixed";
132		regulator-name = "vdd_mmc1";
133		regulator-min-microvolt = <3300000>;
134		regulator-max-microvolt = <3300000>;
135		regulator-boot-on;
136		enable-active-high;
137		vin-supply = <&vcc_3v3_sys>;
138		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
139	};
140
141	com8_ls_en: regulator-3 {
142		compatible = "regulator-fixed";
143		regulator-name = "com8_ls_en";
144		regulator-min-microvolt = <3300000>;
145		regulator-max-microvolt = <3300000>;
146		regulator-always-on;
147		regulator-boot-on;
148		pinctrl-0 = <&main_com8_ls_en_pins_default>;
149		pinctrl-names = "default";
150		gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
151	};
152
153	wlan_en: regulator-4 {
154		/* output of SN74AVC4T245RSVR */
155		compatible = "regulator-fixed";
156		regulator-name = "wlan_en";
157		regulator-min-microvolt = <1800000>;
158		regulator-max-microvolt = <1800000>;
159		enable-active-high;
160		pinctrl-0 = <&main_wlan_en_pins_default>;
161		pinctrl-names = "default";
162		vin-supply = <&com8_ls_en>;
163		gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
164	};
165
166	led-controller {
167		compatible = "gpio-leds";
168
169		led-0 {
170			color = <LED_COLOR_ID_GREEN>;
171			function = LED_FUNCTION_INDICATOR;
172			function-enumerator = <1>;
173			gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
174			default-state = "off";
175		};
176
177		led-1 {
178			color = <LED_COLOR_ID_RED>;
179			function = LED_FUNCTION_INDICATOR;
180			function-enumerator = <2>;
181			gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
182			default-state = "off";
183		};
184
185		led-2 {
186			color = <LED_COLOR_ID_GREEN>;
187			function = LED_FUNCTION_INDICATOR;
188			function-enumerator = <3>;
189			gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
190			default-state = "off";
191		};
192
193		led-3 {
194			color = <LED_COLOR_ID_AMBER>;
195			function = LED_FUNCTION_INDICATOR;
196			function-enumerator = <4>;
197			gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
198			default-state = "off";
199		};
200
201		led-4 {
202			color = <LED_COLOR_ID_GREEN>;
203			function = LED_FUNCTION_INDICATOR;
204			function-enumerator = <5>;
205			gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
206			default-state = "off";
207		};
208
209		led-5 {
210			color = <LED_COLOR_ID_RED>;
211			function = LED_FUNCTION_INDICATOR;
212			function-enumerator = <6>;
213			gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
214			default-state = "off";
215		};
216
217		led-6 {
218			color = <LED_COLOR_ID_GREEN>;
219			function = LED_FUNCTION_INDICATOR;
220			function-enumerator = <7>;
221			gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
222			default-state = "off";
223		};
224
225		led-7 {
226			color = <LED_COLOR_ID_AMBER>;
227			function = LED_FUNCTION_HEARTBEAT;
228			function-enumerator = <8>;
229			linux,default-trigger = "heartbeat";
230			gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
231		};
232	};
233};
234
235&main_pmx0 {
236	main_mmc1_pins_default: main-mmc1-default-pins {
237		pinctrl-single,pins = <
238			AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
239			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
240			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
241			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
242			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
243			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
244			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
245			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
246			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
247		>;
248	};
249
250	main_uart0_pins_default: main-uart0-default-pins {
251		pinctrl-single,pins = <
252			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
253			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
254			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
255			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
256		>;
257	};
258
259	main_uart1_pins_default: main-uart1-default-pins {
260		pinctrl-single,pins = <
261			AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
262			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
263			AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
264			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
265		>;
266	};
267
268	main_usb0_pins_default: main-usb0-default-pins {
269		pinctrl-single,pins = <
270			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
271		>;
272	};
273
274	main_i2c0_pins_default: main-i2c0-default-pins {
275		pinctrl-single,pins = <
276			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
277			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
278		>;
279	};
280
281	main_i2c1_pins_default: main-i2c1-default-pins {
282		pinctrl-single,pins = <
283			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
284			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
285		>;
286	};
287
288	mdio1_pins_default: mdio1-default-pins {
289		pinctrl-single,pins = <
290			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
291			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
292		>;
293	};
294
295	rgmii1_pins_default: rgmii1-default-pins {
296		pinctrl-single,pins = <
297			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
298			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
299			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
300			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
301			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
302			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
303			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
304			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
305			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
306			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
307			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
308			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
309		>;
310	};
311
312       rgmii2_pins_default: rgmii2-default-pins {
313		pinctrl-single,pins = <
314			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
315			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
316			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
317			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
318			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
319			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
320			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
321			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
322			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
323			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
324			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
325			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
326		>;
327	};
328
329	ospi0_pins_default: ospi0-default-pins {
330		pinctrl-single,pins = <
331			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
332			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
333			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
334			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
335			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
336			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
337			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
338			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
339			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
340			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
341			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
342		>;
343	};
344
345	main_ecap0_pins_default: main-ecap0-default-pins {
346		pinctrl-single,pins = <
347			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
348		>;
349	};
350	main_wlan_en_pins_default: main-wlan-en-default-pins {
351		pinctrl-single,pins = <
352			AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
353		>;
354	};
355
356	main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
357		pinctrl-single,pins = <
358			AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
359		>;
360	};
361
362	main_wlan_pins_default: main-wlan-default-pins {
363		pinctrl-single,pins = <
364			AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
365		>;
366	};
367};
368
369&main_uart0 {
370	status = "okay";
371	pinctrl-names = "default";
372	pinctrl-0 = <&main_uart0_pins_default>;
373	current-speed = <115200>;
374};
375
376&main_uart1 {
377	/* main_uart1 is reserved for firmware usage */
378	status = "reserved";
379	pinctrl-names = "default";
380	pinctrl-0 = <&main_uart1_pins_default>;
381};
382
383&main_i2c0 {
384	status = "okay";
385	pinctrl-names = "default";
386	pinctrl-0 = <&main_i2c0_pins_default>;
387	clock-frequency = <400000>;
388
389	eeprom@51 {
390		compatible = "atmel,24c512";
391		reg = <0x51>;
392	};
393};
394
395&main_i2c1 {
396	status = "okay";
397	pinctrl-names = "default";
398	pinctrl-0 = <&main_i2c1_pins_default>;
399	clock-frequency = <400000>;
400
401	exp1: gpio@70 {
402		compatible = "nxp,pca9538";
403		reg = <0x70>;
404		gpio-controller;
405		#gpio-cells = <2>;
406		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
407				  "PRU_DETECT", "MMC1_SD_EN",
408				  "VPP_LDO_EN", "RPI_PS_3V3_En",
409				  "RPI_PS_5V0_En", "RPI_HAT_DETECT";
410	};
411
412	exp2: gpio@60 {
413		compatible = "ti,tpic2810";
414		reg = <0x60>;
415		gpio-controller;
416		#gpio-cells = <2>;
417		gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
418	};
419};
420
421/* mcu_gpio0 is reserved for mcu firmware usage */
422&mcu_gpio0 {
423	status = "reserved";
424};
425
426&sdhci0 {
427	vmmc-supply = <&wlan_en>;
428	bus-width = <4>;
429	non-removable;
430	cap-power-off-card;
431	keep-power-in-suspend;
432	ti,driver-strength-ohm = <50>;
433
434	#address-cells = <1>;
435	#size-cells = <0>;
436	wlcore: wlcore@2 {
437		compatible = "ti,wl1837";
438		reg = <2>;
439		pinctrl-0 = <&main_wlan_pins_default>;
440		pinctrl-names = "default";
441		interrupt-parent = <&main_gpio0>;
442		interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
443	};
444};
445
446&sdhci1 {
447	/* SD/MMC */
448	vmmc-supply = <&vdd_mmc1>;
449	pinctrl-names = "default";
450	bus-width = <4>;
451	pinctrl-0 = <&main_mmc1_pins_default>;
452	ti,driver-strength-ohm = <50>;
453	disable-wp;
454};
455
456&serdes_ln_ctrl {
457	idle-states = <AM64_SERDES0_LANE0_USB>;
458};
459
460&serdes0 {
461	serdes0_usb_link: phy@0 {
462		reg = <0>;
463		cdns,num-lanes = <1>;
464		#phy-cells = <0>;
465		cdns,phy-type = <PHY_TYPE_USB3>;
466		resets = <&serdes_wiz0 1>;
467	};
468};
469
470&usbss0 {
471	ti,vbus-divider;
472};
473
474&usb0 {
475	dr_mode = "host";
476	maximum-speed = "super-speed";
477	pinctrl-names = "default";
478	pinctrl-0 = <&main_usb0_pins_default>;
479	phys = <&serdes0_usb_link>;
480	phy-names = "cdns3,usb3-phy";
481};
482
483&cpsw3g {
484	pinctrl-names = "default";
485	pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
486};
487
488&cpsw_port1 {
489	phy-mode = "rgmii-rxid";
490	phy-handle = <&cpsw3g_phy0>;
491};
492
493&cpsw_port2 {
494	phy-mode = "rgmii-rxid";
495	phy-handle = <&cpsw3g_phy1>;
496};
497
498&cpsw3g_mdio {
499	status = "okay";
500	pinctrl-names = "default";
501	pinctrl-0 = <&mdio1_pins_default>;
502
503	cpsw3g_phy0: ethernet-phy@0 {
504		reg = <0>;
505		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
506		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
507	};
508
509	cpsw3g_phy1: ethernet-phy@1 {
510		reg = <1>;
511		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
512		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
513	};
514};
515
516&ospi0 {
517	status = "okay";
518	pinctrl-names = "default";
519	pinctrl-0 = <&ospi0_pins_default>;
520
521	flash@0 {
522		compatible = "jedec,spi-nor";
523		reg = <0x0>;
524		spi-tx-bus-width = <8>;
525		spi-rx-bus-width = <8>;
526		spi-max-frequency = <25000000>;
527		cdns,tshsl-ns = <60>;
528		cdns,tsd2d-ns = <60>;
529		cdns,tchsh-ns = <60>;
530		cdns,tslch-ns = <60>;
531		cdns,read-delay = <4>;
532
533		partitions {
534			compatible = "fixed-partitions";
535			#address-cells = <1>;
536			#size-cells = <1>;
537
538			partition@0 {
539				label = "ospi.tiboot3";
540				reg = <0x0 0x100000>;
541			};
542
543			partition@100000 {
544				label = "ospi.tispl";
545				reg = <0x100000 0x200000>;
546			};
547
548			partition@300000 {
549				label = "ospi.u-boot";
550				reg = <0x300000 0x400000>;
551			};
552
553			partition@700000 {
554				label = "ospi.env";
555				reg = <0x700000 0x40000>;
556			};
557
558			partition@740000 {
559				label = "ospi.env.backup";
560				reg = <0x740000 0x40000>;
561			};
562
563			partition@800000 {
564				label = "ospi.rootfs";
565				reg = <0x800000 0x37c0000>;
566			};
567
568			partition@3fc0000 {
569				label = "ospi.phypattern";
570				reg = <0x3fc0000 0x40000>;
571			};
572		};
573	};
574};
575
576&mailbox0_cluster2 {
577	status = "okay";
578
579	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
580		ti,mbox-rx = <0 0 2>;
581		ti,mbox-tx = <1 0 2>;
582	};
583
584	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
585		ti,mbox-rx = <2 0 2>;
586		ti,mbox-tx = <3 0 2>;
587	};
588};
589
590&mailbox0_cluster4 {
591	status = "okay";
592
593	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
594		ti,mbox-rx = <0 0 2>;
595		ti,mbox-tx = <1 0 2>;
596	};
597
598	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
599		ti,mbox-rx = <2 0 2>;
600		ti,mbox-tx = <3 0 2>;
601	};
602};
603
604&mailbox0_cluster6 {
605	status = "okay";
606
607	mbox_m4_0: mbox-m4-0 {
608		ti,mbox-rx = <0 0 2>;
609		ti,mbox-tx = <1 0 2>;
610	};
611};
612
613&main_r5fss0_core0 {
614	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
615	memory-region = <&main_r5fss0_core0_dma_memory_region>,
616			<&main_r5fss0_core0_memory_region>;
617};
618
619&main_r5fss0_core1 {
620	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
621	memory-region = <&main_r5fss0_core1_dma_memory_region>,
622			<&main_r5fss0_core1_memory_region>;
623};
624
625&main_r5fss1_core0 {
626	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
627	memory-region = <&main_r5fss1_core0_dma_memory_region>,
628			<&main_r5fss1_core0_memory_region>;
629};
630
631&main_r5fss1_core1 {
632	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
633	memory-region = <&main_r5fss1_core1_dma_memory_region>,
634			<&main_r5fss1_core1_memory_region>;
635};
636
637&ecap0 {
638	status = "okay";
639	/* PWM is available on Pin 1 of header J3 */
640	pinctrl-names = "default";
641	pinctrl-0 = <&main_ecap0_pins_default>;
642};
643