1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM64 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_uart0: serial@4a00000 { 10 compatible = "ti,am64-uart", "ti,am654-uart"; 11 reg = <0x00 0x04a00000 0x00 0x100>; 12 reg-shift = <2>; 13 reg-io-width = <4>; 14 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 15 clock-frequency = <48000000>; 16 current-speed = <115200>; 17 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 18 clocks = <&k3_clks 149 0>; 19 clock-names = "fclk"; 20 }; 21 22 mcu_uart1: serial@4a10000 { 23 compatible = "ti,am64-uart", "ti,am654-uart"; 24 reg = <0x00 0x04a10000 0x00 0x100>; 25 reg-shift = <2>; 26 reg-io-width = <4>; 27 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 28 clock-frequency = <48000000>; 29 current-speed = <115200>; 30 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 31 clocks = <&k3_clks 160 0>; 32 clock-names = "fclk"; 33 }; 34 35 mcu_i2c0: i2c@4900000 { 36 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 37 reg = <0x00 0x04900000 0x00 0x100>; 38 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 42 clocks = <&k3_clks 106 2>; 43 clock-names = "fck"; 44 }; 45 46 mcu_i2c1: i2c@4910000 { 47 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 48 reg = <0x00 0x04910000 0x00 0x100>; 49 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 53 clocks = <&k3_clks 107 2>; 54 clock-names = "fck"; 55 }; 56 57 mcu_spi0: spi@4b00000 { 58 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 59 reg = <0x00 0x04b00000 0x00 0x400>; 60 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 61 #address-cells = <1>; 62 #size-cells = <0>; 63 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 64 clocks = <&k3_clks 147 0>; 65 }; 66 67 mcu_spi1: spi@4b10000 { 68 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 69 reg = <0x00 0x04b10000 0x00 0x400>; 70 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 74 clocks = <&k3_clks 148 0>; 75 }; 76 77 mcu_gpio_intr: interrupt-controller@4210000 { 78 compatible = "ti,sci-intr"; 79 reg = <0x00 0x04210000 0x00 0x200>; 80 ti,intr-trigger-type = <1>; 81 interrupt-controller; 82 interrupt-parent = <&gic500>; 83 #interrupt-cells = <1>; 84 ti,sci = <&dmsc>; 85 ti,sci-dev-id = <5>; 86 ti,interrupt-ranges = <0 104 4>; 87 }; 88 89 mcu_gpio0: gpio@4201000 { 90 compatible = "ti,am64-gpio", "keystone-gpio"; 91 reg = <0x0 0x4201000 0x0 0x100>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 interrupt-parent = <&mcu_gpio_intr>; 95 interrupts = <30>, <31>; 96 interrupt-controller; 97 #interrupt-cells = <2>; 98 ti,ngpio = <23>; 99 ti,davinci-gpio-unbanked = <0>; 100 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 101 clocks = <&k3_clks 79 0>; 102 clock-names = "gpio"; 103 }; 104}; 105