1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM64 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu {
9	mcu_uart0: serial@4a00000 {
10		compatible = "ti,am64-uart", "ti,am654-uart";
11		reg = <0x00 0x04a00000 0x00 0x100>;
12		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
13		clock-frequency = <48000000>;
14		current-speed = <115200>;
15		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
16		clocks = <&k3_clks 149 0>;
17		clock-names = "fclk";
18	};
19
20	mcu_uart1: serial@4a10000 {
21		compatible = "ti,am64-uart", "ti,am654-uart";
22		reg = <0x00 0x04a10000 0x00 0x100>;
23		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
24		clock-frequency = <48000000>;
25		current-speed = <115200>;
26		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
27		clocks = <&k3_clks 160 0>;
28		clock-names = "fclk";
29	};
30
31	mcu_i2c0: i2c@4900000 {
32		compatible = "ti,am64-i2c", "ti,omap4-i2c";
33		reg = <0x00 0x04900000 0x00 0x100>;
34		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
35		#address-cells = <1>;
36		#size-cells = <0>;
37		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
38		clocks = <&k3_clks 106 2>;
39		clock-names = "fck";
40	};
41
42	mcu_i2c1: i2c@4910000 {
43		compatible = "ti,am64-i2c", "ti,omap4-i2c";
44		reg = <0x00 0x04910000 0x00 0x100>;
45		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
46		#address-cells = <1>;
47		#size-cells = <0>;
48		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
49		clocks = <&k3_clks 107 2>;
50		clock-names = "fck";
51	};
52
53	mcu_spi0: spi@4b00000 {
54		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
55		reg = <0x00 0x04b00000 0x00 0x400>;
56		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
57		#address-cells = <1>;
58		#size-cells = <0>;
59		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
60		clocks = <&k3_clks 147 0>;
61	};
62
63	mcu_spi1: spi@4b10000 {
64		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
65		reg = <0x00 0x04b10000 0x00 0x400>;
66		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
67		#address-cells = <1>;
68		#size-cells = <0>;
69		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
70		clocks = <&k3_clks 148 0>;
71	};
72
73	mcu_gpio_intr: interrupt-controller@4210000 {
74		compatible = "ti,sci-intr";
75		reg = <0x00 0x04210000 0x00 0x200>;
76		ti,intr-trigger-type = <1>;
77		interrupt-controller;
78		interrupt-parent = <&gic500>;
79		#interrupt-cells = <1>;
80		ti,sci = <&dmsc>;
81		ti,sci-dev-id = <5>;
82		ti,interrupt-ranges = <0 104 4>;
83	};
84
85	mcu_gpio0: gpio@4201000 {
86		compatible = "ti,am64-gpio", "ti,keystone-gpio";
87		reg = <0x0 0x4201000 0x0 0x100>;
88		gpio-controller;
89		#gpio-cells = <2>;
90		interrupt-parent = <&mcu_gpio_intr>;
91		interrupts = <30>, <31>;
92		interrupt-controller;
93		#interrupt-cells = <2>;
94		ti,ngpio = <23>;
95		ti,davinci-gpio-unbanked = <0>;
96		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
97		clocks = <&k3_clks 79 0>;
98		clock-names = "gpio";
99	};
100};
101