1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x0 0x43000000 0x0 0x20000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 47 serdes_ln_ctrl: mux-controller { 48 compatible = "mmio-mux"; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 51 }; 52 }; 53 54 gic500: interrupt-controller@1800000 { 55 compatible = "arm,gic-v3"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 62 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 63 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 64 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 65 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 66 /* 67 * vcpumntirq: 68 * virtual CPU interface maintenance interrupt 69 */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 dmss: bus@48000000 { 82 compatible = "simple-mfd"; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 dma-ranges; 86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 87 88 ti,sci-dev-id = <25>; 89 90 secure_proxy_main: mailbox@4d000000 { 91 compatible = "ti,am654-secure-proxy"; 92 #mbox-cells = <1>; 93 reg-names = "target_data", "rt", "scfg"; 94 reg = <0x00 0x4d000000 0x00 0x80000>, 95 <0x00 0x4a600000 0x00 0x80000>, 96 <0x00 0x4a400000 0x00 0x80000>; 97 interrupt-names = "rx_012"; 98 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 99 }; 100 101 inta_main_dmss: interrupt-controller@48000000 { 102 compatible = "ti,sci-inta"; 103 reg = <0x00 0x48000000 0x00 0x100000>; 104 #interrupt-cells = <0>; 105 interrupt-controller; 106 interrupt-parent = <&gic500>; 107 msi-controller; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <28>; 110 ti,interrupt-ranges = <4 68 36>; 111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 112 }; 113 114 main_bcdma: dma-controller@485c0100 { 115 compatible = "ti,am64-dmss-bcdma"; 116 reg = <0x00 0x485c0100 0x00 0x100>, 117 <0x00 0x4c000000 0x00 0x20000>, 118 <0x00 0x4a820000 0x00 0x20000>, 119 <0x00 0x4aa40000 0x00 0x20000>, 120 <0x00 0x4bc00000 0x00 0x100000>; 121 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 122 msi-parent = <&inta_main_dmss>; 123 #dma-cells = <3>; 124 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <26>; 127 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 128 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 129 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 130 }; 131 132 main_pktdma: dma-controller@485c0000 { 133 compatible = "ti,am64-dmss-pktdma"; 134 reg = <0x00 0x485c0000 0x00 0x100>, 135 <0x00 0x4a800000 0x00 0x20000>, 136 <0x00 0x4aa00000 0x00 0x40000>, 137 <0x00 0x4b800000 0x00 0x400000>; 138 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 139 msi-parent = <&inta_main_dmss>; 140 #dma-cells = <2>; 141 142 ti,sci = <&dmsc>; 143 ti,sci-dev-id = <30>; 144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 145 <0x24>, /* CPSW_TX_CHAN */ 146 <0x25>, /* SAUL_TX_0_CHAN */ 147 <0x26>, /* SAUL_TX_1_CHAN */ 148 <0x27>, /* ICSSG_0_TX_CHAN */ 149 <0x28>; /* ICSSG_1_TX_CHAN */ 150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 151 <0x11>, /* RING_CPSW_TX_CHAN */ 152 <0x12>, /* RING_SAUL_TX_0_CHAN */ 153 <0x13>, /* RING_SAUL_TX_1_CHAN */ 154 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 155 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 157 <0x2b>, /* CPSW_RX_CHAN */ 158 <0x2d>, /* SAUL_RX_0_CHAN */ 159 <0x2f>, /* SAUL_RX_1_CHAN */ 160 <0x31>, /* SAUL_RX_2_CHAN */ 161 <0x33>, /* SAUL_RX_3_CHAN */ 162 <0x35>, /* ICSSG_0_RX_CHAN */ 163 <0x37>; /* ICSSG_1_RX_CHAN */ 164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 165 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 170 }; 171 }; 172 173 dmsc: system-controller@44043000 { 174 compatible = "ti,k2g-sci"; 175 ti,host-id = <12>; 176 mbox-names = "rx", "tx"; 177 mboxes= <&secure_proxy_main 12>, 178 <&secure_proxy_main 13>; 179 reg-names = "debug_messages"; 180 reg = <0x00 0x44043000 0x00 0xfe0>; 181 182 k3_pds: power-controller { 183 compatible = "ti,sci-pm-domain"; 184 #power-domain-cells = <2>; 185 }; 186 187 k3_clks: clock-controller { 188 compatible = "ti,k2g-sci-clk"; 189 #clock-cells = <2>; 190 }; 191 192 k3_reset: reset-controller { 193 compatible = "ti,sci-reset"; 194 #reset-cells = <2>; 195 }; 196 }; 197 198 main_pmx0: pinctrl@f4000 { 199 compatible = "pinctrl-single"; 200 reg = <0x00 0xf4000 0x00 0x2d0>; 201 #pinctrl-cells = <1>; 202 pinctrl-single,register-width = <32>; 203 pinctrl-single,function-mask = <0xffffffff>; 204 }; 205 206 main_conf: syscon@43000000 { 207 compatible = "syscon", "simple-mfd"; 208 reg = <0x00 0x43000000 0x00 0x20000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0x00 0x00 0x43000000 0x20000>; 212 213 chipid@14 { 214 compatible = "ti,am654-chipid"; 215 reg = <0x00000014 0x4>; 216 }; 217 218 phy_gmii_sel: phy@4044 { 219 compatible = "ti,am654-phy-gmii-sel"; 220 reg = <0x4044 0x8>; 221 #phy-cells = <1>; 222 }; 223 224 epwm_tbclk: clock@4140 { 225 compatible = "ti,am64-epwm-tbclk", "syscon"; 226 reg = <0x4130 0x4>; 227 #clock-cells = <1>; 228 }; 229 }; 230 231 main_uart0: serial@2800000 { 232 compatible = "ti,am64-uart", "ti,am654-uart"; 233 reg = <0x00 0x02800000 0x00 0x100>; 234 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 235 clock-frequency = <48000000>; 236 current-speed = <115200>; 237 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 238 clocks = <&k3_clks 146 0>; 239 clock-names = "fclk"; 240 }; 241 242 main_uart1: serial@2810000 { 243 compatible = "ti,am64-uart", "ti,am654-uart"; 244 reg = <0x00 0x02810000 0x00 0x100>; 245 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 246 clock-frequency = <48000000>; 247 current-speed = <115200>; 248 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 249 clocks = <&k3_clks 152 0>; 250 clock-names = "fclk"; 251 }; 252 253 main_uart2: serial@2820000 { 254 compatible = "ti,am64-uart", "ti,am654-uart"; 255 reg = <0x00 0x02820000 0x00 0x100>; 256 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 257 clock-frequency = <48000000>; 258 current-speed = <115200>; 259 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 260 clocks = <&k3_clks 153 0>; 261 clock-names = "fclk"; 262 }; 263 264 main_uart3: serial@2830000 { 265 compatible = "ti,am64-uart", "ti,am654-uart"; 266 reg = <0x00 0x02830000 0x00 0x100>; 267 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 268 clock-frequency = <48000000>; 269 current-speed = <115200>; 270 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 271 clocks = <&k3_clks 154 0>; 272 clock-names = "fclk"; 273 }; 274 275 main_uart4: serial@2840000 { 276 compatible = "ti,am64-uart", "ti,am654-uart"; 277 reg = <0x00 0x02840000 0x00 0x100>; 278 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 279 clock-frequency = <48000000>; 280 current-speed = <115200>; 281 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 282 clocks = <&k3_clks 155 0>; 283 clock-names = "fclk"; 284 }; 285 286 main_uart5: serial@2850000 { 287 compatible = "ti,am64-uart", "ti,am654-uart"; 288 reg = <0x00 0x02850000 0x00 0x100>; 289 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 290 clock-frequency = <48000000>; 291 current-speed = <115200>; 292 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 293 clocks = <&k3_clks 156 0>; 294 clock-names = "fclk"; 295 }; 296 297 main_uart6: serial@2860000 { 298 compatible = "ti,am64-uart", "ti,am654-uart"; 299 reg = <0x00 0x02860000 0x00 0x100>; 300 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 301 clock-frequency = <48000000>; 302 current-speed = <115200>; 303 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 304 clocks = <&k3_clks 158 0>; 305 clock-names = "fclk"; 306 }; 307 308 main_i2c0: i2c@20000000 { 309 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 310 reg = <0x00 0x20000000 0x00 0x100>; 311 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 315 clocks = <&k3_clks 102 2>; 316 clock-names = "fck"; 317 }; 318 319 main_i2c1: i2c@20010000 { 320 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 321 reg = <0x00 0x20010000 0x00 0x100>; 322 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 326 clocks = <&k3_clks 103 2>; 327 clock-names = "fck"; 328 }; 329 330 main_i2c2: i2c@20020000 { 331 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 332 reg = <0x00 0x20020000 0x00 0x100>; 333 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 337 clocks = <&k3_clks 104 2>; 338 clock-names = "fck"; 339 }; 340 341 main_i2c3: i2c@20030000 { 342 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 343 reg = <0x00 0x20030000 0x00 0x100>; 344 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 348 clocks = <&k3_clks 105 2>; 349 clock-names = "fck"; 350 }; 351 352 main_spi0: spi@20100000 { 353 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 354 reg = <0x00 0x20100000 0x00 0x400>; 355 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 359 clocks = <&k3_clks 141 0>; 360 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 361 dma-names = "tx0", "rx0"; 362 }; 363 364 main_spi1: spi@20110000 { 365 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 366 reg = <0x00 0x20110000 0x00 0x400>; 367 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 371 clocks = <&k3_clks 142 0>; 372 }; 373 374 main_spi2: spi@20120000 { 375 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 376 reg = <0x00 0x20120000 0x00 0x400>; 377 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 381 clocks = <&k3_clks 143 0>; 382 }; 383 384 main_spi3: spi@20130000 { 385 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 386 reg = <0x00 0x20130000 0x00 0x400>; 387 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 391 clocks = <&k3_clks 144 0>; 392 }; 393 394 main_spi4: spi@20140000 { 395 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 396 reg = <0x00 0x20140000 0x00 0x400>; 397 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 145 0>; 402 }; 403 404 main_gpio_intr: interrupt-controller@a00000 { 405 compatible = "ti,sci-intr"; 406 reg = <0x00 0x00a00000 0x00 0x800>; 407 ti,intr-trigger-type = <1>; 408 interrupt-controller; 409 interrupt-parent = <&gic500>; 410 #interrupt-cells = <1>; 411 ti,sci = <&dmsc>; 412 ti,sci-dev-id = <3>; 413 ti,interrupt-ranges = <0 32 16>; 414 }; 415 416 main_gpio0: gpio@600000 { 417 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 418 reg = <0x0 0x00600000 0x0 0x100>; 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-parent = <&main_gpio_intr>; 422 interrupts = <190>, <191>, <192>, 423 <193>, <194>, <195>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 ti,ngpio = <87>; 427 ti,davinci-gpio-unbanked = <0>; 428 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 77 0>; 430 clock-names = "gpio"; 431 }; 432 433 main_gpio1: gpio@601000 { 434 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 435 reg = <0x0 0x00601000 0x0 0x100>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 interrupt-parent = <&main_gpio_intr>; 439 interrupts = <180>, <181>, <182>, 440 <183>, <184>, <185>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 ti,ngpio = <88>; 444 ti,davinci-gpio-unbanked = <0>; 445 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 78 0>; 447 clock-names = "gpio"; 448 }; 449 450 sdhci0: mmc@fa10000 { 451 compatible = "ti,am64-sdhci-8bit"; 452 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 453 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 454 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 455 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 456 clock-names = "clk_ahb", "clk_xin"; 457 mmc-ddr-1_8v; 458 mmc-hs200-1_8v; 459 mmc-hs400-1_8v; 460 ti,trm-icp = <0x2>; 461 ti,otap-del-sel-legacy = <0x0>; 462 ti,otap-del-sel-mmc-hs = <0x0>; 463 ti,otap-del-sel-ddr52 = <0x6>; 464 ti,otap-del-sel-hs200 = <0x7>; 465 ti,otap-del-sel-hs400 = <0x4>; 466 }; 467 468 sdhci1: mmc@fa00000 { 469 compatible = "ti,am64-sdhci-4bit"; 470 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 471 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 472 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 473 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 474 clock-names = "clk_ahb", "clk_xin"; 475 ti,trm-icp = <0x2>; 476 ti,otap-del-sel-legacy = <0x0>; 477 ti,otap-del-sel-sd-hs = <0xf>; 478 ti,otap-del-sel-sdr12 = <0xf>; 479 ti,otap-del-sel-sdr25 = <0xf>; 480 ti,otap-del-sel-sdr50 = <0xc>; 481 ti,otap-del-sel-sdr104 = <0x6>; 482 ti,otap-del-sel-ddr50 = <0x9>; 483 ti,clkbuf-sel = <0x7>; 484 }; 485 486 cpsw3g: ethernet@8000000 { 487 compatible = "ti,am642-cpsw-nuss"; 488 #address-cells = <2>; 489 #size-cells = <2>; 490 reg = <0x0 0x8000000 0x0 0x200000>; 491 reg-names = "cpsw_nuss"; 492 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 493 clocks = <&k3_clks 13 0>; 494 assigned-clocks = <&k3_clks 13 1>; 495 assigned-clock-parents = <&k3_clks 13 9>; 496 clock-names = "fck"; 497 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 498 499 dmas = <&main_pktdma 0xC500 15>, 500 <&main_pktdma 0xC501 15>, 501 <&main_pktdma 0xC502 15>, 502 <&main_pktdma 0xC503 15>, 503 <&main_pktdma 0xC504 15>, 504 <&main_pktdma 0xC505 15>, 505 <&main_pktdma 0xC506 15>, 506 <&main_pktdma 0xC507 15>, 507 <&main_pktdma 0x4500 15>; 508 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 509 "tx7", "rx"; 510 511 ethernet-ports { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 cpsw_port1: port@1 { 516 reg = <1>; 517 ti,mac-only; 518 label = "port1"; 519 phys = <&phy_gmii_sel 1>; 520 mac-address = [00 00 00 00 00 00]; 521 ti,syscon-efuse = <&main_conf 0x200>; 522 }; 523 524 cpsw_port2: port@2 { 525 reg = <2>; 526 ti,mac-only; 527 label = "port2"; 528 phys = <&phy_gmii_sel 2>; 529 mac-address = [00 00 00 00 00 00]; 530 }; 531 }; 532 533 cpsw3g_mdio: mdio@f00 { 534 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 535 reg = <0x0 0xf00 0x0 0x100>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 clocks = <&k3_clks 13 0>; 539 clock-names = "fck"; 540 bus_freq = <1000000>; 541 }; 542 543 cpts@3d000 { 544 compatible = "ti,j721e-cpts"; 545 reg = <0x0 0x3d000 0x0 0x400>; 546 clocks = <&k3_clks 13 1>; 547 clock-names = "cpts"; 548 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "cpts"; 550 ti,cpts-ext-ts-inputs = <4>; 551 ti,cpts-periodic-outputs = <2>; 552 }; 553 }; 554 555 cpts@39000000 { 556 compatible = "ti,j721e-cpts"; 557 reg = <0x0 0x39000000 0x0 0x400>; 558 reg-names = "cpts"; 559 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 560 clocks = <&k3_clks 84 0>; 561 clock-names = "cpts"; 562 assigned-clocks = <&k3_clks 84 0>; 563 assigned-clock-parents = <&k3_clks 84 8>; 564 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 565 interrupt-names = "cpts"; 566 ti,cpts-periodic-outputs = <6>; 567 ti,cpts-ext-ts-inputs = <8>; 568 }; 569 570 timesync_router: pinctrl@a40000 { 571 compatible = "pinctrl-single"; 572 reg = <0x0 0xa40000 0x0 0x800>; 573 #pinctrl-cells = <1>; 574 pinctrl-single,register-width = <32>; 575 pinctrl-single,function-mask = <0x000107ff>; 576 }; 577 578 usbss0: cdns-usb@f900000{ 579 compatible = "ti,am64-usb"; 580 reg = <0x00 0xf900000 0x00 0x100>; 581 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 582 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 583 clock-names = "ref", "lpm"; 584 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 585 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 586 #address-cells = <2>; 587 #size-cells = <2>; 588 ranges; 589 usb0: usb@f400000{ 590 compatible = "cdns,usb3"; 591 reg = <0x00 0xf400000 0x00 0x10000>, 592 <0x00 0xf410000 0x00 0x10000>, 593 <0x00 0xf420000 0x00 0x10000>; 594 reg-names = "otg", 595 "xhci", 596 "dev"; 597 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 598 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 599 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 600 interrupt-names = "host", 601 "peripheral", 602 "otg"; 603 maximum-speed = "super-speed"; 604 dr_mode = "otg"; 605 }; 606 }; 607 608 tscadc0: tscadc@28001000 { 609 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 610 reg = <0x00 0x28001000 0x00 0x1000>; 611 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 612 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 613 clocks = <&k3_clks 0 0>; 614 assigned-clocks = <&k3_clks 0 0>; 615 assigned-clock-parents = <&k3_clks 0 3>; 616 assigned-clock-rates = <60000000>; 617 clock-names = "adc_tsc_fck"; 618 619 adc { 620 #io-channel-cells = <1>; 621 compatible = "ti,am654-adc", "ti,am3359-adc"; 622 }; 623 }; 624 625 fss: bus@fc00000 { 626 compatible = "simple-bus"; 627 reg = <0x00 0x0fc00000 0x00 0x70000>; 628 #address-cells = <2>; 629 #size-cells = <2>; 630 ranges; 631 632 ospi0: spi@fc40000 { 633 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 634 reg = <0x00 0x0fc40000 0x00 0x100>, 635 <0x05 0x00000000 0x01 0x00000000>; 636 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 637 cdns,fifo-depth = <256>; 638 cdns,fifo-width = <4>; 639 cdns,trigger-address = <0x0>; 640 #address-cells = <0x1>; 641 #size-cells = <0x0>; 642 clocks = <&k3_clks 75 6>; 643 assigned-clocks = <&k3_clks 75 6>; 644 assigned-clock-parents = <&k3_clks 75 7>; 645 assigned-clock-rates = <166666666>; 646 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 647 }; 648 }; 649 650 hwspinlock: spinlock@2a000000 { 651 compatible = "ti,am64-hwspinlock"; 652 reg = <0x00 0x2a000000 0x00 0x1000>; 653 #hwlock-cells = <1>; 654 }; 655 656 mailbox0_cluster2: mailbox@29020000 { 657 compatible = "ti,am64-mailbox"; 658 reg = <0x00 0x29020000 0x00 0x200>; 659 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 661 #mbox-cells = <1>; 662 ti,mbox-num-users = <4>; 663 ti,mbox-num-fifos = <16>; 664 }; 665 666 mailbox0_cluster3: mailbox@29030000 { 667 compatible = "ti,am64-mailbox"; 668 reg = <0x00 0x29030000 0x00 0x200>; 669 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 671 #mbox-cells = <1>; 672 ti,mbox-num-users = <4>; 673 ti,mbox-num-fifos = <16>; 674 }; 675 676 mailbox0_cluster4: mailbox@29040000 { 677 compatible = "ti,am64-mailbox"; 678 reg = <0x00 0x29040000 0x00 0x200>; 679 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 681 #mbox-cells = <1>; 682 ti,mbox-num-users = <4>; 683 ti,mbox-num-fifos = <16>; 684 }; 685 686 mailbox0_cluster5: mailbox@29050000 { 687 compatible = "ti,am64-mailbox"; 688 reg = <0x00 0x29050000 0x00 0x200>; 689 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 691 #mbox-cells = <1>; 692 ti,mbox-num-users = <4>; 693 ti,mbox-num-fifos = <16>; 694 }; 695 696 mailbox0_cluster6: mailbox@29060000 { 697 compatible = "ti,am64-mailbox"; 698 reg = <0x00 0x29060000 0x00 0x200>; 699 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 700 #mbox-cells = <1>; 701 ti,mbox-num-users = <4>; 702 ti,mbox-num-fifos = <16>; 703 }; 704 705 mailbox0_cluster7: mailbox@29070000 { 706 compatible = "ti,am64-mailbox"; 707 reg = <0x00 0x29070000 0x00 0x200>; 708 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 709 #mbox-cells = <1>; 710 ti,mbox-num-users = <4>; 711 ti,mbox-num-fifos = <16>; 712 }; 713 714 main_r5fss0: r5fss@78000000 { 715 compatible = "ti,am64-r5fss"; 716 ti,cluster-mode = <0>; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges = <0x78000000 0x00 0x78000000 0x10000>, 720 <0x78100000 0x00 0x78100000 0x10000>, 721 <0x78200000 0x00 0x78200000 0x08000>, 722 <0x78300000 0x00 0x78300000 0x08000>; 723 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 724 725 main_r5fss0_core0: r5f@78000000 { 726 compatible = "ti,am64-r5f"; 727 reg = <0x78000000 0x00010000>, 728 <0x78100000 0x00010000>; 729 reg-names = "atcm", "btcm"; 730 ti,sci = <&dmsc>; 731 ti,sci-dev-id = <121>; 732 ti,sci-proc-ids = <0x01 0xff>; 733 resets = <&k3_reset 121 1>; 734 firmware-name = "am64-main-r5f0_0-fw"; 735 ti,atcm-enable = <1>; 736 ti,btcm-enable = <1>; 737 ti,loczrama = <1>; 738 }; 739 740 main_r5fss0_core1: r5f@78200000 { 741 compatible = "ti,am64-r5f"; 742 reg = <0x78200000 0x00008000>, 743 <0x78300000 0x00008000>; 744 reg-names = "atcm", "btcm"; 745 ti,sci = <&dmsc>; 746 ti,sci-dev-id = <122>; 747 ti,sci-proc-ids = <0x02 0xff>; 748 resets = <&k3_reset 122 1>; 749 firmware-name = "am64-main-r5f0_1-fw"; 750 ti,atcm-enable = <1>; 751 ti,btcm-enable = <1>; 752 ti,loczrama = <1>; 753 }; 754 }; 755 756 main_r5fss1: r5fss@78400000 { 757 compatible = "ti,am64-r5fss"; 758 ti,cluster-mode = <0>; 759 #address-cells = <1>; 760 #size-cells = <1>; 761 ranges = <0x78400000 0x00 0x78400000 0x10000>, 762 <0x78500000 0x00 0x78500000 0x10000>, 763 <0x78600000 0x00 0x78600000 0x08000>, 764 <0x78700000 0x00 0x78700000 0x08000>; 765 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 766 767 main_r5fss1_core0: r5f@78400000 { 768 compatible = "ti,am64-r5f"; 769 reg = <0x78400000 0x00010000>, 770 <0x78500000 0x00010000>; 771 reg-names = "atcm", "btcm"; 772 ti,sci = <&dmsc>; 773 ti,sci-dev-id = <123>; 774 ti,sci-proc-ids = <0x06 0xff>; 775 resets = <&k3_reset 123 1>; 776 firmware-name = "am64-main-r5f1_0-fw"; 777 ti,atcm-enable = <1>; 778 ti,btcm-enable = <1>; 779 ti,loczrama = <1>; 780 }; 781 782 main_r5fss1_core1: r5f@78600000 { 783 compatible = "ti,am64-r5f"; 784 reg = <0x78600000 0x00008000>, 785 <0x78700000 0x00008000>; 786 reg-names = "atcm", "btcm"; 787 ti,sci = <&dmsc>; 788 ti,sci-dev-id = <124>; 789 ti,sci-proc-ids = <0x07 0xff>; 790 resets = <&k3_reset 124 1>; 791 firmware-name = "am64-main-r5f1_1-fw"; 792 ti,atcm-enable = <1>; 793 ti,btcm-enable = <1>; 794 ti,loczrama = <1>; 795 }; 796 }; 797 798 serdes_wiz0: wiz@f000000 { 799 compatible = "ti,am64-wiz-10g"; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 803 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 804 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 805 num-lanes = <1>; 806 #reset-cells = <1>; 807 #clock-cells = <1>; 808 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 809 810 assigned-clocks = <&k3_clks 162 1>; 811 assigned-clock-parents = <&k3_clks 162 5>; 812 813 serdes0: serdes@f000000 { 814 compatible = "ti,j721e-serdes-10g"; 815 reg = <0x0f000000 0x00010000>; 816 reg-names = "torrent_phy"; 817 resets = <&serdes_wiz0 0>; 818 reset-names = "torrent_reset"; 819 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 820 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 821 clock-names = "refclk", "phy_en_refclk"; 822 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 823 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 824 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 825 assigned-clock-parents = <&k3_clks 162 1>, 826 <&k3_clks 162 1>, 827 <&k3_clks 162 1>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 #clock-cells = <1>; 831 }; 832 }; 833 834 pcie0_rc: pcie@f102000 { 835 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 836 reg = <0x00 0x0f102000 0x00 0x1000>, 837 <0x00 0x0f100000 0x00 0x400>, 838 <0x00 0x0d000000 0x00 0x00800000>, 839 <0x00 0x68000000 0x00 0x00001000>; 840 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 841 interrupt-names = "link_state"; 842 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 843 device_type = "pci"; 844 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 845 max-link-speed = <2>; 846 num-lanes = <1>; 847 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 848 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 849 clock-names = "fck", "pcie_refclk"; 850 #address-cells = <3>; 851 #size-cells = <2>; 852 bus-range = <0x0 0xff>; 853 cdns,no-bar-match-nbits = <64>; 854 vendor-id = <0x104c>; 855 device-id = <0xb010>; 856 msi-map = <0x0 &gic_its 0x0 0x10000>; 857 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 858 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 859 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 860 }; 861 862 pcie0_ep: pcie-ep@f102000 { 863 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 864 reg = <0x00 0x0f102000 0x00 0x1000>, 865 <0x00 0x0f100000 0x00 0x400>, 866 <0x00 0x0d000000 0x00 0x00800000>, 867 <0x00 0x68000000 0x00 0x08000000>; 868 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 869 interrupt-names = "link_state"; 870 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 871 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 872 max-link-speed = <2>; 873 num-lanes = <1>; 874 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 875 clocks = <&k3_clks 114 0>; 876 clock-names = "fck"; 877 max-functions = /bits/ 8 <1>; 878 }; 879 880 epwm0: pwm@23000000 { 881 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 882 #pwm-cells = <3>; 883 reg = <0x0 0x23000000 0x0 0x100>; 884 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 885 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 886 clock-names = "tbclk", "fck"; 887 }; 888 889 epwm1: pwm@23010000 { 890 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 891 #pwm-cells = <3>; 892 reg = <0x0 0x23010000 0x0 0x100>; 893 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 894 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 895 clock-names = "tbclk", "fck"; 896 }; 897 898 epwm2: pwm@23020000 { 899 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 900 #pwm-cells = <3>; 901 reg = <0x0 0x23020000 0x0 0x100>; 902 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 903 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 904 clock-names = "tbclk", "fck"; 905 }; 906 907 epwm3: pwm@23030000 { 908 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 909 #pwm-cells = <3>; 910 reg = <0x0 0x23030000 0x0 0x100>; 911 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 912 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 913 clock-names = "tbclk", "fck"; 914 }; 915 916 epwm4: pwm@23040000 { 917 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 918 #pwm-cells = <3>; 919 reg = <0x0 0x23040000 0x0 0x100>; 920 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 921 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 922 clock-names = "tbclk", "fck"; 923 }; 924 925 epwm5: pwm@23050000 { 926 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 927 #pwm-cells = <3>; 928 reg = <0x0 0x23050000 0x0 0x100>; 929 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 931 clock-names = "tbclk", "fck"; 932 }; 933 934 epwm6: pwm@23060000 { 935 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 936 #pwm-cells = <3>; 937 reg = <0x0 0x23060000 0x0 0x100>; 938 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 939 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 940 clock-names = "tbclk", "fck"; 941 }; 942 943 epwm7: pwm@23070000 { 944 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 945 #pwm-cells = <3>; 946 reg = <0x0 0x23070000 0x0 0x100>; 947 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 948 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 949 clock-names = "tbclk", "fck"; 950 }; 951 952 epwm8: pwm@23080000 { 953 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 954 #pwm-cells = <3>; 955 reg = <0x0 0x23080000 0x0 0x100>; 956 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 957 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 958 clock-names = "tbclk", "fck"; 959 }; 960 961 ecap0: pwm@23100000 { 962 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 963 #pwm-cells = <3>; 964 reg = <0x0 0x23100000 0x0 0x60>; 965 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 966 clocks = <&k3_clks 51 0>; 967 clock-names = "fck"; 968 }; 969 970 ecap1: pwm@23110000 { 971 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 972 #pwm-cells = <3>; 973 reg = <0x0 0x23110000 0x0 0x60>; 974 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 975 clocks = <&k3_clks 52 0>; 976 clock-names = "fck"; 977 }; 978 979 ecap2: pwm@23120000 { 980 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 981 #pwm-cells = <3>; 982 reg = <0x0 0x23120000 0x0 0x60>; 983 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 984 clocks = <&k3_clks 53 0>; 985 clock-names = "fck"; 986 }; 987 988 main_rti0: watchdog@e000000 { 989 compatible = "ti,j7-rti-wdt"; 990 reg = <0x00 0xe000000 0x00 0x100>; 991 clocks = <&k3_clks 125 0>; 992 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 993 assigned-clocks = <&k3_clks 125 0>; 994 assigned-clock-parents = <&k3_clks 125 2>; 995 }; 996 997 main_rti1: watchdog@e010000 { 998 compatible = "ti,j7-rti-wdt"; 999 reg = <0x00 0xe010000 0x00 0x100>; 1000 clocks = <&k3_clks 126 0>; 1001 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1002 assigned-clocks = <&k3_clks 126 0>; 1003 assigned-clock-parents = <&k3_clks 126 2>; 1004 }; 1005 1006 icssg0: icssg@30000000 { 1007 compatible = "ti,am642-icssg"; 1008 reg = <0x00 0x30000000 0x00 0x80000>; 1009 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1010 #address-cells = <1>; 1011 #size-cells = <1>; 1012 ranges = <0x0 0x00 0x30000000 0x80000>; 1013 1014 icssg0_mem: memories@0 { 1015 reg = <0x0 0x2000>, 1016 <0x2000 0x2000>, 1017 <0x10000 0x10000>; 1018 reg-names = "dram0", "dram1", "shrdram2"; 1019 }; 1020 1021 icssg0_cfg: cfg@26000 { 1022 compatible = "ti,pruss-cfg", "syscon"; 1023 reg = <0x26000 0x200>; 1024 #address-cells = <1>; 1025 #size-cells = <1>; 1026 ranges = <0x0 0x26000 0x2000>; 1027 1028 clocks { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 icssg0_coreclk_mux: coreclk-mux@3c { 1033 reg = <0x3c>; 1034 #clock-cells = <0>; 1035 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1036 <&k3_clks 81 20>; /* icssg0_iclk */ 1037 assigned-clocks = <&icssg0_coreclk_mux>; 1038 assigned-clock-parents = <&k3_clks 81 20>; 1039 }; 1040 1041 icssg0_iepclk_mux: iepclk-mux@30 { 1042 reg = <0x30>; 1043 #clock-cells = <0>; 1044 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1045 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1046 assigned-clocks = <&icssg0_iepclk_mux>; 1047 assigned-clock-parents = <&icssg0_coreclk_mux>; 1048 }; 1049 }; 1050 }; 1051 1052 icssg0_mii_rt: mii-rt@32000 { 1053 compatible = "ti,pruss-mii", "syscon"; 1054 reg = <0x32000 0x100>; 1055 }; 1056 1057 icssg0_mii_g_rt: mii-g-rt@33000 { 1058 compatible = "ti,pruss-mii-g", "syscon"; 1059 reg = <0x33000 0x1000>; 1060 }; 1061 1062 icssg0_intc: interrupt-controller@20000 { 1063 compatible = "ti,icssg-intc"; 1064 reg = <0x20000 0x2000>; 1065 interrupt-controller; 1066 #interrupt-cells = <3>; 1067 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1075 interrupt-names = "host_intr0", "host_intr1", 1076 "host_intr2", "host_intr3", 1077 "host_intr4", "host_intr5", 1078 "host_intr6", "host_intr7"; 1079 }; 1080 1081 pru0_0: pru@34000 { 1082 compatible = "ti,am642-pru"; 1083 reg = <0x34000 0x3000>, 1084 <0x22000 0x100>, 1085 <0x22400 0x100>; 1086 reg-names = "iram", "control", "debug"; 1087 firmware-name = "am64x-pru0_0-fw"; 1088 }; 1089 1090 rtu0_0: rtu@4000 { 1091 compatible = "ti,am642-rtu"; 1092 reg = <0x4000 0x2000>, 1093 <0x23000 0x100>, 1094 <0x23400 0x100>; 1095 reg-names = "iram", "control", "debug"; 1096 firmware-name = "am64x-rtu0_0-fw"; 1097 }; 1098 1099 tx_pru0_0: txpru@a000 { 1100 compatible = "ti,am642-tx-pru"; 1101 reg = <0xa000 0x1800>, 1102 <0x25000 0x100>, 1103 <0x25400 0x100>; 1104 reg-names = "iram", "control", "debug"; 1105 firmware-name = "am64x-txpru0_0-fw"; 1106 }; 1107 1108 pru0_1: pru@38000 { 1109 compatible = "ti,am642-pru"; 1110 reg = <0x38000 0x3000>, 1111 <0x24000 0x100>, 1112 <0x24400 0x100>; 1113 reg-names = "iram", "control", "debug"; 1114 firmware-name = "am64x-pru0_1-fw"; 1115 }; 1116 1117 rtu0_1: rtu@6000 { 1118 compatible = "ti,am642-rtu"; 1119 reg = <0x6000 0x2000>, 1120 <0x23800 0x100>, 1121 <0x23c00 0x100>; 1122 reg-names = "iram", "control", "debug"; 1123 firmware-name = "am64x-rtu0_1-fw"; 1124 }; 1125 1126 tx_pru0_1: txpru@c000 { 1127 compatible = "ti,am642-tx-pru"; 1128 reg = <0xc000 0x1800>, 1129 <0x25800 0x100>, 1130 <0x25c00 0x100>; 1131 reg-names = "iram", "control", "debug"; 1132 firmware-name = "am64x-txpru0_1-fw"; 1133 }; 1134 1135 icssg0_mdio: mdio@32400 { 1136 compatible = "ti,davinci_mdio"; 1137 reg = <0x32400 0x100>; 1138 clocks = <&k3_clks 62 3>; 1139 clock-names = "fck"; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 bus_freq = <1000000>; 1143 }; 1144 }; 1145 1146 icssg1: icssg@30080000 { 1147 compatible = "ti,am642-icssg"; 1148 reg = <0x00 0x30080000 0x00 0x80000>; 1149 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1150 #address-cells = <1>; 1151 #size-cells = <1>; 1152 ranges = <0x0 0x00 0x30080000 0x80000>; 1153 1154 icssg1_mem: memories@0 { 1155 reg = <0x0 0x2000>, 1156 <0x2000 0x2000>, 1157 <0x10000 0x10000>; 1158 reg-names = "dram0", "dram1", "shrdram2"; 1159 }; 1160 1161 icssg1_cfg: cfg@26000 { 1162 compatible = "ti,pruss-cfg", "syscon"; 1163 reg = <0x26000 0x200>; 1164 #address-cells = <1>; 1165 #size-cells = <1>; 1166 ranges = <0x0 0x26000 0x2000>; 1167 1168 clocks { 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 icssg1_coreclk_mux: coreclk-mux@3c { 1173 reg = <0x3c>; 1174 #clock-cells = <0>; 1175 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1176 <&k3_clks 82 20>; /* icssg1_iclk */ 1177 assigned-clocks = <&icssg1_coreclk_mux>; 1178 assigned-clock-parents = <&k3_clks 82 20>; 1179 }; 1180 1181 icssg1_iepclk_mux: iepclk-mux@30 { 1182 reg = <0x30>; 1183 #clock-cells = <0>; 1184 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1185 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1186 assigned-clocks = <&icssg1_iepclk_mux>; 1187 assigned-clock-parents = <&icssg1_coreclk_mux>; 1188 }; 1189 }; 1190 }; 1191 1192 icssg1_mii_rt: mii-rt@32000 { 1193 compatible = "ti,pruss-mii", "syscon"; 1194 reg = <0x32000 0x100>; 1195 }; 1196 1197 icssg1_mii_g_rt: mii-g-rt@33000 { 1198 compatible = "ti,pruss-mii-g", "syscon"; 1199 reg = <0x33000 0x1000>; 1200 }; 1201 1202 icssg1_intc: interrupt-controller@20000 { 1203 compatible = "ti,icssg-intc"; 1204 reg = <0x20000 0x2000>; 1205 interrupt-controller; 1206 #interrupt-cells = <3>; 1207 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1215 interrupt-names = "host_intr0", "host_intr1", 1216 "host_intr2", "host_intr3", 1217 "host_intr4", "host_intr5", 1218 "host_intr6", "host_intr7"; 1219 }; 1220 1221 pru1_0: pru@34000 { 1222 compatible = "ti,am642-pru"; 1223 reg = <0x34000 0x4000>, 1224 <0x22000 0x100>, 1225 <0x22400 0x100>; 1226 reg-names = "iram", "control", "debug"; 1227 firmware-name = "am64x-pru1_0-fw"; 1228 }; 1229 1230 rtu1_0: rtu@4000 { 1231 compatible = "ti,am642-rtu"; 1232 reg = <0x4000 0x2000>, 1233 <0x23000 0x100>, 1234 <0x23400 0x100>; 1235 reg-names = "iram", "control", "debug"; 1236 firmware-name = "am64x-rtu1_0-fw"; 1237 }; 1238 1239 tx_pru1_0: txpru@a000 { 1240 compatible = "ti,am642-tx-pru"; 1241 reg = <0xa000 0x1800>, 1242 <0x25000 0x100>, 1243 <0x25400 0x100>; 1244 reg-names = "iram", "control", "debug"; 1245 firmware-name = "am64x-txpru1_0-fw"; 1246 }; 1247 1248 pru1_1: pru@38000 { 1249 compatible = "ti,am642-pru"; 1250 reg = <0x38000 0x4000>, 1251 <0x24000 0x100>, 1252 <0x24400 0x100>; 1253 reg-names = "iram", "control", "debug"; 1254 firmware-name = "am64x-pru1_1-fw"; 1255 }; 1256 1257 rtu1_1: rtu@6000 { 1258 compatible = "ti,am642-rtu"; 1259 reg = <0x6000 0x2000>, 1260 <0x23800 0x100>, 1261 <0x23c00 0x100>; 1262 reg-names = "iram", "control", "debug"; 1263 firmware-name = "am64x-rtu1_1-fw"; 1264 }; 1265 1266 tx_pru1_1: txpru@c000 { 1267 compatible = "ti,am642-tx-pru"; 1268 reg = <0xc000 0x1800>, 1269 <0x25800 0x100>, 1270 <0x25c00 0x100>; 1271 reg-names = "iram", "control", "debug"; 1272 firmware-name = "am64x-txpru1_1-fw"; 1273 }; 1274 1275 icssg1_mdio: mdio@32400 { 1276 compatible = "ti,davinci_mdio"; 1277 reg = <0x32400 0x100>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 clocks = <&k3_clks 82 0>; 1281 clock-names = "fck"; 1282 bus_freq = <1000000>; 1283 }; 1284 }; 1285 1286 main_mcan0: can@20701000 { 1287 compatible = "bosch,m_can"; 1288 reg = <0x00 0x20701000 0x00 0x200>, 1289 <0x00 0x20708000 0x00 0x8000>; 1290 reg-names = "m_can", "message_ram"; 1291 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1292 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1293 clock-names = "hclk", "cclk"; 1294 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1296 interrupt-names = "int0", "int1"; 1297 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1298 }; 1299 1300 main_mcan1: can@20711000 { 1301 compatible = "bosch,m_can"; 1302 reg = <0x00 0x20711000 0x00 0x200>, 1303 <0x00 0x20718000 0x00 0x8000>; 1304 reg-names = "m_can", "message_ram"; 1305 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1306 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1307 clock-names = "hclk", "cclk"; 1308 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-names = "int0", "int1"; 1311 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1312 }; 1313}; 1314