1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x0 0x43000000 0x0 0x20000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 47 serdes_ln_ctrl: mux-controller { 48 compatible = "mmio-mux"; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 51 }; 52 }; 53 54 gic500: interrupt-controller@1800000 { 55 compatible = "arm,gic-v3"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 62 <0x00 0x01840000 0x00 0xC0000>; /* GICR */ 63 /* 64 * vcpumntirq: 65 * virtual CPU interface maintenance interrupt 66 */ 67 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 68 69 gic_its: msi-controller@1820000 { 70 compatible = "arm,gic-v3-its"; 71 reg = <0x00 0x01820000 0x00 0x10000>; 72 socionext,synquacer-pre-its = <0x1000000 0x400000>; 73 msi-controller; 74 #msi-cells = <1>; 75 }; 76 }; 77 78 dmss: bus@48000000 { 79 compatible = "simple-mfd"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 dma-ranges; 83 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 84 85 ti,sci-dev-id = <25>; 86 87 secure_proxy_main: mailbox@4d000000 { 88 compatible = "ti,am654-secure-proxy"; 89 #mbox-cells = <1>; 90 reg-names = "target_data", "rt", "scfg"; 91 reg = <0x00 0x4d000000 0x00 0x80000>, 92 <0x00 0x4a600000 0x00 0x80000>, 93 <0x00 0x4a400000 0x00 0x80000>; 94 interrupt-names = "rx_012"; 95 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 96 }; 97 98 inta_main_dmss: interrupt-controller@48000000 { 99 compatible = "ti,sci-inta"; 100 reg = <0x00 0x48000000 0x00 0x100000>; 101 #interrupt-cells = <0>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 msi-controller; 105 ti,sci = <&dmsc>; 106 ti,sci-dev-id = <28>; 107 ti,interrupt-ranges = <4 68 36>; 108 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 109 }; 110 111 main_bcdma: dma-controller@485c0100 { 112 compatible = "ti,am64-dmss-bcdma"; 113 reg = <0x00 0x485c0100 0x00 0x100>, 114 <0x00 0x4c000000 0x00 0x20000>, 115 <0x00 0x4a820000 0x00 0x20000>, 116 <0x00 0x4aa40000 0x00 0x20000>, 117 <0x00 0x4bc00000 0x00 0x100000>; 118 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 119 msi-parent = <&inta_main_dmss>; 120 #dma-cells = <3>; 121 122 ti,sci = <&dmsc>; 123 ti,sci-dev-id = <26>; 124 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 125 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 126 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 127 }; 128 129 main_pktdma: dma-controller@485c0000 { 130 compatible = "ti,am64-dmss-pktdma"; 131 reg = <0x00 0x485c0000 0x00 0x100>, 132 <0x00 0x4a800000 0x00 0x20000>, 133 <0x00 0x4aa00000 0x00 0x40000>, 134 <0x00 0x4b800000 0x00 0x400000>; 135 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 136 msi-parent = <&inta_main_dmss>; 137 #dma-cells = <2>; 138 139 ti,sci = <&dmsc>; 140 ti,sci-dev-id = <30>; 141 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 142 <0x24>, /* CPSW_TX_CHAN */ 143 <0x25>, /* SAUL_TX_0_CHAN */ 144 <0x26>, /* SAUL_TX_1_CHAN */ 145 <0x27>, /* ICSSG_0_TX_CHAN */ 146 <0x28>; /* ICSSG_1_TX_CHAN */ 147 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 148 <0x11>, /* RING_CPSW_TX_CHAN */ 149 <0x12>, /* RING_SAUL_TX_0_CHAN */ 150 <0x13>, /* RING_SAUL_TX_1_CHAN */ 151 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 152 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 153 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 154 <0x2b>, /* CPSW_RX_CHAN */ 155 <0x2d>, /* SAUL_RX_0_CHAN */ 156 <0x2f>, /* SAUL_RX_1_CHAN */ 157 <0x31>, /* SAUL_RX_2_CHAN */ 158 <0x33>, /* SAUL_RX_3_CHAN */ 159 <0x35>, /* ICSSG_0_RX_CHAN */ 160 <0x37>; /* ICSSG_1_RX_CHAN */ 161 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 162 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 163 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 164 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 165 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 166 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 167 }; 168 }; 169 170 dmsc: system-controller@44043000 { 171 compatible = "ti,k2g-sci"; 172 ti,host-id = <12>; 173 mbox-names = "rx", "tx"; 174 mboxes= <&secure_proxy_main 12>, 175 <&secure_proxy_main 13>; 176 reg-names = "debug_messages"; 177 reg = <0x00 0x44043000 0x00 0xfe0>; 178 179 k3_pds: power-controller { 180 compatible = "ti,sci-pm-domain"; 181 #power-domain-cells = <2>; 182 }; 183 184 k3_clks: clock-controller { 185 compatible = "ti,k2g-sci-clk"; 186 #clock-cells = <2>; 187 }; 188 189 k3_reset: reset-controller { 190 compatible = "ti,sci-reset"; 191 #reset-cells = <2>; 192 }; 193 }; 194 195 main_pmx0: pinctrl@f4000 { 196 compatible = "pinctrl-single"; 197 reg = <0x00 0xf4000 0x00 0x2d0>; 198 #pinctrl-cells = <1>; 199 pinctrl-single,register-width = <32>; 200 pinctrl-single,function-mask = <0xffffffff>; 201 }; 202 203 main_conf: syscon@43000000 { 204 compatible = "syscon", "simple-mfd"; 205 reg = <0x00 0x43000000 0x00 0x20000>; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges = <0x00 0x00 0x43000000 0x20000>; 209 210 chipid@14 { 211 compatible = "ti,am654-chipid"; 212 reg = <0x00000014 0x4>; 213 }; 214 215 phy_gmii_sel: phy@4044 { 216 compatible = "ti,am654-phy-gmii-sel"; 217 reg = <0x4044 0x8>; 218 #phy-cells = <1>; 219 }; 220 }; 221 222 main_uart0: serial@2800000 { 223 compatible = "ti,am64-uart", "ti,am654-uart"; 224 reg = <0x00 0x02800000 0x00 0x100>; 225 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 226 clock-frequency = <48000000>; 227 current-speed = <115200>; 228 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 229 clocks = <&k3_clks 146 0>; 230 clock-names = "fclk"; 231 }; 232 233 main_uart1: serial@2810000 { 234 compatible = "ti,am64-uart", "ti,am654-uart"; 235 reg = <0x00 0x02810000 0x00 0x100>; 236 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 237 clock-frequency = <48000000>; 238 current-speed = <115200>; 239 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 240 clocks = <&k3_clks 152 0>; 241 clock-names = "fclk"; 242 }; 243 244 main_uart2: serial@2820000 { 245 compatible = "ti,am64-uart", "ti,am654-uart"; 246 reg = <0x00 0x02820000 0x00 0x100>; 247 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 248 clock-frequency = <48000000>; 249 current-speed = <115200>; 250 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 251 clocks = <&k3_clks 153 0>; 252 clock-names = "fclk"; 253 }; 254 255 main_uart3: serial@2830000 { 256 compatible = "ti,am64-uart", "ti,am654-uart"; 257 reg = <0x00 0x02830000 0x00 0x100>; 258 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 259 clock-frequency = <48000000>; 260 current-speed = <115200>; 261 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 262 clocks = <&k3_clks 154 0>; 263 clock-names = "fclk"; 264 }; 265 266 main_uart4: serial@2840000 { 267 compatible = "ti,am64-uart", "ti,am654-uart"; 268 reg = <0x00 0x02840000 0x00 0x100>; 269 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 270 clock-frequency = <48000000>; 271 current-speed = <115200>; 272 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 273 clocks = <&k3_clks 155 0>; 274 clock-names = "fclk"; 275 }; 276 277 main_uart5: serial@2850000 { 278 compatible = "ti,am64-uart", "ti,am654-uart"; 279 reg = <0x00 0x02850000 0x00 0x100>; 280 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 281 clock-frequency = <48000000>; 282 current-speed = <115200>; 283 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 284 clocks = <&k3_clks 156 0>; 285 clock-names = "fclk"; 286 }; 287 288 main_uart6: serial@2860000 { 289 compatible = "ti,am64-uart", "ti,am654-uart"; 290 reg = <0x00 0x02860000 0x00 0x100>; 291 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 292 clock-frequency = <48000000>; 293 current-speed = <115200>; 294 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 295 clocks = <&k3_clks 158 0>; 296 clock-names = "fclk"; 297 }; 298 299 main_i2c0: i2c@20000000 { 300 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 301 reg = <0x00 0x20000000 0x00 0x100>; 302 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 306 clocks = <&k3_clks 102 2>; 307 clock-names = "fck"; 308 }; 309 310 main_i2c1: i2c@20010000 { 311 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 312 reg = <0x00 0x20010000 0x00 0x100>; 313 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 317 clocks = <&k3_clks 103 2>; 318 clock-names = "fck"; 319 }; 320 321 main_i2c2: i2c@20020000 { 322 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 323 reg = <0x00 0x20020000 0x00 0x100>; 324 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 328 clocks = <&k3_clks 104 2>; 329 clock-names = "fck"; 330 }; 331 332 main_i2c3: i2c@20030000 { 333 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 334 reg = <0x00 0x20030000 0x00 0x100>; 335 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 339 clocks = <&k3_clks 105 2>; 340 clock-names = "fck"; 341 }; 342 343 main_spi0: spi@20100000 { 344 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 345 reg = <0x00 0x20100000 0x00 0x400>; 346 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 350 clocks = <&k3_clks 141 0>; 351 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 352 dma-names = "tx0", "rx0"; 353 }; 354 355 main_spi1: spi@20110000 { 356 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 357 reg = <0x00 0x20110000 0x00 0x400>; 358 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 362 clocks = <&k3_clks 142 0>; 363 }; 364 365 main_spi2: spi@20120000 { 366 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 367 reg = <0x00 0x20120000 0x00 0x400>; 368 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 372 clocks = <&k3_clks 143 0>; 373 }; 374 375 main_spi3: spi@20130000 { 376 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 377 reg = <0x00 0x20130000 0x00 0x400>; 378 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 382 clocks = <&k3_clks 144 0>; 383 }; 384 385 main_spi4: spi@20140000 { 386 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 387 reg = <0x00 0x20140000 0x00 0x400>; 388 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 392 clocks = <&k3_clks 145 0>; 393 }; 394 395 main_gpio_intr: interrupt-controller@a00000 { 396 compatible = "ti,sci-intr"; 397 reg = <0x00 0x00a00000 0x00 0x800>; 398 ti,intr-trigger-type = <1>; 399 interrupt-controller; 400 interrupt-parent = <&gic500>; 401 #interrupt-cells = <1>; 402 ti,sci = <&dmsc>; 403 ti,sci-dev-id = <3>; 404 ti,interrupt-ranges = <0 32 16>; 405 }; 406 407 main_gpio0: gpio@600000 { 408 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 409 reg = <0x0 0x00600000 0x0 0x100>; 410 gpio-controller; 411 #gpio-cells = <2>; 412 interrupt-parent = <&main_gpio_intr>; 413 interrupts = <190>, <191>, <192>, 414 <193>, <194>, <195>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 ti,ngpio = <87>; 418 ti,davinci-gpio-unbanked = <0>; 419 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 77 0>; 421 clock-names = "gpio"; 422 }; 423 424 main_gpio1: gpio@601000 { 425 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 426 reg = <0x0 0x00601000 0x0 0x100>; 427 gpio-controller; 428 #gpio-cells = <2>; 429 interrupt-parent = <&main_gpio_intr>; 430 interrupts = <180>, <181>, <182>, 431 <183>, <184>, <185>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 ti,ngpio = <88>; 435 ti,davinci-gpio-unbanked = <0>; 436 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 437 clocks = <&k3_clks 78 0>; 438 clock-names = "gpio"; 439 }; 440 441 sdhci0: mmc@fa10000 { 442 compatible = "ti,am64-sdhci-8bit"; 443 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 444 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 445 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 447 clock-names = "clk_ahb", "clk_xin"; 448 mmc-ddr-1_8v; 449 mmc-hs200-1_8v; 450 mmc-hs400-1_8v; 451 ti,trm-icp = <0x2>; 452 ti,otap-del-sel-legacy = <0x0>; 453 ti,otap-del-sel-mmc-hs = <0x0>; 454 ti,otap-del-sel-ddr52 = <0x6>; 455 ti,otap-del-sel-hs200 = <0x7>; 456 ti,otap-del-sel-hs400 = <0x4>; 457 }; 458 459 sdhci1: mmc@fa00000 { 460 compatible = "ti,am64-sdhci-4bit"; 461 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 462 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 463 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 464 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 465 clock-names = "clk_ahb", "clk_xin"; 466 ti,trm-icp = <0x2>; 467 ti,otap-del-sel-legacy = <0x0>; 468 ti,otap-del-sel-sd-hs = <0xf>; 469 ti,otap-del-sel-sdr12 = <0xf>; 470 ti,otap-del-sel-sdr25 = <0xf>; 471 ti,otap-del-sel-sdr50 = <0xc>; 472 ti,otap-del-sel-sdr104 = <0x6>; 473 ti,otap-del-sel-ddr50 = <0x9>; 474 ti,clkbuf-sel = <0x7>; 475 }; 476 477 cpsw3g: ethernet@8000000 { 478 compatible = "ti,am642-cpsw-nuss"; 479 #address-cells = <2>; 480 #size-cells = <2>; 481 reg = <0x0 0x8000000 0x0 0x200000>; 482 reg-names = "cpsw_nuss"; 483 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 484 clocks = <&k3_clks 13 0>; 485 assigned-clocks = <&k3_clks 13 1>; 486 assigned-clock-parents = <&k3_clks 13 9>; 487 clock-names = "fck"; 488 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 489 490 dmas = <&main_pktdma 0xC500 15>, 491 <&main_pktdma 0xC501 15>, 492 <&main_pktdma 0xC502 15>, 493 <&main_pktdma 0xC503 15>, 494 <&main_pktdma 0xC504 15>, 495 <&main_pktdma 0xC505 15>, 496 <&main_pktdma 0xC506 15>, 497 <&main_pktdma 0xC507 15>, 498 <&main_pktdma 0x4500 15>; 499 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 500 "tx7", "rx"; 501 502 ethernet-ports { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 cpsw_port1: port@1 { 507 reg = <1>; 508 ti,mac-only; 509 label = "port1"; 510 phys = <&phy_gmii_sel 1>; 511 mac-address = [00 00 00 00 00 00]; 512 ti,syscon-efuse = <&main_conf 0x200>; 513 }; 514 515 cpsw_port2: port@2 { 516 reg = <2>; 517 ti,mac-only; 518 label = "port2"; 519 phys = <&phy_gmii_sel 2>; 520 mac-address = [00 00 00 00 00 00]; 521 }; 522 }; 523 524 cpsw3g_mdio: mdio@f00 { 525 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 526 reg = <0x0 0xf00 0x0 0x100>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 clocks = <&k3_clks 13 0>; 530 clock-names = "fck"; 531 bus_freq = <1000000>; 532 }; 533 534 cpts@3d000 { 535 compatible = "ti,j721e-cpts"; 536 reg = <0x0 0x3d000 0x0 0x400>; 537 clocks = <&k3_clks 13 1>; 538 clock-names = "cpts"; 539 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-names = "cpts"; 541 ti,cpts-ext-ts-inputs = <4>; 542 ti,cpts-periodic-outputs = <2>; 543 }; 544 }; 545 546 cpts@39000000 { 547 compatible = "ti,j721e-cpts"; 548 reg = <0x0 0x39000000 0x0 0x400>; 549 reg-names = "cpts"; 550 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 551 clocks = <&k3_clks 84 0>; 552 clock-names = "cpts"; 553 assigned-clocks = <&k3_clks 84 0>; 554 assigned-clock-parents = <&k3_clks 84 8>; 555 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 556 interrupt-names = "cpts"; 557 ti,cpts-periodic-outputs = <6>; 558 ti,cpts-ext-ts-inputs = <8>; 559 }; 560 561 usbss0: cdns-usb@f900000{ 562 compatible = "ti,am64-usb"; 563 reg = <0x00 0xf900000 0x00 0x100>; 564 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 565 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 566 clock-names = "ref", "lpm"; 567 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 568 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 569 #address-cells = <2>; 570 #size-cells = <2>; 571 ranges; 572 usb0: usb@f400000{ 573 compatible = "cdns,usb3"; 574 reg = <0x00 0xf400000 0x00 0x10000>, 575 <0x00 0xf410000 0x00 0x10000>, 576 <0x00 0xf420000 0x00 0x10000>; 577 reg-names = "otg", 578 "xhci", 579 "dev"; 580 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 581 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 582 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 583 interrupt-names = "host", 584 "peripheral", 585 "otg"; 586 maximum-speed = "super-speed"; 587 dr_mode = "otg"; 588 }; 589 }; 590 591 tscadc0: tscadc@28001000 { 592 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 593 reg = <0x00 0x28001000 0x00 0x1000>; 594 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 595 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 596 clocks = <&k3_clks 0 0>; 597 assigned-clocks = <&k3_clks 0 0>; 598 assigned-clock-parents = <&k3_clks 0 3>; 599 assigned-clock-rates = <60000000>; 600 clock-names = "adc_tsc_fck"; 601 602 adc { 603 #io-channel-cells = <1>; 604 compatible = "ti,am654-adc", "ti,am3359-adc"; 605 }; 606 }; 607 608 fss: bus@fc00000 { 609 compatible = "simple-bus"; 610 reg = <0x00 0x0fc00000 0x00 0x70000>; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges; 614 615 ospi0: spi@fc40000 { 616 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 617 reg = <0x00 0x0fc40000 0x00 0x100>, 618 <0x05 0x00000000 0x01 0x00000000>; 619 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 620 cdns,fifo-depth = <256>; 621 cdns,fifo-width = <4>; 622 cdns,trigger-address = <0x0>; 623 #address-cells = <0x1>; 624 #size-cells = <0x0>; 625 clocks = <&k3_clks 75 6>; 626 assigned-clocks = <&k3_clks 75 6>; 627 assigned-clock-parents = <&k3_clks 75 7>; 628 assigned-clock-rates = <166666666>; 629 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 630 }; 631 }; 632 633 hwspinlock: spinlock@2a000000 { 634 compatible = "ti,am64-hwspinlock"; 635 reg = <0x00 0x2a000000 0x00 0x1000>; 636 #hwlock-cells = <1>; 637 }; 638 639 mailbox0_cluster2: mailbox@29020000 { 640 compatible = "ti,am64-mailbox"; 641 reg = <0x00 0x29020000 0x00 0x200>; 642 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 644 #mbox-cells = <1>; 645 ti,mbox-num-users = <4>; 646 ti,mbox-num-fifos = <16>; 647 }; 648 649 mailbox0_cluster3: mailbox@29030000 { 650 compatible = "ti,am64-mailbox"; 651 reg = <0x00 0x29030000 0x00 0x200>; 652 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 654 #mbox-cells = <1>; 655 ti,mbox-num-users = <4>; 656 ti,mbox-num-fifos = <16>; 657 }; 658 659 mailbox0_cluster4: mailbox@29040000 { 660 compatible = "ti,am64-mailbox"; 661 reg = <0x00 0x29040000 0x00 0x200>; 662 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 664 #mbox-cells = <1>; 665 ti,mbox-num-users = <4>; 666 ti,mbox-num-fifos = <16>; 667 }; 668 669 mailbox0_cluster5: mailbox@29050000 { 670 compatible = "ti,am64-mailbox"; 671 reg = <0x00 0x29050000 0x00 0x200>; 672 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 674 #mbox-cells = <1>; 675 ti,mbox-num-users = <4>; 676 ti,mbox-num-fifos = <16>; 677 }; 678 679 mailbox0_cluster6: mailbox@29060000 { 680 compatible = "ti,am64-mailbox"; 681 reg = <0x00 0x29060000 0x00 0x200>; 682 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 683 #mbox-cells = <1>; 684 ti,mbox-num-users = <4>; 685 ti,mbox-num-fifos = <16>; 686 }; 687 688 mailbox0_cluster7: mailbox@29070000 { 689 compatible = "ti,am64-mailbox"; 690 reg = <0x00 0x29070000 0x00 0x200>; 691 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 692 #mbox-cells = <1>; 693 ti,mbox-num-users = <4>; 694 ti,mbox-num-fifos = <16>; 695 }; 696 697 main_r5fss0: r5fss@78000000 { 698 compatible = "ti,am64-r5fss"; 699 ti,cluster-mode = <0>; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges = <0x78000000 0x00 0x78000000 0x10000>, 703 <0x78100000 0x00 0x78100000 0x10000>, 704 <0x78200000 0x00 0x78200000 0x08000>, 705 <0x78300000 0x00 0x78300000 0x08000>; 706 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 707 708 main_r5fss0_core0: r5f@78000000 { 709 compatible = "ti,am64-r5f"; 710 reg = <0x78000000 0x00010000>, 711 <0x78100000 0x00010000>; 712 reg-names = "atcm", "btcm"; 713 ti,sci = <&dmsc>; 714 ti,sci-dev-id = <121>; 715 ti,sci-proc-ids = <0x01 0xff>; 716 resets = <&k3_reset 121 1>; 717 firmware-name = "am64-main-r5f0_0-fw"; 718 ti,atcm-enable = <1>; 719 ti,btcm-enable = <1>; 720 ti,loczrama = <1>; 721 }; 722 723 main_r5fss0_core1: r5f@78200000 { 724 compatible = "ti,am64-r5f"; 725 reg = <0x78200000 0x00008000>, 726 <0x78300000 0x00008000>; 727 reg-names = "atcm", "btcm"; 728 ti,sci = <&dmsc>; 729 ti,sci-dev-id = <122>; 730 ti,sci-proc-ids = <0x02 0xff>; 731 resets = <&k3_reset 122 1>; 732 firmware-name = "am64-main-r5f0_1-fw"; 733 ti,atcm-enable = <1>; 734 ti,btcm-enable = <1>; 735 ti,loczrama = <1>; 736 }; 737 }; 738 739 main_r5fss1: r5fss@78400000 { 740 compatible = "ti,am64-r5fss"; 741 ti,cluster-mode = <0>; 742 #address-cells = <1>; 743 #size-cells = <1>; 744 ranges = <0x78400000 0x00 0x78400000 0x10000>, 745 <0x78500000 0x00 0x78500000 0x10000>, 746 <0x78600000 0x00 0x78600000 0x08000>, 747 <0x78700000 0x00 0x78700000 0x08000>; 748 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 749 750 main_r5fss1_core0: r5f@78400000 { 751 compatible = "ti,am64-r5f"; 752 reg = <0x78400000 0x00010000>, 753 <0x78500000 0x00010000>; 754 reg-names = "atcm", "btcm"; 755 ti,sci = <&dmsc>; 756 ti,sci-dev-id = <123>; 757 ti,sci-proc-ids = <0x06 0xff>; 758 resets = <&k3_reset 123 1>; 759 firmware-name = "am64-main-r5f1_0-fw"; 760 ti,atcm-enable = <1>; 761 ti,btcm-enable = <1>; 762 ti,loczrama = <1>; 763 }; 764 765 main_r5fss1_core1: r5f@78600000 { 766 compatible = "ti,am64-r5f"; 767 reg = <0x78600000 0x00008000>, 768 <0x78700000 0x00008000>; 769 reg-names = "atcm", "btcm"; 770 ti,sci = <&dmsc>; 771 ti,sci-dev-id = <124>; 772 ti,sci-proc-ids = <0x07 0xff>; 773 resets = <&k3_reset 124 1>; 774 firmware-name = "am64-main-r5f1_1-fw"; 775 ti,atcm-enable = <1>; 776 ti,btcm-enable = <1>; 777 ti,loczrama = <1>; 778 }; 779 }; 780 781 serdes_wiz0: wiz@f000000 { 782 compatible = "ti,am64-wiz-10g"; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 786 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 787 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 788 num-lanes = <1>; 789 #reset-cells = <1>; 790 #clock-cells = <1>; 791 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 792 793 assigned-clocks = <&k3_clks 162 1>; 794 assigned-clock-parents = <&k3_clks 162 5>; 795 796 serdes0: serdes@f000000 { 797 compatible = "ti,j721e-serdes-10g"; 798 reg = <0x0f000000 0x00010000>; 799 reg-names = "torrent_phy"; 800 resets = <&serdes_wiz0 0>; 801 reset-names = "torrent_reset"; 802 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 803 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 804 clock-names = "refclk", "phy_en_refclk"; 805 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 806 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 807 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 808 assigned-clock-parents = <&k3_clks 162 1>, 809 <&k3_clks 162 1>, 810 <&k3_clks 162 1>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 #clock-cells = <1>; 814 }; 815 }; 816 817 pcie0_rc: pcie@f102000 { 818 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 819 reg = <0x00 0x0f102000 0x00 0x1000>, 820 <0x00 0x0f100000 0x00 0x400>, 821 <0x00 0x0d000000 0x00 0x00800000>, 822 <0x00 0x68000000 0x00 0x00001000>; 823 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 824 interrupt-names = "link_state"; 825 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 826 device_type = "pci"; 827 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 828 max-link-speed = <2>; 829 num-lanes = <1>; 830 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 832 clock-names = "fck", "pcie_refclk"; 833 #address-cells = <3>; 834 #size-cells = <2>; 835 bus-range = <0x0 0xff>; 836 cdns,no-bar-match-nbits = <64>; 837 vendor-id = <0x104c>; 838 device-id = <0xb010>; 839 msi-map = <0x0 &gic_its 0x0 0x10000>; 840 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 841 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 842 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 843 }; 844 845 pcie0_ep: pcie-ep@f102000 { 846 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 847 reg = <0x00 0x0f102000 0x00 0x1000>, 848 <0x00 0x0f100000 0x00 0x400>, 849 <0x00 0x0d000000 0x00 0x00800000>, 850 <0x00 0x68000000 0x00 0x08000000>; 851 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 852 interrupt-names = "link_state"; 853 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 854 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 855 max-link-speed = <2>; 856 num-lanes = <1>; 857 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 858 clocks = <&k3_clks 114 0>; 859 clock-names = "fck"; 860 max-functions = /bits/ 8 <1>; 861 }; 862}; 863