1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x0 0x43000000 0x0 0x20000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 47 serdes_ln_ctrl: mux-controller { 48 compatible = "mmio-mux"; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 51 }; 52 }; 53 54 gic500: interrupt-controller@1800000 { 55 compatible = "arm,gic-v3"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 62 <0x00 0x01840000 0x00 0xC0000>; /* GICR */ 63 /* 64 * vcpumntirq: 65 * virtual CPU interface maintenance interrupt 66 */ 67 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 68 69 gic_its: msi-controller@1820000 { 70 compatible = "arm,gic-v3-its"; 71 reg = <0x00 0x01820000 0x00 0x10000>; 72 socionext,synquacer-pre-its = <0x1000000 0x400000>; 73 msi-controller; 74 #msi-cells = <1>; 75 }; 76 }; 77 78 dmss: bus@48000000 { 79 compatible = "simple-mfd"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 dma-ranges; 83 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 84 85 ti,sci-dev-id = <25>; 86 87 secure_proxy_main: mailbox@4d000000 { 88 compatible = "ti,am654-secure-proxy"; 89 #mbox-cells = <1>; 90 reg-names = "target_data", "rt", "scfg"; 91 reg = <0x00 0x4d000000 0x00 0x80000>, 92 <0x00 0x4a600000 0x00 0x80000>, 93 <0x00 0x4a400000 0x00 0x80000>; 94 interrupt-names = "rx_012"; 95 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 96 }; 97 98 inta_main_dmss: interrupt-controller@48000000 { 99 compatible = "ti,sci-inta"; 100 reg = <0x00 0x48000000 0x00 0x100000>; 101 #interrupt-cells = <0>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 msi-controller; 105 ti,sci = <&dmsc>; 106 ti,sci-dev-id = <28>; 107 ti,interrupt-ranges = <4 68 36>; 108 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 109 }; 110 111 main_bcdma: dma-controller@485c0100 { 112 compatible = "ti,am64-dmss-bcdma"; 113 reg = <0x00 0x485c0100 0x00 0x100>, 114 <0x00 0x4c000000 0x00 0x20000>, 115 <0x00 0x4a820000 0x00 0x20000>, 116 <0x00 0x4aa40000 0x00 0x20000>, 117 <0x00 0x4bc00000 0x00 0x100000>; 118 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 119 msi-parent = <&inta_main_dmss>; 120 #dma-cells = <3>; 121 122 ti,sci = <&dmsc>; 123 ti,sci-dev-id = <26>; 124 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 125 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 126 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 127 }; 128 129 main_pktdma: dma-controller@485c0000 { 130 compatible = "ti,am64-dmss-pktdma"; 131 reg = <0x00 0x485c0000 0x00 0x100>, 132 <0x00 0x4a800000 0x00 0x20000>, 133 <0x00 0x4aa00000 0x00 0x40000>, 134 <0x00 0x4b800000 0x00 0x400000>; 135 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 136 msi-parent = <&inta_main_dmss>; 137 #dma-cells = <2>; 138 139 ti,sci = <&dmsc>; 140 ti,sci-dev-id = <30>; 141 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 142 <0x24>, /* CPSW_TX_CHAN */ 143 <0x25>, /* SAUL_TX_0_CHAN */ 144 <0x26>, /* SAUL_TX_1_CHAN */ 145 <0x27>, /* ICSSG_0_TX_CHAN */ 146 <0x28>; /* ICSSG_1_TX_CHAN */ 147 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 148 <0x11>, /* RING_CPSW_TX_CHAN */ 149 <0x12>, /* RING_SAUL_TX_0_CHAN */ 150 <0x13>, /* RING_SAUL_TX_1_CHAN */ 151 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 152 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 153 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 154 <0x2b>, /* CPSW_RX_CHAN */ 155 <0x2d>, /* SAUL_RX_0_CHAN */ 156 <0x2f>, /* SAUL_RX_1_CHAN */ 157 <0x31>, /* SAUL_RX_2_CHAN */ 158 <0x33>, /* SAUL_RX_3_CHAN */ 159 <0x35>, /* ICSSG_0_RX_CHAN */ 160 <0x37>; /* ICSSG_1_RX_CHAN */ 161 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 162 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 163 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 164 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 165 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 166 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 167 }; 168 }; 169 170 dmsc: system-controller@44043000 { 171 compatible = "ti,k2g-sci"; 172 ti,host-id = <12>; 173 mbox-names = "rx", "tx"; 174 mboxes= <&secure_proxy_main 12>, 175 <&secure_proxy_main 13>; 176 reg-names = "debug_messages"; 177 reg = <0x00 0x44043000 0x00 0xfe0>; 178 179 k3_pds: power-controller { 180 compatible = "ti,sci-pm-domain"; 181 #power-domain-cells = <2>; 182 }; 183 184 k3_clks: clock-controller { 185 compatible = "ti,k2g-sci-clk"; 186 #clock-cells = <2>; 187 }; 188 189 k3_reset: reset-controller { 190 compatible = "ti,sci-reset"; 191 #reset-cells = <2>; 192 }; 193 }; 194 195 main_pmx0: pinctrl@f4000 { 196 compatible = "pinctrl-single"; 197 reg = <0x00 0xf4000 0x00 0x2d0>; 198 #pinctrl-cells = <1>; 199 pinctrl-single,register-width = <32>; 200 pinctrl-single,function-mask = <0xffffffff>; 201 }; 202 203 main_conf: syscon@43000000 { 204 compatible = "syscon", "simple-mfd"; 205 reg = <0x00 0x43000000 0x00 0x20000>; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges = <0x00 0x00 0x43000000 0x20000>; 209 210 chipid@14 { 211 compatible = "ti,am654-chipid"; 212 reg = <0x00000014 0x4>; 213 }; 214 215 phy_gmii_sel: phy@4044 { 216 compatible = "ti,am654-phy-gmii-sel"; 217 reg = <0x4044 0x8>; 218 #phy-cells = <1>; 219 }; 220 221 epwm_tbclk: clock@4140 { 222 compatible = "ti,am64-epwm-tbclk", "syscon"; 223 reg = <0x4130 0x4>; 224 #clock-cells = <1>; 225 }; 226 }; 227 228 main_uart0: serial@2800000 { 229 compatible = "ti,am64-uart", "ti,am654-uart"; 230 reg = <0x00 0x02800000 0x00 0x100>; 231 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 232 clock-frequency = <48000000>; 233 current-speed = <115200>; 234 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 235 clocks = <&k3_clks 146 0>; 236 clock-names = "fclk"; 237 }; 238 239 main_uart1: serial@2810000 { 240 compatible = "ti,am64-uart", "ti,am654-uart"; 241 reg = <0x00 0x02810000 0x00 0x100>; 242 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 243 clock-frequency = <48000000>; 244 current-speed = <115200>; 245 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 246 clocks = <&k3_clks 152 0>; 247 clock-names = "fclk"; 248 }; 249 250 main_uart2: serial@2820000 { 251 compatible = "ti,am64-uart", "ti,am654-uart"; 252 reg = <0x00 0x02820000 0x00 0x100>; 253 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 254 clock-frequency = <48000000>; 255 current-speed = <115200>; 256 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 257 clocks = <&k3_clks 153 0>; 258 clock-names = "fclk"; 259 }; 260 261 main_uart3: serial@2830000 { 262 compatible = "ti,am64-uart", "ti,am654-uart"; 263 reg = <0x00 0x02830000 0x00 0x100>; 264 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 265 clock-frequency = <48000000>; 266 current-speed = <115200>; 267 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 268 clocks = <&k3_clks 154 0>; 269 clock-names = "fclk"; 270 }; 271 272 main_uart4: serial@2840000 { 273 compatible = "ti,am64-uart", "ti,am654-uart"; 274 reg = <0x00 0x02840000 0x00 0x100>; 275 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 276 clock-frequency = <48000000>; 277 current-speed = <115200>; 278 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 279 clocks = <&k3_clks 155 0>; 280 clock-names = "fclk"; 281 }; 282 283 main_uart5: serial@2850000 { 284 compatible = "ti,am64-uart", "ti,am654-uart"; 285 reg = <0x00 0x02850000 0x00 0x100>; 286 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 287 clock-frequency = <48000000>; 288 current-speed = <115200>; 289 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 290 clocks = <&k3_clks 156 0>; 291 clock-names = "fclk"; 292 }; 293 294 main_uart6: serial@2860000 { 295 compatible = "ti,am64-uart", "ti,am654-uart"; 296 reg = <0x00 0x02860000 0x00 0x100>; 297 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 298 clock-frequency = <48000000>; 299 current-speed = <115200>; 300 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 301 clocks = <&k3_clks 158 0>; 302 clock-names = "fclk"; 303 }; 304 305 main_i2c0: i2c@20000000 { 306 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 307 reg = <0x00 0x20000000 0x00 0x100>; 308 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 312 clocks = <&k3_clks 102 2>; 313 clock-names = "fck"; 314 }; 315 316 main_i2c1: i2c@20010000 { 317 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 318 reg = <0x00 0x20010000 0x00 0x100>; 319 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 323 clocks = <&k3_clks 103 2>; 324 clock-names = "fck"; 325 }; 326 327 main_i2c2: i2c@20020000 { 328 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 329 reg = <0x00 0x20020000 0x00 0x100>; 330 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 334 clocks = <&k3_clks 104 2>; 335 clock-names = "fck"; 336 }; 337 338 main_i2c3: i2c@20030000 { 339 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 340 reg = <0x00 0x20030000 0x00 0x100>; 341 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 345 clocks = <&k3_clks 105 2>; 346 clock-names = "fck"; 347 }; 348 349 main_spi0: spi@20100000 { 350 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 351 reg = <0x00 0x20100000 0x00 0x400>; 352 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 141 0>; 357 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 358 dma-names = "tx0", "rx0"; 359 }; 360 361 main_spi1: spi@20110000 { 362 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 363 reg = <0x00 0x20110000 0x00 0x400>; 364 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 368 clocks = <&k3_clks 142 0>; 369 }; 370 371 main_spi2: spi@20120000 { 372 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 373 reg = <0x00 0x20120000 0x00 0x400>; 374 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 378 clocks = <&k3_clks 143 0>; 379 }; 380 381 main_spi3: spi@20130000 { 382 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 383 reg = <0x00 0x20130000 0x00 0x400>; 384 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 388 clocks = <&k3_clks 144 0>; 389 }; 390 391 main_spi4: spi@20140000 { 392 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 393 reg = <0x00 0x20140000 0x00 0x400>; 394 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 398 clocks = <&k3_clks 145 0>; 399 }; 400 401 main_gpio_intr: interrupt-controller@a00000 { 402 compatible = "ti,sci-intr"; 403 reg = <0x00 0x00a00000 0x00 0x800>; 404 ti,intr-trigger-type = <1>; 405 interrupt-controller; 406 interrupt-parent = <&gic500>; 407 #interrupt-cells = <1>; 408 ti,sci = <&dmsc>; 409 ti,sci-dev-id = <3>; 410 ti,interrupt-ranges = <0 32 16>; 411 }; 412 413 main_gpio0: gpio@600000 { 414 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 415 reg = <0x0 0x00600000 0x0 0x100>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-parent = <&main_gpio_intr>; 419 interrupts = <190>, <191>, <192>, 420 <193>, <194>, <195>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 ti,ngpio = <87>; 424 ti,davinci-gpio-unbanked = <0>; 425 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 77 0>; 427 clock-names = "gpio"; 428 }; 429 430 main_gpio1: gpio@601000 { 431 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 432 reg = <0x0 0x00601000 0x0 0x100>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-parent = <&main_gpio_intr>; 436 interrupts = <180>, <181>, <182>, 437 <183>, <184>, <185>; 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 ti,ngpio = <88>; 441 ti,davinci-gpio-unbanked = <0>; 442 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 443 clocks = <&k3_clks 78 0>; 444 clock-names = "gpio"; 445 }; 446 447 sdhci0: mmc@fa10000 { 448 compatible = "ti,am64-sdhci-8bit"; 449 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 450 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 451 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 452 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 453 clock-names = "clk_ahb", "clk_xin"; 454 mmc-ddr-1_8v; 455 mmc-hs200-1_8v; 456 mmc-hs400-1_8v; 457 ti,trm-icp = <0x2>; 458 ti,otap-del-sel-legacy = <0x0>; 459 ti,otap-del-sel-mmc-hs = <0x0>; 460 ti,otap-del-sel-ddr52 = <0x6>; 461 ti,otap-del-sel-hs200 = <0x7>; 462 ti,otap-del-sel-hs400 = <0x4>; 463 }; 464 465 sdhci1: mmc@fa00000 { 466 compatible = "ti,am64-sdhci-4bit"; 467 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 468 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 469 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 470 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 471 clock-names = "clk_ahb", "clk_xin"; 472 ti,trm-icp = <0x2>; 473 ti,otap-del-sel-legacy = <0x0>; 474 ti,otap-del-sel-sd-hs = <0xf>; 475 ti,otap-del-sel-sdr12 = <0xf>; 476 ti,otap-del-sel-sdr25 = <0xf>; 477 ti,otap-del-sel-sdr50 = <0xc>; 478 ti,otap-del-sel-sdr104 = <0x6>; 479 ti,otap-del-sel-ddr50 = <0x9>; 480 ti,clkbuf-sel = <0x7>; 481 }; 482 483 cpsw3g: ethernet@8000000 { 484 compatible = "ti,am642-cpsw-nuss"; 485 #address-cells = <2>; 486 #size-cells = <2>; 487 reg = <0x0 0x8000000 0x0 0x200000>; 488 reg-names = "cpsw_nuss"; 489 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 490 clocks = <&k3_clks 13 0>; 491 assigned-clocks = <&k3_clks 13 1>; 492 assigned-clock-parents = <&k3_clks 13 9>; 493 clock-names = "fck"; 494 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 495 496 dmas = <&main_pktdma 0xC500 15>, 497 <&main_pktdma 0xC501 15>, 498 <&main_pktdma 0xC502 15>, 499 <&main_pktdma 0xC503 15>, 500 <&main_pktdma 0xC504 15>, 501 <&main_pktdma 0xC505 15>, 502 <&main_pktdma 0xC506 15>, 503 <&main_pktdma 0xC507 15>, 504 <&main_pktdma 0x4500 15>; 505 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 506 "tx7", "rx"; 507 508 ethernet-ports { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 cpsw_port1: port@1 { 513 reg = <1>; 514 ti,mac-only; 515 label = "port1"; 516 phys = <&phy_gmii_sel 1>; 517 mac-address = [00 00 00 00 00 00]; 518 ti,syscon-efuse = <&main_conf 0x200>; 519 }; 520 521 cpsw_port2: port@2 { 522 reg = <2>; 523 ti,mac-only; 524 label = "port2"; 525 phys = <&phy_gmii_sel 2>; 526 mac-address = [00 00 00 00 00 00]; 527 }; 528 }; 529 530 cpsw3g_mdio: mdio@f00 { 531 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 532 reg = <0x0 0xf00 0x0 0x100>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 clocks = <&k3_clks 13 0>; 536 clock-names = "fck"; 537 bus_freq = <1000000>; 538 }; 539 540 cpts@3d000 { 541 compatible = "ti,j721e-cpts"; 542 reg = <0x0 0x3d000 0x0 0x400>; 543 clocks = <&k3_clks 13 1>; 544 clock-names = "cpts"; 545 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 546 interrupt-names = "cpts"; 547 ti,cpts-ext-ts-inputs = <4>; 548 ti,cpts-periodic-outputs = <2>; 549 }; 550 }; 551 552 cpts@39000000 { 553 compatible = "ti,j721e-cpts"; 554 reg = <0x0 0x39000000 0x0 0x400>; 555 reg-names = "cpts"; 556 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 557 clocks = <&k3_clks 84 0>; 558 clock-names = "cpts"; 559 assigned-clocks = <&k3_clks 84 0>; 560 assigned-clock-parents = <&k3_clks 84 8>; 561 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "cpts"; 563 ti,cpts-periodic-outputs = <6>; 564 ti,cpts-ext-ts-inputs = <8>; 565 }; 566 567 timesync_router: pinctrl@a40000 { 568 compatible = "pinctrl-single"; 569 reg = <0x0 0xa40000 0x0 0x800>; 570 #pinctrl-cells = <1>; 571 pinctrl-single,register-width = <32>; 572 pinctrl-single,function-mask = <0x000107ff>; 573 }; 574 575 usbss0: cdns-usb@f900000{ 576 compatible = "ti,am64-usb"; 577 reg = <0x00 0xf900000 0x00 0x100>; 578 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 579 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 580 clock-names = "ref", "lpm"; 581 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 582 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 583 #address-cells = <2>; 584 #size-cells = <2>; 585 ranges; 586 usb0: usb@f400000{ 587 compatible = "cdns,usb3"; 588 reg = <0x00 0xf400000 0x00 0x10000>, 589 <0x00 0xf410000 0x00 0x10000>, 590 <0x00 0xf420000 0x00 0x10000>; 591 reg-names = "otg", 592 "xhci", 593 "dev"; 594 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 595 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 596 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 597 interrupt-names = "host", 598 "peripheral", 599 "otg"; 600 maximum-speed = "super-speed"; 601 dr_mode = "otg"; 602 }; 603 }; 604 605 tscadc0: tscadc@28001000 { 606 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 607 reg = <0x00 0x28001000 0x00 0x1000>; 608 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 609 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 610 clocks = <&k3_clks 0 0>; 611 assigned-clocks = <&k3_clks 0 0>; 612 assigned-clock-parents = <&k3_clks 0 3>; 613 assigned-clock-rates = <60000000>; 614 clock-names = "adc_tsc_fck"; 615 616 adc { 617 #io-channel-cells = <1>; 618 compatible = "ti,am654-adc", "ti,am3359-adc"; 619 }; 620 }; 621 622 fss: bus@fc00000 { 623 compatible = "simple-bus"; 624 reg = <0x00 0x0fc00000 0x00 0x70000>; 625 #address-cells = <2>; 626 #size-cells = <2>; 627 ranges; 628 629 ospi0: spi@fc40000 { 630 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 631 reg = <0x00 0x0fc40000 0x00 0x100>, 632 <0x05 0x00000000 0x01 0x00000000>; 633 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 634 cdns,fifo-depth = <256>; 635 cdns,fifo-width = <4>; 636 cdns,trigger-address = <0x0>; 637 #address-cells = <0x1>; 638 #size-cells = <0x0>; 639 clocks = <&k3_clks 75 6>; 640 assigned-clocks = <&k3_clks 75 6>; 641 assigned-clock-parents = <&k3_clks 75 7>; 642 assigned-clock-rates = <166666666>; 643 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 644 }; 645 }; 646 647 hwspinlock: spinlock@2a000000 { 648 compatible = "ti,am64-hwspinlock"; 649 reg = <0x00 0x2a000000 0x00 0x1000>; 650 #hwlock-cells = <1>; 651 }; 652 653 mailbox0_cluster2: mailbox@29020000 { 654 compatible = "ti,am64-mailbox"; 655 reg = <0x00 0x29020000 0x00 0x200>; 656 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 658 #mbox-cells = <1>; 659 ti,mbox-num-users = <4>; 660 ti,mbox-num-fifos = <16>; 661 }; 662 663 mailbox0_cluster3: mailbox@29030000 { 664 compatible = "ti,am64-mailbox"; 665 reg = <0x00 0x29030000 0x00 0x200>; 666 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 668 #mbox-cells = <1>; 669 ti,mbox-num-users = <4>; 670 ti,mbox-num-fifos = <16>; 671 }; 672 673 mailbox0_cluster4: mailbox@29040000 { 674 compatible = "ti,am64-mailbox"; 675 reg = <0x00 0x29040000 0x00 0x200>; 676 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 678 #mbox-cells = <1>; 679 ti,mbox-num-users = <4>; 680 ti,mbox-num-fifos = <16>; 681 }; 682 683 mailbox0_cluster5: mailbox@29050000 { 684 compatible = "ti,am64-mailbox"; 685 reg = <0x00 0x29050000 0x00 0x200>; 686 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 688 #mbox-cells = <1>; 689 ti,mbox-num-users = <4>; 690 ti,mbox-num-fifos = <16>; 691 }; 692 693 mailbox0_cluster6: mailbox@29060000 { 694 compatible = "ti,am64-mailbox"; 695 reg = <0x00 0x29060000 0x00 0x200>; 696 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 697 #mbox-cells = <1>; 698 ti,mbox-num-users = <4>; 699 ti,mbox-num-fifos = <16>; 700 }; 701 702 mailbox0_cluster7: mailbox@29070000 { 703 compatible = "ti,am64-mailbox"; 704 reg = <0x00 0x29070000 0x00 0x200>; 705 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 706 #mbox-cells = <1>; 707 ti,mbox-num-users = <4>; 708 ti,mbox-num-fifos = <16>; 709 }; 710 711 main_r5fss0: r5fss@78000000 { 712 compatible = "ti,am64-r5fss"; 713 ti,cluster-mode = <0>; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 ranges = <0x78000000 0x00 0x78000000 0x10000>, 717 <0x78100000 0x00 0x78100000 0x10000>, 718 <0x78200000 0x00 0x78200000 0x08000>, 719 <0x78300000 0x00 0x78300000 0x08000>; 720 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 721 722 main_r5fss0_core0: r5f@78000000 { 723 compatible = "ti,am64-r5f"; 724 reg = <0x78000000 0x00010000>, 725 <0x78100000 0x00010000>; 726 reg-names = "atcm", "btcm"; 727 ti,sci = <&dmsc>; 728 ti,sci-dev-id = <121>; 729 ti,sci-proc-ids = <0x01 0xff>; 730 resets = <&k3_reset 121 1>; 731 firmware-name = "am64-main-r5f0_0-fw"; 732 ti,atcm-enable = <1>; 733 ti,btcm-enable = <1>; 734 ti,loczrama = <1>; 735 }; 736 737 main_r5fss0_core1: r5f@78200000 { 738 compatible = "ti,am64-r5f"; 739 reg = <0x78200000 0x00008000>, 740 <0x78300000 0x00008000>; 741 reg-names = "atcm", "btcm"; 742 ti,sci = <&dmsc>; 743 ti,sci-dev-id = <122>; 744 ti,sci-proc-ids = <0x02 0xff>; 745 resets = <&k3_reset 122 1>; 746 firmware-name = "am64-main-r5f0_1-fw"; 747 ti,atcm-enable = <1>; 748 ti,btcm-enable = <1>; 749 ti,loczrama = <1>; 750 }; 751 }; 752 753 main_r5fss1: r5fss@78400000 { 754 compatible = "ti,am64-r5fss"; 755 ti,cluster-mode = <0>; 756 #address-cells = <1>; 757 #size-cells = <1>; 758 ranges = <0x78400000 0x00 0x78400000 0x10000>, 759 <0x78500000 0x00 0x78500000 0x10000>, 760 <0x78600000 0x00 0x78600000 0x08000>, 761 <0x78700000 0x00 0x78700000 0x08000>; 762 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 763 764 main_r5fss1_core0: r5f@78400000 { 765 compatible = "ti,am64-r5f"; 766 reg = <0x78400000 0x00010000>, 767 <0x78500000 0x00010000>; 768 reg-names = "atcm", "btcm"; 769 ti,sci = <&dmsc>; 770 ti,sci-dev-id = <123>; 771 ti,sci-proc-ids = <0x06 0xff>; 772 resets = <&k3_reset 123 1>; 773 firmware-name = "am64-main-r5f1_0-fw"; 774 ti,atcm-enable = <1>; 775 ti,btcm-enable = <1>; 776 ti,loczrama = <1>; 777 }; 778 779 main_r5fss1_core1: r5f@78600000 { 780 compatible = "ti,am64-r5f"; 781 reg = <0x78600000 0x00008000>, 782 <0x78700000 0x00008000>; 783 reg-names = "atcm", "btcm"; 784 ti,sci = <&dmsc>; 785 ti,sci-dev-id = <124>; 786 ti,sci-proc-ids = <0x07 0xff>; 787 resets = <&k3_reset 124 1>; 788 firmware-name = "am64-main-r5f1_1-fw"; 789 ti,atcm-enable = <1>; 790 ti,btcm-enable = <1>; 791 ti,loczrama = <1>; 792 }; 793 }; 794 795 serdes_wiz0: wiz@f000000 { 796 compatible = "ti,am64-wiz-10g"; 797 #address-cells = <1>; 798 #size-cells = <1>; 799 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 800 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 801 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 802 num-lanes = <1>; 803 #reset-cells = <1>; 804 #clock-cells = <1>; 805 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 806 807 assigned-clocks = <&k3_clks 162 1>; 808 assigned-clock-parents = <&k3_clks 162 5>; 809 810 serdes0: serdes@f000000 { 811 compatible = "ti,j721e-serdes-10g"; 812 reg = <0x0f000000 0x00010000>; 813 reg-names = "torrent_phy"; 814 resets = <&serdes_wiz0 0>; 815 reset-names = "torrent_reset"; 816 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 817 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 818 clock-names = "refclk", "phy_en_refclk"; 819 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 820 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 821 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 822 assigned-clock-parents = <&k3_clks 162 1>, 823 <&k3_clks 162 1>, 824 <&k3_clks 162 1>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 #clock-cells = <1>; 828 }; 829 }; 830 831 pcie0_rc: pcie@f102000 { 832 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 833 reg = <0x00 0x0f102000 0x00 0x1000>, 834 <0x00 0x0f100000 0x00 0x400>, 835 <0x00 0x0d000000 0x00 0x00800000>, 836 <0x00 0x68000000 0x00 0x00001000>; 837 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 838 interrupt-names = "link_state"; 839 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 840 device_type = "pci"; 841 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 842 max-link-speed = <2>; 843 num-lanes = <1>; 844 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 845 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 846 clock-names = "fck", "pcie_refclk"; 847 #address-cells = <3>; 848 #size-cells = <2>; 849 bus-range = <0x0 0xff>; 850 cdns,no-bar-match-nbits = <64>; 851 vendor-id = <0x104c>; 852 device-id = <0xb010>; 853 msi-map = <0x0 &gic_its 0x0 0x10000>; 854 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 855 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 856 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 857 }; 858 859 pcie0_ep: pcie-ep@f102000 { 860 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 861 reg = <0x00 0x0f102000 0x00 0x1000>, 862 <0x00 0x0f100000 0x00 0x400>, 863 <0x00 0x0d000000 0x00 0x00800000>, 864 <0x00 0x68000000 0x00 0x08000000>; 865 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 866 interrupt-names = "link_state"; 867 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 868 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 869 max-link-speed = <2>; 870 num-lanes = <1>; 871 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 872 clocks = <&k3_clks 114 0>; 873 clock-names = "fck"; 874 max-functions = /bits/ 8 <1>; 875 }; 876 877 epwm0: pwm@23000000 { 878 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 879 #pwm-cells = <3>; 880 reg = <0x0 0x23000000 0x0 0x100>; 881 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 882 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 883 clock-names = "tbclk", "fck"; 884 }; 885 886 epwm1: pwm@23010000 { 887 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 888 #pwm-cells = <3>; 889 reg = <0x0 0x23010000 0x0 0x100>; 890 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 891 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 892 clock-names = "tbclk", "fck"; 893 }; 894 895 epwm2: pwm@23020000 { 896 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 897 #pwm-cells = <3>; 898 reg = <0x0 0x23020000 0x0 0x100>; 899 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 900 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 901 clock-names = "tbclk", "fck"; 902 }; 903 904 epwm3: pwm@23030000 { 905 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 906 #pwm-cells = <3>; 907 reg = <0x0 0x23030000 0x0 0x100>; 908 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 909 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 910 clock-names = "tbclk", "fck"; 911 }; 912 913 epwm4: pwm@23040000 { 914 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 915 #pwm-cells = <3>; 916 reg = <0x0 0x23040000 0x0 0x100>; 917 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 918 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 919 clock-names = "tbclk", "fck"; 920 }; 921 922 epwm5: pwm@23050000 { 923 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 924 #pwm-cells = <3>; 925 reg = <0x0 0x23050000 0x0 0x100>; 926 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 927 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 928 clock-names = "tbclk", "fck"; 929 }; 930 931 epwm6: pwm@23060000 { 932 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 933 #pwm-cells = <3>; 934 reg = <0x0 0x23060000 0x0 0x100>; 935 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 936 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 937 clock-names = "tbclk", "fck"; 938 }; 939 940 epwm7: pwm@23070000 { 941 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 942 #pwm-cells = <3>; 943 reg = <0x0 0x23070000 0x0 0x100>; 944 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 945 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 946 clock-names = "tbclk", "fck"; 947 }; 948 949 epwm8: pwm@23080000 { 950 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 951 #pwm-cells = <3>; 952 reg = <0x0 0x23080000 0x0 0x100>; 953 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 954 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 955 clock-names = "tbclk", "fck"; 956 }; 957 958 ecap0: pwm@23100000 { 959 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 960 #pwm-cells = <3>; 961 reg = <0x0 0x23100000 0x0 0x60>; 962 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 963 clocks = <&k3_clks 51 0>; 964 clock-names = "fck"; 965 }; 966 967 ecap1: pwm@23110000 { 968 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 969 #pwm-cells = <3>; 970 reg = <0x0 0x23110000 0x0 0x60>; 971 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 972 clocks = <&k3_clks 52 0>; 973 clock-names = "fck"; 974 }; 975 976 ecap2: pwm@23120000 { 977 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 978 #pwm-cells = <3>; 979 reg = <0x0 0x23120000 0x0 0x60>; 980 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 981 clocks = <&k3_clks 53 0>; 982 clock-names = "fck"; 983 }; 984 985 icssg0: icssg@30000000 { 986 compatible = "ti,am642-icssg"; 987 reg = <0x00 0x30000000 0x00 0x80000>; 988 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 989 #address-cells = <1>; 990 #size-cells = <1>; 991 ranges = <0x0 0x00 0x30000000 0x80000>; 992 993 icssg0_mem: memories@0 { 994 reg = <0x0 0x2000>, 995 <0x2000 0x2000>, 996 <0x10000 0x10000>; 997 reg-names = "dram0", "dram1", "shrdram2"; 998 }; 999 1000 icssg0_cfg: cfg@26000 { 1001 compatible = "ti,pruss-cfg", "syscon"; 1002 reg = <0x26000 0x200>; 1003 #address-cells = <1>; 1004 #size-cells = <1>; 1005 ranges = <0x0 0x26000 0x2000>; 1006 1007 clocks { 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 icssg0_coreclk_mux: coreclk-mux@3c { 1012 reg = <0x3c>; 1013 #clock-cells = <0>; 1014 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1015 <&k3_clks 81 20>; /* icssg0_iclk */ 1016 assigned-clocks = <&icssg0_coreclk_mux>; 1017 assigned-clock-parents = <&k3_clks 81 20>; 1018 }; 1019 1020 icssg0_iepclk_mux: iepclk-mux@30 { 1021 reg = <0x30>; 1022 #clock-cells = <0>; 1023 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1024 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1025 assigned-clocks = <&icssg0_iepclk_mux>; 1026 assigned-clock-parents = <&icssg0_coreclk_mux>; 1027 }; 1028 }; 1029 }; 1030 1031 icssg0_mii_rt: mii-rt@32000 { 1032 compatible = "ti,pruss-mii", "syscon"; 1033 reg = <0x32000 0x100>; 1034 }; 1035 1036 icssg0_mii_g_rt: mii-g-rt@33000 { 1037 compatible = "ti,pruss-mii-g", "syscon"; 1038 reg = <0x33000 0x1000>; 1039 }; 1040 1041 icssg0_intc: interrupt-controller@20000 { 1042 compatible = "ti,icssg-intc"; 1043 reg = <0x20000 0x2000>; 1044 interrupt-controller; 1045 #interrupt-cells = <3>; 1046 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-names = "host_intr0", "host_intr1", 1055 "host_intr2", "host_intr3", 1056 "host_intr4", "host_intr5", 1057 "host_intr6", "host_intr7"; 1058 }; 1059 1060 pru0_0: pru@34000 { 1061 compatible = "ti,am642-pru"; 1062 reg = <0x34000 0x3000>, 1063 <0x22000 0x100>, 1064 <0x22400 0x100>; 1065 reg-names = "iram", "control", "debug"; 1066 firmware-name = "am64x-pru0_0-fw"; 1067 }; 1068 1069 rtu0_0: rtu@4000 { 1070 compatible = "ti,am642-rtu"; 1071 reg = <0x4000 0x2000>, 1072 <0x23000 0x100>, 1073 <0x23400 0x100>; 1074 reg-names = "iram", "control", "debug"; 1075 firmware-name = "am64x-rtu0_0-fw"; 1076 }; 1077 1078 tx_pru0_0: txpru@a000 { 1079 compatible = "ti,am642-tx-pru"; 1080 reg = <0xa000 0x1800>, 1081 <0x25000 0x100>, 1082 <0x25400 0x100>; 1083 reg-names = "iram", "control", "debug"; 1084 firmware-name = "am64x-txpru0_0-fw"; 1085 }; 1086 1087 pru0_1: pru@38000 { 1088 compatible = "ti,am642-pru"; 1089 reg = <0x38000 0x3000>, 1090 <0x24000 0x100>, 1091 <0x24400 0x100>; 1092 reg-names = "iram", "control", "debug"; 1093 firmware-name = "am64x-pru0_1-fw"; 1094 }; 1095 1096 rtu0_1: rtu@6000 { 1097 compatible = "ti,am642-rtu"; 1098 reg = <0x6000 0x2000>, 1099 <0x23800 0x100>, 1100 <0x23c00 0x100>; 1101 reg-names = "iram", "control", "debug"; 1102 firmware-name = "am64x-rtu0_1-fw"; 1103 }; 1104 1105 tx_pru0_1: txpru@c000 { 1106 compatible = "ti,am642-tx-pru"; 1107 reg = <0xc000 0x1800>, 1108 <0x25800 0x100>, 1109 <0x25c00 0x100>; 1110 reg-names = "iram", "control", "debug"; 1111 firmware-name = "am64x-txpru0_1-fw"; 1112 }; 1113 1114 icssg0_mdio: mdio@32400 { 1115 compatible = "ti,davinci_mdio"; 1116 reg = <0x32400 0x100>; 1117 clocks = <&k3_clks 62 3>; 1118 clock-names = "fck"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 bus_freq = <1000000>; 1122 }; 1123 }; 1124 1125 icssg1: icssg@30080000 { 1126 compatible = "ti,am642-icssg"; 1127 reg = <0x00 0x30080000 0x00 0x80000>; 1128 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1129 #address-cells = <1>; 1130 #size-cells = <1>; 1131 ranges = <0x0 0x00 0x30080000 0x80000>; 1132 1133 icssg1_mem: memories@0 { 1134 reg = <0x0 0x2000>, 1135 <0x2000 0x2000>, 1136 <0x10000 0x10000>; 1137 reg-names = "dram0", "dram1", "shrdram2"; 1138 }; 1139 1140 icssg1_cfg: cfg@26000 { 1141 compatible = "ti,pruss-cfg", "syscon"; 1142 reg = <0x26000 0x200>; 1143 #address-cells = <1>; 1144 #size-cells = <1>; 1145 ranges = <0x0 0x26000 0x2000>; 1146 1147 clocks { 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 icssg1_coreclk_mux: coreclk-mux@3c { 1152 reg = <0x3c>; 1153 #clock-cells = <0>; 1154 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1155 <&k3_clks 82 20>; /* icssg1_iclk */ 1156 assigned-clocks = <&icssg1_coreclk_mux>; 1157 assigned-clock-parents = <&k3_clks 82 20>; 1158 }; 1159 1160 icssg1_iepclk_mux: iepclk-mux@30 { 1161 reg = <0x30>; 1162 #clock-cells = <0>; 1163 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1164 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1165 assigned-clocks = <&icssg1_iepclk_mux>; 1166 assigned-clock-parents = <&icssg1_coreclk_mux>; 1167 }; 1168 }; 1169 }; 1170 1171 icssg1_mii_rt: mii-rt@32000 { 1172 compatible = "ti,pruss-mii", "syscon"; 1173 reg = <0x32000 0x100>; 1174 }; 1175 1176 icssg1_mii_g_rt: mii-g-rt@33000 { 1177 compatible = "ti,pruss-mii-g", "syscon"; 1178 reg = <0x33000 0x1000>; 1179 }; 1180 1181 icssg1_intc: interrupt-controller@20000 { 1182 compatible = "ti,icssg-intc"; 1183 reg = <0x20000 0x2000>; 1184 interrupt-controller; 1185 #interrupt-cells = <3>; 1186 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1194 interrupt-names = "host_intr0", "host_intr1", 1195 "host_intr2", "host_intr3", 1196 "host_intr4", "host_intr5", 1197 "host_intr6", "host_intr7"; 1198 }; 1199 1200 pru1_0: pru@34000 { 1201 compatible = "ti,am642-pru"; 1202 reg = <0x34000 0x4000>, 1203 <0x22000 0x100>, 1204 <0x22400 0x100>; 1205 reg-names = "iram", "control", "debug"; 1206 firmware-name = "am64x-pru1_0-fw"; 1207 }; 1208 1209 rtu1_0: rtu@4000 { 1210 compatible = "ti,am642-rtu"; 1211 reg = <0x4000 0x2000>, 1212 <0x23000 0x100>, 1213 <0x23400 0x100>; 1214 reg-names = "iram", "control", "debug"; 1215 firmware-name = "am64x-rtu1_0-fw"; 1216 }; 1217 1218 tx_pru1_0: txpru@a000 { 1219 compatible = "ti,am642-tx-pru"; 1220 reg = <0xa000 0x1800>, 1221 <0x25000 0x100>, 1222 <0x25400 0x100>; 1223 reg-names = "iram", "control", "debug"; 1224 firmware-name = "am64x-txpru1_0-fw"; 1225 }; 1226 1227 pru1_1: pru@38000 { 1228 compatible = "ti,am642-pru"; 1229 reg = <0x38000 0x4000>, 1230 <0x24000 0x100>, 1231 <0x24400 0x100>; 1232 reg-names = "iram", "control", "debug"; 1233 firmware-name = "am64x-pru1_1-fw"; 1234 }; 1235 1236 rtu1_1: rtu@6000 { 1237 compatible = "ti,am642-rtu"; 1238 reg = <0x6000 0x2000>, 1239 <0x23800 0x100>, 1240 <0x23c00 0x100>; 1241 reg-names = "iram", "control", "debug"; 1242 firmware-name = "am64x-rtu1_1-fw"; 1243 }; 1244 1245 tx_pru1_1: txpru@c000 { 1246 compatible = "ti,am642-tx-pru"; 1247 reg = <0xc000 0x1800>, 1248 <0x25800 0x100>, 1249 <0x25c00 0x100>; 1250 reg-names = "iram", "control", "debug"; 1251 firmware-name = "am64x-txpru1_1-fw"; 1252 }; 1253 1254 icssg1_mdio: mdio@32400 { 1255 compatible = "ti,davinci_mdio"; 1256 reg = <0x32400 0x100>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 clocks = <&k3_clks 82 0>; 1260 clock-names = "fck"; 1261 bus_freq = <1000000>; 1262 }; 1263 }; 1264 1265 main_mcan0: can@20701000 { 1266 compatible = "bosch,m_can"; 1267 reg = <0x00 0x20701000 0x00 0x200>, 1268 <0x00 0x20708000 0x00 0x8000>; 1269 reg-names = "m_can", "message_ram"; 1270 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1271 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1272 clock-names = "hclk", "cclk"; 1273 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1275 interrupt-names = "int0", "int1"; 1276 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1277 }; 1278 1279 main_mcan1: can@20711000 { 1280 compatible = "bosch,m_can"; 1281 reg = <0x00 0x20711000 0x00 0x200>, 1282 <0x00 0x20718000 0x00 0x8000>; 1283 reg-names = "m_can", "message_ram"; 1284 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1285 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1286 clock-names = "hclk", "cclk"; 1287 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1289 interrupt-names = "int0", "int1"; 1290 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1291 }; 1292}; 1293