1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM642 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/phy/phy-cadence.h>
9#include <dt-bindings/phy/phy-ti.h>
10
11/ {
12	serdes_refclk: clock-cmnrefclk {
13		#clock-cells = <0>;
14		compatible = "fixed-clock";
15		clock-frequency = <0>;
16	};
17};
18
19&cbass_main {
20	oc_sram: sram@70000000 {
21		compatible = "mmio-sram";
22		reg = <0x00 0x70000000 0x00 0x200000>;
23		#address-cells = <1>;
24		#size-cells = <1>;
25		ranges = <0x0 0x00 0x70000000 0x200000>;
26
27		tfa-sram@1c0000 {
28			reg = <0x1c0000 0x20000>;
29		};
30
31		dmsc-sram@1e0000 {
32			reg = <0x1e0000 0x1c000>;
33		};
34
35		sproxy-sram@1fc000 {
36			reg = <0x1fc000 0x4000>;
37		};
38	};
39
40	main_conf: syscon@43000000 {
41		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42		reg = <0x0 0x43000000 0x0 0x20000>;
43		#address-cells = <1>;
44		#size-cells = <1>;
45		ranges = <0x0 0x0 0x43000000 0x20000>;
46
47		serdes_ln_ctrl: mux-controller {
48			compatible = "mmio-mux";
49			#mux-control-cells = <1>;
50			mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
51		};
52	};
53
54	gic500: interrupt-controller@1800000 {
55		compatible = "arm,gic-v3";
56		#address-cells = <2>;
57		#size-cells = <2>;
58		ranges;
59		#interrupt-cells = <3>;
60		interrupt-controller;
61		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
62		      <0x00 0x01840000 0x00 0xC0000>,	/* GICR */
63		      <0x01 0x00000000 0x00 0x2000>,	/* GICC */
64		      <0x01 0x00010000 0x00 0x1000>,	/* GICH */
65		      <0x01 0x00020000 0x00 0x2000>;	/* GICV */
66		/*
67		 * vcpumntirq:
68		 * virtual CPU interface maintenance interrupt
69		 */
70		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
71
72		gic_its: msi-controller@1820000 {
73			compatible = "arm,gic-v3-its";
74			reg = <0x00 0x01820000 0x00 0x10000>;
75			socionext,synquacer-pre-its = <0x1000000 0x400000>;
76			msi-controller;
77			#msi-cells = <1>;
78		};
79	};
80
81	dmss: bus@48000000 {
82		compatible = "simple-mfd";
83		#address-cells = <2>;
84		#size-cells = <2>;
85		dma-ranges;
86		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
87
88		ti,sci-dev-id = <25>;
89
90		secure_proxy_main: mailbox@4d000000 {
91			compatible = "ti,am654-secure-proxy";
92			#mbox-cells = <1>;
93			reg-names = "target_data", "rt", "scfg";
94			reg = <0x00 0x4d000000 0x00 0x80000>,
95			      <0x00 0x4a600000 0x00 0x80000>,
96			      <0x00 0x4a400000 0x00 0x80000>;
97			interrupt-names = "rx_012";
98			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
99		};
100
101		inta_main_dmss: interrupt-controller@48000000 {
102			compatible = "ti,sci-inta";
103			reg = <0x00 0x48000000 0x00 0x100000>;
104			#interrupt-cells = <0>;
105			interrupt-controller;
106			interrupt-parent = <&gic500>;
107			msi-controller;
108			ti,sci = <&dmsc>;
109			ti,sci-dev-id = <28>;
110			ti,interrupt-ranges = <4 68 36>;
111			ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
112		};
113
114		main_bcdma: dma-controller@485c0100 {
115			compatible = "ti,am64-dmss-bcdma";
116			reg = <0x00 0x485c0100 0x00 0x100>,
117			      <0x00 0x4c000000 0x00 0x20000>,
118			      <0x00 0x4a820000 0x00 0x20000>,
119			      <0x00 0x4aa40000 0x00 0x20000>,
120			      <0x00 0x4bc00000 0x00 0x100000>;
121			reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
122			msi-parent = <&inta_main_dmss>;
123			#dma-cells = <3>;
124
125			ti,sci = <&dmsc>;
126			ti,sci-dev-id = <26>;
127			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
128			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
129			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
130		};
131
132		main_pktdma: dma-controller@485c0000 {
133			compatible = "ti,am64-dmss-pktdma";
134			reg = <0x00 0x485c0000 0x00 0x100>,
135			      <0x00 0x4a800000 0x00 0x20000>,
136			      <0x00 0x4aa00000 0x00 0x40000>,
137			      <0x00 0x4b800000 0x00 0x400000>;
138			reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
139			msi-parent = <&inta_main_dmss>;
140			#dma-cells = <2>;
141
142			ti,sci = <&dmsc>;
143			ti,sci-dev-id = <30>;
144			ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
145						<0x24>, /* CPSW_TX_CHAN */
146						<0x25>, /* SAUL_TX_0_CHAN */
147						<0x26>, /* SAUL_TX_1_CHAN */
148						<0x27>, /* ICSSG_0_TX_CHAN */
149						<0x28>; /* ICSSG_1_TX_CHAN */
150			ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
151						<0x11>, /* RING_CPSW_TX_CHAN */
152						<0x12>, /* RING_SAUL_TX_0_CHAN */
153						<0x13>, /* RING_SAUL_TX_1_CHAN */
154						<0x14>, /* RING_ICSSG_0_TX_CHAN */
155						<0x15>; /* RING_ICSSG_1_TX_CHAN */
156			ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
157						<0x2b>, /* CPSW_RX_CHAN */
158						<0x2d>, /* SAUL_RX_0_CHAN */
159						<0x2f>, /* SAUL_RX_1_CHAN */
160						<0x31>, /* SAUL_RX_2_CHAN */
161						<0x33>, /* SAUL_RX_3_CHAN */
162						<0x35>, /* ICSSG_0_RX_CHAN */
163						<0x37>; /* ICSSG_1_RX_CHAN */
164			ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
165						<0x2c>, /* FLOW_CPSW_RX_CHAN */
166						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
167						<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
168						<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
169						<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
170		};
171	};
172
173	dmsc: system-controller@44043000 {
174		compatible = "ti,k2g-sci";
175		ti,host-id = <12>;
176		mbox-names = "rx", "tx";
177		mboxes = <&secure_proxy_main 12>,
178			<&secure_proxy_main 13>;
179		reg-names = "debug_messages";
180		reg = <0x00 0x44043000 0x00 0xfe0>;
181
182		k3_pds: power-controller {
183			compatible = "ti,sci-pm-domain";
184			#power-domain-cells = <2>;
185		};
186
187		k3_clks: clock-controller {
188			compatible = "ti,k2g-sci-clk";
189			#clock-cells = <2>;
190		};
191
192		k3_reset: reset-controller {
193			compatible = "ti,sci-reset";
194			#reset-cells = <2>;
195		};
196	};
197
198	main_pmx0: pinctrl@f4000 {
199		compatible = "pinctrl-single";
200		reg = <0x00 0xf4000 0x00 0x2d0>;
201		#pinctrl-cells = <1>;
202		pinctrl-single,register-width = <32>;
203		pinctrl-single,function-mask = <0xffffffff>;
204	};
205
206	main_conf: syscon@43000000 {
207		compatible = "syscon", "simple-mfd";
208		reg = <0x00 0x43000000 0x00 0x20000>;
209		#address-cells = <1>;
210		#size-cells = <1>;
211		ranges = <0x00 0x00 0x43000000 0x20000>;
212
213		chipid@14 {
214			compatible = "ti,am654-chipid";
215			reg = <0x00000014 0x4>;
216		};
217
218		phy_gmii_sel: phy@4044 {
219			compatible = "ti,am654-phy-gmii-sel";
220			reg = <0x4044 0x8>;
221			#phy-cells = <1>;
222		};
223
224		epwm_tbclk: clock@4140 {
225			compatible = "ti,am64-epwm-tbclk", "syscon";
226			reg = <0x4130 0x4>;
227			#clock-cells = <1>;
228		};
229	};
230
231	main_timer0: timer@2400000 {
232		compatible = "ti,am654-timer";
233		reg = <0x00 0x2400000 0x00 0x400>;
234		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
235		clocks = <&k3_clks 36 1>;
236		clock-names = "fck";
237		assigned-clocks = <&k3_clks 36 1>;
238		assigned-clock-parents = <&k3_clks 36 2>;
239		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
240		ti,timer-pwm;
241	};
242
243	main_timer1: timer@2410000 {
244		compatible = "ti,am654-timer";
245		reg = <0x00 0x2410000 0x00 0x400>;
246		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
247		clocks = <&k3_clks 37 1>;
248		clock-names = "fck";
249		assigned-clocks = <&k3_clks 37 1>;
250		assigned-clock-parents = <&k3_clks 37 2>;
251		power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
252		ti,timer-pwm;
253	};
254
255	main_timer2: timer@2420000 {
256		compatible = "ti,am654-timer";
257		reg = <0x00 0x2420000 0x00 0x400>;
258		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
259		clocks = <&k3_clks 38 1>;
260		clock-names = "fck";
261		assigned-clocks = <&k3_clks 38 1>;
262		assigned-clock-parents = <&k3_clks 38 2>;
263		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
264		ti,timer-pwm;
265	};
266
267	main_timer3: timer@2430000 {
268		compatible = "ti,am654-timer";
269		reg = <0x00 0x2430000 0x00 0x400>;
270		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
271		clocks = <&k3_clks 39 1>;
272		clock-names = "fck";
273		assigned-clocks = <&k3_clks 39 1>;
274		assigned-clock-parents = <&k3_clks 39 2>;
275		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
276		ti,timer-pwm;
277	};
278
279	main_timer4: timer@2440000 {
280		compatible = "ti,am654-timer";
281		reg = <0x00 0x2440000 0x00 0x400>;
282		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
283		clocks = <&k3_clks 40 1>;
284		clock-names = "fck";
285		assigned-clocks = <&k3_clks 40 1>;
286		assigned-clock-parents = <&k3_clks 40 2>;
287		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
288		ti,timer-pwm;
289	};
290
291	main_timer5: timer@2450000 {
292		compatible = "ti,am654-timer";
293		reg = <0x00 0x2450000 0x00 0x400>;
294		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
295		clocks = <&k3_clks 41 1>;
296		clock-names = "fck";
297		assigned-clocks = <&k3_clks 41 1>;
298		assigned-clock-parents = <&k3_clks 41 2>;
299		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
300		ti,timer-pwm;
301	};
302
303	main_timer6: timer@2460000 {
304		compatible = "ti,am654-timer";
305		reg = <0x00 0x2460000 0x00 0x400>;
306		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
307		clocks = <&k3_clks 42 1>;
308		clock-names = "fck";
309		assigned-clocks = <&k3_clks 42 1>;
310		assigned-clock-parents = <&k3_clks 42 2>;
311		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
312		ti,timer-pwm;
313	};
314
315	main_timer7: timer@2470000 {
316		compatible = "ti,am654-timer";
317		reg = <0x00 0x2470000 0x00 0x400>;
318		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
319		clocks = <&k3_clks 43 1>;
320		clock-names = "fck";
321		assigned-clocks = <&k3_clks 43 1>;
322		assigned-clock-parents = <&k3_clks 43 2>;
323		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
324		ti,timer-pwm;
325	};
326
327	main_timer8: timer@2480000 {
328		compatible = "ti,am654-timer";
329		reg = <0x00 0x2480000 0x00 0x400>;
330		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
331		clocks = <&k3_clks 44 1>;
332		clock-names = "fck";
333		assigned-clocks = <&k3_clks 44 1>;
334		assigned-clock-parents = <&k3_clks 44 2>;
335		power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
336		ti,timer-pwm;
337	};
338
339	main_timer9: timer@2490000 {
340		compatible = "ti,am654-timer";
341		reg = <0x00 0x2490000 0x00 0x400>;
342		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
343		clocks = <&k3_clks 45 1>;
344		clock-names = "fck";
345		assigned-clocks = <&k3_clks 45 1>;
346		assigned-clock-parents = <&k3_clks 45 2>;
347		power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
348		ti,timer-pwm;
349	};
350
351	main_timer10: timer@24a0000 {
352		compatible = "ti,am654-timer";
353		reg = <0x00 0x24a0000 0x00 0x400>;
354		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
355		clocks = <&k3_clks 46 1>;
356		clock-names = "fck";
357		assigned-clocks = <&k3_clks 46 1>;
358		assigned-clock-parents = <&k3_clks 46 2>;
359		power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>;
360		ti,timer-pwm;
361	};
362
363	main_timer11: timer@24b0000 {
364		compatible = "ti,am654-timer";
365		reg = <0x00 0x24b0000 0x00 0x400>;
366		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
367		clocks = <&k3_clks 47 1>;
368		clock-names = "fck";
369		assigned-clocks = <&k3_clks 47 1>;
370		assigned-clock-parents = <&k3_clks 47 2>;
371		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
372		ti,timer-pwm;
373	};
374
375	main_esm: esm@420000 {
376		compatible = "ti,j721e-esm";
377		reg = <0x00 0x420000 0x00 0x1000>;
378		ti,esm-pins = <160>, <161>;
379	};
380
381	main_uart0: serial@2800000 {
382		compatible = "ti,am64-uart", "ti,am654-uart";
383		reg = <0x00 0x02800000 0x00 0x100>;
384		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
385		clock-frequency = <48000000>;
386		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
387		clocks = <&k3_clks 146 0>;
388		clock-names = "fclk";
389		status = "disabled";
390	};
391
392	main_uart1: serial@2810000 {
393		compatible = "ti,am64-uart", "ti,am654-uart";
394		reg = <0x00 0x02810000 0x00 0x100>;
395		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
396		clock-frequency = <48000000>;
397		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
398		clocks = <&k3_clks 152 0>;
399		clock-names = "fclk";
400		status = "disabled";
401	};
402
403	main_uart2: serial@2820000 {
404		compatible = "ti,am64-uart", "ti,am654-uart";
405		reg = <0x00 0x02820000 0x00 0x100>;
406		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
407		clock-frequency = <48000000>;
408		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
409		clocks = <&k3_clks 153 0>;
410		clock-names = "fclk";
411		status = "disabled";
412	};
413
414	main_uart3: serial@2830000 {
415		compatible = "ti,am64-uart", "ti,am654-uart";
416		reg = <0x00 0x02830000 0x00 0x100>;
417		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
418		clock-frequency = <48000000>;
419		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
420		clocks = <&k3_clks 154 0>;
421		clock-names = "fclk";
422		status = "disabled";
423	};
424
425	main_uart4: serial@2840000 {
426		compatible = "ti,am64-uart", "ti,am654-uart";
427		reg = <0x00 0x02840000 0x00 0x100>;
428		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
429		clock-frequency = <48000000>;
430		power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
431		clocks = <&k3_clks 155 0>;
432		clock-names = "fclk";
433		status = "disabled";
434	};
435
436	main_uart5: serial@2850000 {
437		compatible = "ti,am64-uart", "ti,am654-uart";
438		reg = <0x00 0x02850000 0x00 0x100>;
439		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
440		clock-frequency = <48000000>;
441		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
442		clocks = <&k3_clks 156 0>;
443		clock-names = "fclk";
444		status = "disabled";
445	};
446
447	main_uart6: serial@2860000 {
448		compatible = "ti,am64-uart", "ti,am654-uart";
449		reg = <0x00 0x02860000 0x00 0x100>;
450		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
451		clock-frequency = <48000000>;
452		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
453		clocks = <&k3_clks 158 0>;
454		clock-names = "fclk";
455		status = "disabled";
456	};
457
458	main_i2c0: i2c@20000000 {
459		compatible = "ti,am64-i2c", "ti,omap4-i2c";
460		reg = <0x00 0x20000000 0x00 0x100>;
461		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
462		#address-cells = <1>;
463		#size-cells = <0>;
464		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
465		clocks = <&k3_clks 102 2>;
466		clock-names = "fck";
467		status = "disabled";
468	};
469
470	main_i2c1: i2c@20010000 {
471		compatible = "ti,am64-i2c", "ti,omap4-i2c";
472		reg = <0x00 0x20010000 0x00 0x100>;
473		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
474		#address-cells = <1>;
475		#size-cells = <0>;
476		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
477		clocks = <&k3_clks 103 2>;
478		clock-names = "fck";
479		status = "disabled";
480	};
481
482	main_i2c2: i2c@20020000 {
483		compatible = "ti,am64-i2c", "ti,omap4-i2c";
484		reg = <0x00 0x20020000 0x00 0x100>;
485		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
486		#address-cells = <1>;
487		#size-cells = <0>;
488		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
489		clocks = <&k3_clks 104 2>;
490		clock-names = "fck";
491		status = "disabled";
492	};
493
494	main_i2c3: i2c@20030000 {
495		compatible = "ti,am64-i2c", "ti,omap4-i2c";
496		reg = <0x00 0x20030000 0x00 0x100>;
497		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
498		#address-cells = <1>;
499		#size-cells = <0>;
500		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
501		clocks = <&k3_clks 105 2>;
502		clock-names = "fck";
503		status = "disabled";
504	};
505
506	main_spi0: spi@20100000 {
507		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
508		reg = <0x00 0x20100000 0x00 0x400>;
509		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
510		#address-cells = <1>;
511		#size-cells = <0>;
512		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
513		clocks = <&k3_clks 141 0>;
514		dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
515		dma-names = "tx0", "rx0";
516		status = "disabled";
517	};
518
519	main_spi1: spi@20110000 {
520		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
521		reg = <0x00 0x20110000 0x00 0x400>;
522		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
523		#address-cells = <1>;
524		#size-cells = <0>;
525		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
526		clocks = <&k3_clks 142 0>;
527		status = "disabled";
528	};
529
530	main_spi2: spi@20120000 {
531		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
532		reg = <0x00 0x20120000 0x00 0x400>;
533		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
534		#address-cells = <1>;
535		#size-cells = <0>;
536		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
537		clocks = <&k3_clks 143 0>;
538		status = "disabled";
539	};
540
541	main_spi3: spi@20130000 {
542		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
543		reg = <0x00 0x20130000 0x00 0x400>;
544		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
545		#address-cells = <1>;
546		#size-cells = <0>;
547		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
548		clocks = <&k3_clks 144 0>;
549		status = "disabled";
550	};
551
552	main_spi4: spi@20140000 {
553		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
554		reg = <0x00 0x20140000 0x00 0x400>;
555		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
556		#address-cells = <1>;
557		#size-cells = <0>;
558		power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
559		clocks = <&k3_clks 145 0>;
560		status = "disabled";
561	};
562
563	main_gpio_intr: interrupt-controller@a00000 {
564		compatible = "ti,sci-intr";
565		reg = <0x00 0x00a00000 0x00 0x800>;
566		ti,intr-trigger-type = <1>;
567		interrupt-controller;
568		interrupt-parent = <&gic500>;
569		#interrupt-cells = <1>;
570		ti,sci = <&dmsc>;
571		ti,sci-dev-id = <3>;
572		ti,interrupt-ranges = <0 32 16>;
573	};
574
575	main_gpio0: gpio@600000 {
576		compatible = "ti,am64-gpio", "ti,keystone-gpio";
577		reg = <0x0 0x00600000 0x0 0x100>;
578		gpio-controller;
579		#gpio-cells = <2>;
580		interrupt-parent = <&main_gpio_intr>;
581		interrupts = <190>, <191>, <192>,
582			     <193>, <194>, <195>;
583		interrupt-controller;
584		#interrupt-cells = <2>;
585		ti,ngpio = <87>;
586		ti,davinci-gpio-unbanked = <0>;
587		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
588		clocks = <&k3_clks 77 0>;
589		clock-names = "gpio";
590	};
591
592	main_gpio1: gpio@601000 {
593		compatible = "ti,am64-gpio", "ti,keystone-gpio";
594		reg = <0x0 0x00601000 0x0 0x100>;
595		gpio-controller;
596		#gpio-cells = <2>;
597		interrupt-parent = <&main_gpio_intr>;
598		interrupts = <180>, <181>, <182>,
599			     <183>, <184>, <185>;
600		interrupt-controller;
601		#interrupt-cells = <2>;
602		ti,ngpio = <88>;
603		ti,davinci-gpio-unbanked = <0>;
604		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
605		clocks = <&k3_clks 78 0>;
606		clock-names = "gpio";
607	};
608
609	sdhci0: mmc@fa10000 {
610		compatible = "ti,am64-sdhci-8bit";
611		reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
612		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
613		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
614		clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
615		clock-names = "clk_ahb", "clk_xin";
616		mmc-ddr-1_8v;
617		mmc-hs200-1_8v;
618		ti,trm-icp = <0x2>;
619		ti,otap-del-sel-legacy = <0x0>;
620		ti,otap-del-sel-mmc-hs = <0x0>;
621		ti,otap-del-sel-ddr52 = <0x6>;
622		ti,otap-del-sel-hs200 = <0x7>;
623	};
624
625	sdhci1: mmc@fa00000 {
626		compatible = "ti,am64-sdhci-4bit";
627		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
628		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
629		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
630		clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
631		clock-names = "clk_ahb", "clk_xin";
632		ti,trm-icp = <0x2>;
633		ti,otap-del-sel-legacy = <0x0>;
634		ti,otap-del-sel-sd-hs = <0xf>;
635		ti,otap-del-sel-sdr12 = <0xf>;
636		ti,otap-del-sel-sdr25 = <0xf>;
637		ti,otap-del-sel-sdr50 = <0xc>;
638		ti,otap-del-sel-sdr104 = <0x6>;
639		ti,otap-del-sel-ddr50 = <0x9>;
640		ti,clkbuf-sel = <0x7>;
641	};
642
643	cpsw3g: ethernet@8000000 {
644		compatible = "ti,am642-cpsw-nuss";
645		#address-cells = <2>;
646		#size-cells = <2>;
647		reg = <0x0 0x8000000 0x0 0x200000>;
648		reg-names = "cpsw_nuss";
649		ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
650		clocks = <&k3_clks 13 0>;
651		assigned-clocks = <&k3_clks 13 1>;
652		assigned-clock-parents = <&k3_clks 13 9>;
653		clock-names = "fck";
654		power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
655
656		dmas = <&main_pktdma 0xC500 15>,
657		       <&main_pktdma 0xC501 15>,
658		       <&main_pktdma 0xC502 15>,
659		       <&main_pktdma 0xC503 15>,
660		       <&main_pktdma 0xC504 15>,
661		       <&main_pktdma 0xC505 15>,
662		       <&main_pktdma 0xC506 15>,
663		       <&main_pktdma 0xC507 15>,
664		       <&main_pktdma 0x4500 15>;
665		dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
666			    "tx7", "rx";
667
668		ethernet-ports {
669			#address-cells = <1>;
670			#size-cells = <0>;
671
672			cpsw_port1: port@1 {
673				reg = <1>;
674				ti,mac-only;
675				label = "port1";
676				phys = <&phy_gmii_sel 1>;
677				mac-address = [00 00 00 00 00 00];
678				ti,syscon-efuse = <&main_conf 0x200>;
679			};
680
681			cpsw_port2: port@2 {
682				reg = <2>;
683				ti,mac-only;
684				label = "port2";
685				phys = <&phy_gmii_sel 2>;
686				mac-address = [00 00 00 00 00 00];
687			};
688		};
689
690		cpsw3g_mdio: mdio@f00 {
691			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
692			reg = <0x0 0xf00 0x0 0x100>;
693			#address-cells = <1>;
694			#size-cells = <0>;
695			clocks = <&k3_clks 13 0>;
696			clock-names = "fck";
697			bus_freq = <1000000>;
698			status = "disabled";
699		};
700
701		cpts@3d000 {
702			compatible = "ti,j721e-cpts";
703			reg = <0x0 0x3d000 0x0 0x400>;
704			clocks = <&k3_clks 13 1>;
705			clock-names = "cpts";
706			interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
707			interrupt-names = "cpts";
708			ti,cpts-ext-ts-inputs = <4>;
709			ti,cpts-periodic-outputs = <2>;
710		};
711	};
712
713	main_cpts0: cpts@39000000 {
714		compatible = "ti,j721e-cpts";
715		reg = <0x0 0x39000000 0x0 0x400>;
716		reg-names = "cpts";
717		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
718		clocks = <&k3_clks 84 0>;
719		clock-names = "cpts";
720		assigned-clocks = <&k3_clks 84 0>;
721		assigned-clock-parents = <&k3_clks 84 8>;
722		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
723		interrupt-names = "cpts";
724		ti,cpts-periodic-outputs = <6>;
725		ti,cpts-ext-ts-inputs = <8>;
726	};
727
728	timesync_router: pinctrl@a40000 {
729		compatible = "pinctrl-single";
730		reg = <0x0 0xa40000 0x0 0x800>;
731		#pinctrl-cells = <1>;
732		pinctrl-single,register-width = <32>;
733		pinctrl-single,function-mask = <0x000107ff>;
734	};
735
736	usbss0: cdns-usb@f900000{
737		compatible = "ti,am64-usb";
738		reg = <0x00 0xf900000 0x00 0x100>;
739		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
740		clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
741		clock-names = "ref", "lpm";
742		assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
743		assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
744		#address-cells = <2>;
745		#size-cells = <2>;
746		ranges;
747		usb0: usb@f400000{
748			compatible = "cdns,usb3";
749			reg = <0x00 0xf400000 0x00 0x10000>,
750			      <0x00 0xf410000 0x00 0x10000>,
751			      <0x00 0xf420000 0x00 0x10000>;
752			reg-names = "otg",
753				    "xhci",
754				    "dev";
755			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
756				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
757				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
758			interrupt-names = "host",
759					  "peripheral",
760					  "otg";
761			maximum-speed = "super-speed";
762			dr_mode = "otg";
763		};
764	};
765
766	tscadc0: tscadc@28001000 {
767		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
768		reg = <0x00 0x28001000 0x00 0x1000>;
769		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
770		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
771		clocks = <&k3_clks 0 0>;
772		assigned-clocks = <&k3_clks 0 0>;
773		assigned-clock-parents = <&k3_clks 0 3>;
774		assigned-clock-rates = <60000000>;
775		clock-names = "fck";
776
777		adc {
778			#io-channel-cells = <1>;
779			compatible = "ti,am654-adc", "ti,am3359-adc";
780		};
781	};
782
783	fss: bus@fc00000 {
784		compatible = "simple-bus";
785		reg = <0x00 0x0fc00000 0x00 0x70000>;
786		#address-cells = <2>;
787		#size-cells = <2>;
788		ranges;
789
790		ospi0: spi@fc40000 {
791			compatible = "ti,am654-ospi", "cdns,qspi-nor";
792			reg = <0x00 0x0fc40000 0x00 0x100>,
793			      <0x05 0x00000000 0x01 0x00000000>;
794			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
795			cdns,fifo-depth = <256>;
796			cdns,fifo-width = <4>;
797			cdns,trigger-address = <0x0>;
798			#address-cells = <0x1>;
799			#size-cells = <0x0>;
800			clocks = <&k3_clks 75 6>;
801			assigned-clocks = <&k3_clks 75 6>;
802			assigned-clock-parents = <&k3_clks 75 7>;
803			assigned-clock-rates = <166666666>;
804			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
805		};
806	};
807
808	hwspinlock: spinlock@2a000000 {
809		compatible = "ti,am64-hwspinlock";
810		reg = <0x00 0x2a000000 0x00 0x1000>;
811		#hwlock-cells = <1>;
812	};
813
814	mailbox0_cluster2: mailbox@29020000 {
815		compatible = "ti,am64-mailbox";
816		reg = <0x00 0x29020000 0x00 0x200>;
817		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
818			     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
819		#mbox-cells = <1>;
820		ti,mbox-num-users = <4>;
821		ti,mbox-num-fifos = <16>;
822		status = "disabled";
823	};
824
825	mailbox0_cluster3: mailbox@29030000 {
826		compatible = "ti,am64-mailbox";
827		reg = <0x00 0x29030000 0x00 0x200>;
828		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
829			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
830		#mbox-cells = <1>;
831		ti,mbox-num-users = <4>;
832		ti,mbox-num-fifos = <16>;
833		status = "disabled";
834	};
835
836	mailbox0_cluster4: mailbox@29040000 {
837		compatible = "ti,am64-mailbox";
838		reg = <0x00 0x29040000 0x00 0x200>;
839		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
840			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
841		#mbox-cells = <1>;
842		ti,mbox-num-users = <4>;
843		ti,mbox-num-fifos = <16>;
844		status = "disabled";
845	};
846
847	mailbox0_cluster5: mailbox@29050000 {
848		compatible = "ti,am64-mailbox";
849		reg = <0x00 0x29050000 0x00 0x200>;
850		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
851			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
852		#mbox-cells = <1>;
853		ti,mbox-num-users = <4>;
854		ti,mbox-num-fifos = <16>;
855		status = "disabled";
856	};
857
858	mailbox0_cluster6: mailbox@29060000 {
859		compatible = "ti,am64-mailbox";
860		reg = <0x00 0x29060000 0x00 0x200>;
861		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
862		#mbox-cells = <1>;
863		ti,mbox-num-users = <4>;
864		ti,mbox-num-fifos = <16>;
865		status = "disabled";
866	};
867
868	mailbox0_cluster7: mailbox@29070000 {
869		compatible = "ti,am64-mailbox";
870		reg = <0x00 0x29070000 0x00 0x200>;
871		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
872		#mbox-cells = <1>;
873		ti,mbox-num-users = <4>;
874		ti,mbox-num-fifos = <16>;
875		status = "disabled";
876	};
877
878	main_r5fss0: r5fss@78000000 {
879		compatible = "ti,am64-r5fss";
880		ti,cluster-mode = <0>;
881		#address-cells = <1>;
882		#size-cells = <1>;
883		ranges = <0x78000000 0x00 0x78000000 0x10000>,
884			 <0x78100000 0x00 0x78100000 0x10000>,
885			 <0x78200000 0x00 0x78200000 0x08000>,
886			 <0x78300000 0x00 0x78300000 0x08000>;
887		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
888
889		main_r5fss0_core0: r5f@78000000 {
890			compatible = "ti,am64-r5f";
891			reg = <0x78000000 0x00010000>,
892			      <0x78100000 0x00010000>;
893			reg-names = "atcm", "btcm";
894			ti,sci = <&dmsc>;
895			ti,sci-dev-id = <121>;
896			ti,sci-proc-ids = <0x01 0xff>;
897			resets = <&k3_reset 121 1>;
898			firmware-name = "am64-main-r5f0_0-fw";
899			ti,atcm-enable = <1>;
900			ti,btcm-enable = <1>;
901			ti,loczrama = <1>;
902		};
903
904		main_r5fss0_core1: r5f@78200000 {
905			compatible = "ti,am64-r5f";
906			reg = <0x78200000 0x00008000>,
907			      <0x78300000 0x00008000>;
908			reg-names = "atcm", "btcm";
909			ti,sci = <&dmsc>;
910			ti,sci-dev-id = <122>;
911			ti,sci-proc-ids = <0x02 0xff>;
912			resets = <&k3_reset 122 1>;
913			firmware-name = "am64-main-r5f0_1-fw";
914			ti,atcm-enable = <1>;
915			ti,btcm-enable = <1>;
916			ti,loczrama = <1>;
917		};
918	};
919
920	main_r5fss1: r5fss@78400000 {
921		compatible = "ti,am64-r5fss";
922		ti,cluster-mode = <0>;
923		#address-cells = <1>;
924		#size-cells = <1>;
925		ranges = <0x78400000 0x00 0x78400000 0x10000>,
926			 <0x78500000 0x00 0x78500000 0x10000>,
927			 <0x78600000 0x00 0x78600000 0x08000>,
928			 <0x78700000 0x00 0x78700000 0x08000>;
929		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
930
931		main_r5fss1_core0: r5f@78400000 {
932			compatible = "ti,am64-r5f";
933			reg = <0x78400000 0x00010000>,
934			      <0x78500000 0x00010000>;
935			reg-names = "atcm", "btcm";
936			ti,sci = <&dmsc>;
937			ti,sci-dev-id = <123>;
938			ti,sci-proc-ids = <0x06 0xff>;
939			resets = <&k3_reset 123 1>;
940			firmware-name = "am64-main-r5f1_0-fw";
941			ti,atcm-enable = <1>;
942			ti,btcm-enable = <1>;
943			ti,loczrama = <1>;
944		};
945
946		main_r5fss1_core1: r5f@78600000 {
947			compatible = "ti,am64-r5f";
948			reg = <0x78600000 0x00008000>,
949			      <0x78700000 0x00008000>;
950			reg-names = "atcm", "btcm";
951			ti,sci = <&dmsc>;
952			ti,sci-dev-id = <124>;
953			ti,sci-proc-ids = <0x07 0xff>;
954			resets = <&k3_reset 124 1>;
955			firmware-name = "am64-main-r5f1_1-fw";
956			ti,atcm-enable = <1>;
957			ti,btcm-enable = <1>;
958			ti,loczrama = <1>;
959		};
960	};
961
962	serdes_wiz0: wiz@f000000 {
963		compatible = "ti,am64-wiz-10g";
964		#address-cells = <1>;
965		#size-cells = <1>;
966		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
967		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
968		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
969		num-lanes = <1>;
970		#reset-cells = <1>;
971		#clock-cells = <1>;
972		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
973
974		assigned-clocks = <&k3_clks 162 1>;
975		assigned-clock-parents = <&k3_clks 162 5>;
976
977		serdes0: serdes@f000000 {
978			compatible = "ti,j721e-serdes-10g";
979			reg = <0x0f000000 0x00010000>;
980			reg-names = "torrent_phy";
981			resets = <&serdes_wiz0 0>;
982			reset-names = "torrent_reset";
983			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
984				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
985			clock-names = "refclk", "phy_en_refclk";
986			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
987					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
988					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
989			assigned-clock-parents = <&k3_clks 162 1>,
990						 <&k3_clks 162 1>,
991						 <&k3_clks 162 1>;
992			#address-cells = <1>;
993			#size-cells = <0>;
994			#clock-cells = <1>;
995		};
996	};
997
998	pcie0_rc: pcie@f102000 {
999		compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
1000		reg = <0x00 0x0f102000 0x00 0x1000>,
1001		      <0x00 0x0f100000 0x00 0x400>,
1002		      <0x00 0x0d000000 0x00 0x00800000>,
1003		      <0x00 0x68000000 0x00 0x00001000>;
1004		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1005		interrupt-names = "link_state";
1006		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1007		device_type = "pci";
1008		ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1009		max-link-speed = <2>;
1010		num-lanes = <1>;
1011		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
1012		clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
1013		clock-names = "fck", "pcie_refclk";
1014		#address-cells = <3>;
1015		#size-cells = <2>;
1016		bus-range = <0x0 0xff>;
1017		cdns,no-bar-match-nbits = <64>;
1018		vendor-id = <0x104c>;
1019		device-id = <0xb010>;
1020		msi-map = <0x0 &gic_its 0x0 0x10000>;
1021		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
1022			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
1023		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
1024		status = "disabled";
1025	};
1026
1027	pcie0_ep: pcie-ep@f102000 {
1028		compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
1029		reg = <0x00 0x0f102000 0x00 0x1000>,
1030		      <0x00 0x0f100000 0x00 0x400>,
1031		      <0x00 0x0d000000 0x00 0x00800000>,
1032		      <0x00 0x68000000 0x00 0x08000000>;
1033		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
1034		interrupt-names = "link_state";
1035		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1036		ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1037		max-link-speed = <2>;
1038		num-lanes = <1>;
1039		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
1040		clocks = <&k3_clks 114 0>;
1041		clock-names = "fck";
1042		max-functions = /bits/ 8 <1>;
1043		status = "disabled";
1044	};
1045
1046	epwm0: pwm@23000000 {
1047		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1048		#pwm-cells = <3>;
1049		reg = <0x0 0x23000000 0x0 0x100>;
1050		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
1051		clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
1052		clock-names = "tbclk", "fck";
1053		status = "disabled";
1054	};
1055
1056	epwm1: pwm@23010000 {
1057		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1058		#pwm-cells = <3>;
1059		reg = <0x0 0x23010000 0x0 0x100>;
1060		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
1061		clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
1062		clock-names = "tbclk", "fck";
1063		status = "disabled";
1064	};
1065
1066	epwm2: pwm@23020000 {
1067		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1068		#pwm-cells = <3>;
1069		reg = <0x0 0x23020000 0x0 0x100>;
1070		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
1071		clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
1072		clock-names = "tbclk", "fck";
1073		status = "disabled";
1074	};
1075
1076	epwm3: pwm@23030000 {
1077		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1078		#pwm-cells = <3>;
1079		reg = <0x0 0x23030000 0x0 0x100>;
1080		power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
1081		clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
1082		clock-names = "tbclk", "fck";
1083		status = "disabled";
1084	};
1085
1086	epwm4: pwm@23040000 {
1087		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1088		#pwm-cells = <3>;
1089		reg = <0x0 0x23040000 0x0 0x100>;
1090		power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
1091		clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
1092		clock-names = "tbclk", "fck";
1093		status = "disabled";
1094	};
1095
1096	epwm5: pwm@23050000 {
1097		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1098		#pwm-cells = <3>;
1099		reg = <0x0 0x23050000 0x0 0x100>;
1100		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1101		clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
1102		clock-names = "tbclk", "fck";
1103		status = "disabled";
1104	};
1105
1106	epwm6: pwm@23060000 {
1107		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1108		#pwm-cells = <3>;
1109		reg = <0x0 0x23060000 0x0 0x100>;
1110		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1111		clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
1112		clock-names = "tbclk", "fck";
1113		status = "disabled";
1114	};
1115
1116	epwm7: pwm@23070000 {
1117		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1118		#pwm-cells = <3>;
1119		reg = <0x0 0x23070000 0x0 0x100>;
1120		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1121		clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
1122		clock-names = "tbclk", "fck";
1123		status = "disabled";
1124	};
1125
1126	epwm8: pwm@23080000 {
1127		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
1128		#pwm-cells = <3>;
1129		reg = <0x0 0x23080000 0x0 0x100>;
1130		power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
1131		clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
1132		clock-names = "tbclk", "fck";
1133		status = "disabled";
1134	};
1135
1136	ecap0: pwm@23100000 {
1137		compatible = "ti,am64-ecap", "ti,am3352-ecap";
1138		#pwm-cells = <3>;
1139		reg = <0x0 0x23100000 0x0 0x60>;
1140		power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1141		clocks = <&k3_clks 51 0>;
1142		clock-names = "fck";
1143		status = "disabled";
1144	};
1145
1146	ecap1: pwm@23110000 {
1147		compatible = "ti,am64-ecap", "ti,am3352-ecap";
1148		#pwm-cells = <3>;
1149		reg = <0x0 0x23110000 0x0 0x60>;
1150		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1151		clocks = <&k3_clks 52 0>;
1152		clock-names = "fck";
1153		status = "disabled";
1154	};
1155
1156	ecap2: pwm@23120000 {
1157		compatible = "ti,am64-ecap", "ti,am3352-ecap";
1158		#pwm-cells = <3>;
1159		reg = <0x0 0x23120000 0x0 0x60>;
1160		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1161		clocks = <&k3_clks 53 0>;
1162		clock-names = "fck";
1163		status = "disabled";
1164	};
1165
1166	main_rti0: watchdog@e000000 {
1167			compatible = "ti,j7-rti-wdt";
1168			reg = <0x00 0xe000000 0x00 0x100>;
1169			clocks = <&k3_clks 125 0>;
1170			power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
1171			assigned-clocks = <&k3_clks 125 0>;
1172			assigned-clock-parents = <&k3_clks 125 2>;
1173	};
1174
1175	main_rti1: watchdog@e010000 {
1176			compatible = "ti,j7-rti-wdt";
1177			reg = <0x00 0xe010000 0x00 0x100>;
1178			clocks = <&k3_clks 126 0>;
1179			power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
1180			assigned-clocks = <&k3_clks 126 0>;
1181			assigned-clock-parents = <&k3_clks 126 2>;
1182	};
1183
1184	icssg0: icssg@30000000 {
1185		compatible = "ti,am642-icssg";
1186		reg = <0x00 0x30000000 0x00 0x80000>;
1187		power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
1188		#address-cells = <1>;
1189		#size-cells = <1>;
1190		ranges = <0x0 0x00 0x30000000 0x80000>;
1191
1192		icssg0_mem: memories@0 {
1193			reg = <0x0 0x2000>,
1194			      <0x2000 0x2000>,
1195			      <0x10000 0x10000>;
1196			reg-names = "dram0", "dram1", "shrdram2";
1197		};
1198
1199		icssg0_cfg: cfg@26000 {
1200			compatible = "ti,pruss-cfg", "syscon";
1201			reg = <0x26000 0x200>;
1202			#address-cells = <1>;
1203			#size-cells = <1>;
1204			ranges = <0x0 0x26000 0x2000>;
1205
1206			clocks {
1207				#address-cells = <1>;
1208				#size-cells = <0>;
1209
1210				icssg0_coreclk_mux: coreclk-mux@3c {
1211					reg = <0x3c>;
1212					#clock-cells = <0>;
1213					clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
1214						 <&k3_clks 81 20>; /* icssg0_iclk */
1215					assigned-clocks = <&icssg0_coreclk_mux>;
1216					assigned-clock-parents = <&k3_clks 81 20>;
1217				};
1218
1219				icssg0_iepclk_mux: iepclk-mux@30 {
1220					reg = <0x30>;
1221					#clock-cells = <0>;
1222					clocks = <&k3_clks 81 3>,	/* icssg0_iep_clk */
1223						 <&icssg0_coreclk_mux>;	/* icssg0_coreclk_mux */
1224					assigned-clocks = <&icssg0_iepclk_mux>;
1225					assigned-clock-parents = <&icssg0_coreclk_mux>;
1226				};
1227			};
1228		};
1229
1230		icssg0_mii_rt: mii-rt@32000 {
1231			compatible = "ti,pruss-mii", "syscon";
1232			reg = <0x32000 0x100>;
1233		};
1234
1235		icssg0_mii_g_rt: mii-g-rt@33000 {
1236			compatible = "ti,pruss-mii-g", "syscon";
1237			reg = <0x33000 0x1000>;
1238		};
1239
1240		icssg0_intc: interrupt-controller@20000 {
1241			compatible = "ti,icssg-intc";
1242			reg = <0x20000 0x2000>;
1243			interrupt-controller;
1244			#interrupt-cells = <3>;
1245			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1246				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1247				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1248				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1249				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1250				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1251				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1252				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1253			interrupt-names = "host_intr0", "host_intr1",
1254					  "host_intr2", "host_intr3",
1255					  "host_intr4", "host_intr5",
1256					  "host_intr6", "host_intr7";
1257		};
1258
1259		pru0_0: pru@34000 {
1260			compatible = "ti,am642-pru";
1261			reg = <0x34000 0x3000>,
1262			      <0x22000 0x100>,
1263			      <0x22400 0x100>;
1264			reg-names = "iram", "control", "debug";
1265			firmware-name = "am64x-pru0_0-fw";
1266		};
1267
1268		rtu0_0: rtu@4000 {
1269			compatible = "ti,am642-rtu";
1270			reg = <0x4000 0x2000>,
1271			      <0x23000 0x100>,
1272			      <0x23400 0x100>;
1273			reg-names = "iram", "control", "debug";
1274			firmware-name = "am64x-rtu0_0-fw";
1275		};
1276
1277		tx_pru0_0: txpru@a000 {
1278			compatible = "ti,am642-tx-pru";
1279			reg = <0xa000 0x1800>,
1280			      <0x25000 0x100>,
1281			      <0x25400 0x100>;
1282			reg-names = "iram", "control", "debug";
1283			firmware-name = "am64x-txpru0_0-fw";
1284		};
1285
1286		pru0_1: pru@38000 {
1287			compatible = "ti,am642-pru";
1288			reg = <0x38000 0x3000>,
1289			      <0x24000 0x100>,
1290			      <0x24400 0x100>;
1291			reg-names = "iram", "control", "debug";
1292			firmware-name = "am64x-pru0_1-fw";
1293		};
1294
1295		rtu0_1: rtu@6000 {
1296			compatible = "ti,am642-rtu";
1297			reg = <0x6000 0x2000>,
1298			      <0x23800 0x100>,
1299			      <0x23c00 0x100>;
1300			reg-names = "iram", "control", "debug";
1301			firmware-name = "am64x-rtu0_1-fw";
1302		};
1303
1304		tx_pru0_1: txpru@c000 {
1305			compatible = "ti,am642-tx-pru";
1306			reg = <0xc000 0x1800>,
1307			      <0x25800 0x100>,
1308			      <0x25c00 0x100>;
1309			reg-names = "iram", "control", "debug";
1310			firmware-name = "am64x-txpru0_1-fw";
1311		};
1312
1313		icssg0_mdio: mdio@32400 {
1314			compatible = "ti,davinci_mdio";
1315			reg = <0x32400 0x100>;
1316			clocks = <&k3_clks 62 3>;
1317			clock-names = "fck";
1318			#address-cells = <1>;
1319			#size-cells = <0>;
1320			bus_freq = <1000000>;
1321			status = "disabled";
1322		};
1323	};
1324
1325	icssg1: icssg@30080000 {
1326		compatible = "ti,am642-icssg";
1327		reg = <0x00 0x30080000 0x00 0x80000>;
1328		power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
1329		#address-cells = <1>;
1330		#size-cells = <1>;
1331		ranges = <0x0 0x00 0x30080000 0x80000>;
1332
1333		icssg1_mem: memories@0 {
1334			reg = <0x0 0x2000>,
1335			      <0x2000 0x2000>,
1336			      <0x10000 0x10000>;
1337			reg-names = "dram0", "dram1", "shrdram2";
1338		};
1339
1340		icssg1_cfg: cfg@26000 {
1341			compatible = "ti,pruss-cfg", "syscon";
1342			reg = <0x26000 0x200>;
1343			#address-cells = <1>;
1344			#size-cells = <1>;
1345			ranges = <0x0 0x26000 0x2000>;
1346
1347			clocks {
1348				#address-cells = <1>;
1349				#size-cells = <0>;
1350
1351				icssg1_coreclk_mux: coreclk-mux@3c {
1352					reg = <0x3c>;
1353					#clock-cells = <0>;
1354					clocks = <&k3_clks 82 0>,   /* icssg1_core_clk */
1355						 <&k3_clks 82 20>;  /* icssg1_iclk */
1356					assigned-clocks = <&icssg1_coreclk_mux>;
1357					assigned-clock-parents = <&k3_clks 82 20>;
1358				};
1359
1360				icssg1_iepclk_mux: iepclk-mux@30 {
1361					reg = <0x30>;
1362					#clock-cells = <0>;
1363					clocks = <&k3_clks 82 3>,	/* icssg1_iep_clk */
1364						 <&icssg1_coreclk_mux>;	/* icssg1_coreclk_mux */
1365					assigned-clocks = <&icssg1_iepclk_mux>;
1366					assigned-clock-parents = <&icssg1_coreclk_mux>;
1367				};
1368			};
1369		};
1370
1371		icssg1_mii_rt: mii-rt@32000 {
1372			compatible = "ti,pruss-mii", "syscon";
1373			reg = <0x32000 0x100>;
1374		};
1375
1376		icssg1_mii_g_rt: mii-g-rt@33000 {
1377			compatible = "ti,pruss-mii-g", "syscon";
1378			reg = <0x33000 0x1000>;
1379		};
1380
1381		icssg1_intc: interrupt-controller@20000 {
1382			compatible = "ti,icssg-intc";
1383			reg = <0x20000 0x2000>;
1384			interrupt-controller;
1385			#interrupt-cells = <3>;
1386			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1387				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1388				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1389				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1390				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1391				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
1392				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1393				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1394			interrupt-names = "host_intr0", "host_intr1",
1395					  "host_intr2", "host_intr3",
1396					  "host_intr4", "host_intr5",
1397					  "host_intr6", "host_intr7";
1398		};
1399
1400		pru1_0: pru@34000 {
1401			compatible = "ti,am642-pru";
1402			reg = <0x34000 0x4000>,
1403			      <0x22000 0x100>,
1404			      <0x22400 0x100>;
1405			reg-names = "iram", "control", "debug";
1406			firmware-name = "am64x-pru1_0-fw";
1407		};
1408
1409		rtu1_0: rtu@4000 {
1410			compatible = "ti,am642-rtu";
1411			reg = <0x4000 0x2000>,
1412			      <0x23000 0x100>,
1413			      <0x23400 0x100>;
1414			reg-names = "iram", "control", "debug";
1415			firmware-name = "am64x-rtu1_0-fw";
1416		};
1417
1418		tx_pru1_0: txpru@a000 {
1419			compatible = "ti,am642-tx-pru";
1420			reg = <0xa000 0x1800>,
1421			      <0x25000 0x100>,
1422			      <0x25400 0x100>;
1423			reg-names = "iram", "control", "debug";
1424			firmware-name = "am64x-txpru1_0-fw";
1425		};
1426
1427		pru1_1: pru@38000 {
1428			compatible = "ti,am642-pru";
1429			reg = <0x38000 0x4000>,
1430			      <0x24000 0x100>,
1431			      <0x24400 0x100>;
1432			reg-names = "iram", "control", "debug";
1433			firmware-name = "am64x-pru1_1-fw";
1434		};
1435
1436		rtu1_1: rtu@6000 {
1437			compatible = "ti,am642-rtu";
1438			reg = <0x6000 0x2000>,
1439			      <0x23800 0x100>,
1440			      <0x23c00 0x100>;
1441			reg-names = "iram", "control", "debug";
1442			firmware-name = "am64x-rtu1_1-fw";
1443		};
1444
1445		tx_pru1_1: txpru@c000 {
1446			compatible = "ti,am642-tx-pru";
1447			reg = <0xc000 0x1800>,
1448			      <0x25800 0x100>,
1449			      <0x25c00 0x100>;
1450			reg-names = "iram", "control", "debug";
1451			firmware-name = "am64x-txpru1_1-fw";
1452		};
1453
1454		icssg1_mdio: mdio@32400 {
1455			compatible = "ti,davinci_mdio";
1456			reg = <0x32400 0x100>;
1457			#address-cells = <1>;
1458			#size-cells = <0>;
1459			clocks = <&k3_clks 82 0>;
1460			clock-names = "fck";
1461			bus_freq = <1000000>;
1462			status = "disabled";
1463		};
1464	};
1465
1466	main_mcan0: can@20701000 {
1467		compatible = "bosch,m_can";
1468		reg = <0x00 0x20701000 0x00 0x200>,
1469		      <0x00 0x20708000 0x00 0x8000>;
1470		reg-names = "m_can", "message_ram";
1471		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
1472		clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1473		clock-names = "hclk", "cclk";
1474		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1475			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1476		interrupt-names = "int0", "int1";
1477		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1478		status = "disabled";
1479	};
1480
1481	main_mcan1: can@20711000 {
1482		compatible = "bosch,m_can";
1483		reg = <0x00 0x20711000 0x00 0x200>,
1484		      <0x00 0x20718000 0x00 0x8000>;
1485		reg-names = "m_can", "message_ram";
1486		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
1487		clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1488		clock-names = "hclk", "cclk";
1489		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1490			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1491		interrupt-names = "int0", "int1";
1492		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1493		status = "disabled";
1494	};
1495
1496	crypto: crypto@40900000 {
1497		compatible = "ti,am64-sa2ul";
1498		reg = <0x00 0x40900000 0x00 0x1200>;
1499		power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
1500		#address-cells = <2>;
1501		#size-cells = <2>;
1502		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
1503		dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
1504		       <&main_pktdma 0x4003 0>;
1505		dma-names = "tx", "rx1", "rx2";
1506
1507		rng: rng@40910000 {
1508			compatible = "inside-secure,safexcel-eip76";
1509			reg = <0x00 0x40910000 0x00 0x7d>;
1510			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1511			status = "disabled"; /* Used by OP-TEE */
1512		};
1513	};
1514
1515	gpmc0: memory-controller@3b000000 {
1516		compatible = "ti,am64-gpmc";
1517		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
1518		clocks = <&k3_clks 80 0>;
1519		clock-names = "fck";
1520		reg = <0x00 0x3b000000 0x00 0x400>,
1521		      <0x00 0x50000000 0x00 0x8000000>;
1522		reg-names = "cfg", "data";
1523		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1524		gpmc,num-cs = <3>;
1525		gpmc,num-waitpins = <2>;
1526		#address-cells = <2>;
1527		#size-cells = <1>;
1528		interrupt-controller;
1529		#interrupt-cells = <2>;
1530		gpio-controller;
1531		#gpio-cells = <2>;
1532		status = "disabled";
1533	};
1534
1535	elm0: ecc@25010000 {
1536		compatible = "ti,am64-elm";
1537		reg = <0x00 0x25010000 0x00 0x2000>;
1538		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1539		power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1540		clocks = <&k3_clks 54 0>;
1541		clock-names = "fck";
1542		status = "disabled";
1543	};
1544
1545	main_vtm0: temperature-sensor@b00000 {
1546		compatible = "ti,j7200-vtm";
1547		reg = <0x00 0xb00000 0x00 0x400>,
1548		      <0x00 0xb01000 0x00 0x400>;
1549		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
1550		#thermal-sensor-cells = <1>;
1551	};
1552};
1553