1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM62A SoC Family 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/k3.h> 12#include <dt-bindings/soc/ti,sci_pm_domain.h> 13 14/ { 15 model = "Texas Instruments K3 AM62A SoC"; 16 compatible = "ti,am62a7"; 17 interrupt-parent = <&gic500>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 firmware { 24 optee { 25 compatible = "linaro,optee-tz"; 26 method = "smc"; 27 }; 28 29 psci: psci { 30 compatible = "arm,psci-1.0"; 31 method = "smc"; 32 }; 33 }; 34 35 a53_timer0: timer-cl0-cpu0 { 36 compatible = "arm,armv8-timer"; 37 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 38 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 39 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 40 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 41 }; 42 43 pmu: pmu { 44 compatible = "arm,cortex-a53-pmu"; 45 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 46 }; 47 48 cbass_main: bus@f0000 { 49 compatible = "simple-bus"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ 63 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 64 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 65 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ 66 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 67 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ 68 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 69 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ 70 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 71 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 72 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 73 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 74 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ 75 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 76 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ 77 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */ 78 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 79 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 80 81 /* MCU Domain Range */ 82 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 83 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ 84 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ 85 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */ 86 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */ 87 88 /* Wakeup Domain Range */ 89 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, 90 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 91 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, 92 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */ 93 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */ 94 95 cbass_mcu: bus@4000000 { 96 compatible = "simple-bus"; 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ 100 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ 101 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ 102 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ 103 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ 104 }; 105 106 cbass_wakeup: bus@b00000 { 107 compatible = "simple-bus"; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 111 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 112 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ 113 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ 114 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ 115 }; 116 }; 117}; 118 119/* Now include the peripherals for each bus segments */ 120#include "k3-am62a-main.dtsi" 121#include "k3-am62a-mcu.dtsi" 122#include "k3-am62a-wakeup.dtsi" 123