1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM625 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_main {
9	oc_sram: sram@70000000 {
10		compatible = "mmio-sram";
11		reg = <0x00 0x70000000 0x00 0x10000>;
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges = <0x0 0x00 0x70000000 0x10000>;
15	};
16
17	gic500: interrupt-controller@1800000 {
18		compatible = "arm,gic-v3";
19		#address-cells = <2>;
20		#size-cells = <2>;
21		ranges;
22		#interrupt-cells = <3>;
23		interrupt-controller;
24		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
25		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
26		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
27		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
28		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
29		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
30		/*
31		 * vcpumntirq:
32		 * virtual CPU interface maintenance interrupt
33		 */
34		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
35
36		gic_its: msi-controller@1820000 {
37			compatible = "arm,gic-v3-its";
38			reg = <0x00 0x01820000 0x00 0x10000>;
39			socionext,synquacer-pre-its = <0x1000000 0x400000>;
40			msi-controller;
41			#msi-cells = <1>;
42		};
43	};
44
45	main_conf: syscon@100000 {
46		compatible = "syscon", "simple-mfd";
47		reg = <0x00 0x00100000 0x00 0x20000>;
48		#address-cells = <1>;
49		#size-cells = <1>;
50		ranges = <0x0 0x00 0x00100000 0x20000>;
51
52		phy_gmii_sel: phy@4044 {
53			compatible = "ti,am654-phy-gmii-sel";
54			reg = <0x4044 0x8>;
55			#phy-cells = <1>;
56		};
57
58		epwm_tbclk: clock@4130 {
59			compatible = "ti,am62-epwm-tbclk", "syscon";
60			reg = <0x4130 0x4>;
61			#clock-cells = <1>;
62		};
63	};
64
65	dmss: bus@48000000 {
66		compatible = "simple-mfd";
67		#address-cells = <2>;
68		#size-cells = <2>;
69		dma-ranges;
70		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
71
72		ti,sci-dev-id = <25>;
73
74		secure_proxy_main: mailbox@4d000000 {
75			compatible = "ti,am654-secure-proxy";
76			#mbox-cells = <1>;
77			reg-names = "target_data", "rt", "scfg";
78			reg = <0x00 0x4d000000 0x00 0x80000>,
79			      <0x00 0x4a600000 0x00 0x80000>,
80			      <0x00 0x4a400000 0x00 0x80000>;
81			interrupt-names = "rx_012";
82			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
83		};
84
85		inta_main_dmss: interrupt-controller@48000000 {
86			compatible = "ti,sci-inta";
87			reg = <0x00 0x48000000 0x00 0x100000>;
88			#interrupt-cells = <0>;
89			interrupt-controller;
90			interrupt-parent = <&gic500>;
91			msi-controller;
92			ti,sci = <&dmsc>;
93			ti,sci-dev-id = <28>;
94			ti,interrupt-ranges = <4 68 36>;
95			ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
96		};
97
98		main_bcdma: dma-controller@485c0100 {
99			compatible = "ti,am64-dmss-bcdma";
100			reg = <0x00 0x485c0100 0x00 0x100>,
101			      <0x00 0x4c000000 0x00 0x20000>,
102			      <0x00 0x4a820000 0x00 0x20000>,
103			      <0x00 0x4aa40000 0x00 0x20000>,
104			      <0x00 0x4bc00000 0x00 0x100000>;
105			reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
106			msi-parent = <&inta_main_dmss>;
107			#dma-cells = <3>;
108
109			ti,sci = <&dmsc>;
110			ti,sci-dev-id = <26>;
111			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
112			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
113			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
114		};
115
116		main_pktdma: dma-controller@485c0000 {
117			compatible = "ti,am64-dmss-pktdma";
118			reg = <0x00 0x485c0000 0x00 0x100>,
119			      <0x00 0x4a800000 0x00 0x20000>,
120			      <0x00 0x4aa00000 0x00 0x40000>,
121			      <0x00 0x4b800000 0x00 0x400000>;
122			reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
123			msi-parent = <&inta_main_dmss>;
124			#dma-cells = <2>;
125
126			ti,sci = <&dmsc>;
127			ti,sci-dev-id = <30>;
128			ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
129						<0x24>, /* CPSW_TX_CHAN */
130						<0x25>, /* SAUL_TX_0_CHAN */
131						<0x26>; /* SAUL_TX_1_CHAN */
132			ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
133						<0x11>, /* RING_CPSW_TX_CHAN */
134						<0x12>, /* RING_SAUL_TX_0_CHAN */
135						<0x13>; /* RING_SAUL_TX_1_CHAN */
136			ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
137						<0x2b>, /* CPSW_RX_CHAN */
138						<0x2d>, /* SAUL_RX_0_CHAN */
139						<0x2f>, /* SAUL_RX_1_CHAN */
140						<0x31>, /* SAUL_RX_2_CHAN */
141						<0x33>; /* SAUL_RX_3_CHAN */
142			ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
143						<0x2c>, /* FLOW_CPSW_RX_CHAN */
144						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
145						<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
146		};
147	};
148
149	dmsc: system-controller@44043000 {
150		compatible = "ti,k2g-sci";
151		ti,host-id = <12>;
152		mbox-names = "rx", "tx";
153		mboxes = <&secure_proxy_main 12>,
154			 <&secure_proxy_main 13>;
155		reg-names = "debug_messages";
156		reg = <0x00 0x44043000 0x00 0xfe0>;
157
158		k3_pds: power-controller {
159			compatible = "ti,sci-pm-domain";
160			#power-domain-cells = <2>;
161		};
162
163		k3_clks: clock-controller {
164			compatible = "ti,k2g-sci-clk";
165			#clock-cells = <2>;
166		};
167
168		k3_reset: reset-controller {
169			compatible = "ti,sci-reset";
170			#reset-cells = <2>;
171		};
172	};
173
174	crypto: crypto@40900000 {
175		compatible = "ti,am62-sa3ul";
176		reg = <0x00 0x40900000 0x00 0x1200>;
177		power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
178		#address-cells = <2>;
179		#size-cells = <2>;
180		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
181
182		dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
183		       <&main_pktdma 0x7507 0>;
184		dma-names = "tx", "rx1", "rx2";
185	};
186
187	secure_proxy_sa3: mailbox@43600000 {
188		compatible = "ti,am654-secure-proxy";
189		#mbox-cells = <1>;
190		reg-names = "target_data", "rt", "scfg";
191		reg = <0x00 0x43600000 0x00 0x10000>,
192		      <0x00 0x44880000 0x00 0x20000>,
193		      <0x00 0x44860000 0x00 0x20000>;
194		/*
195		 * Marked Disabled:
196		 * Node is incomplete as it is meant for bootloaders and
197		 * firmware on non-MPU processors
198		 */
199		status = "disabled";
200	};
201
202	main_pmx0: pinctrl@f4000 {
203		compatible = "pinctrl-single";
204		reg = <0x00 0xf4000 0x00 0x2ac>;
205		#pinctrl-cells = <1>;
206		pinctrl-single,register-width = <32>;
207		pinctrl-single,function-mask = <0xffffffff>;
208	};
209
210	main_esm: esm@420000 {
211		compatible = "ti,j721e-esm";
212		reg = <0x00 0x420000 0x00 0x1000>;
213		ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
214	};
215
216	main_timer0: timer@2400000 {
217		compatible = "ti,am654-timer";
218		reg = <0x00 0x2400000 0x00 0x400>;
219		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
220		clocks = <&k3_clks 36 2>;
221		clock-names = "fck";
222		assigned-clocks = <&k3_clks 36 2>;
223		assigned-clock-parents = <&k3_clks 36 3>;
224		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
225		ti,timer-pwm;
226	};
227
228	main_timer1: timer@2410000 {
229		compatible = "ti,am654-timer";
230		reg = <0x00 0x2410000 0x00 0x400>;
231		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
232		clocks = <&k3_clks 37 2>;
233		clock-names = "fck";
234		assigned-clocks = <&k3_clks 37 2>;
235		assigned-clock-parents = <&k3_clks 37 3>;
236		power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
237		ti,timer-pwm;
238	};
239
240	main_timer2: timer@2420000 {
241		compatible = "ti,am654-timer";
242		reg = <0x00 0x2420000 0x00 0x400>;
243		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
244		clocks = <&k3_clks 38 2>;
245		clock-names = "fck";
246		assigned-clocks = <&k3_clks 38 2>;
247		assigned-clock-parents = <&k3_clks 38 3>;
248		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
249		ti,timer-pwm;
250	};
251
252	main_timer3: timer@2430000 {
253		compatible = "ti,am654-timer";
254		reg = <0x00 0x2430000 0x00 0x400>;
255		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
256		clocks = <&k3_clks 39 2>;
257		clock-names = "fck";
258		assigned-clocks = <&k3_clks 39 2>;
259		assigned-clock-parents = <&k3_clks 39 3>;
260		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
261		ti,timer-pwm;
262	};
263
264	main_timer4: timer@2440000 {
265		compatible = "ti,am654-timer";
266		reg = <0x00 0x2440000 0x00 0x400>;
267		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
268		clocks = <&k3_clks 40 2>;
269		clock-names = "fck";
270		assigned-clocks = <&k3_clks 40 2>;
271		assigned-clock-parents = <&k3_clks 40 3>;
272		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
273		ti,timer-pwm;
274	};
275
276	main_timer5: timer@2450000 {
277		compatible = "ti,am654-timer";
278		reg = <0x00 0x2450000 0x00 0x400>;
279		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
280		clocks = <&k3_clks 41 2>;
281		clock-names = "fck";
282		assigned-clocks = <&k3_clks 41 2>;
283		assigned-clock-parents = <&k3_clks 41 3>;
284		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
285		ti,timer-pwm;
286	};
287
288	main_timer6: timer@2460000 {
289		compatible = "ti,am654-timer";
290		reg = <0x00 0x2460000 0x00 0x400>;
291		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
292		clocks = <&k3_clks 42 2>;
293		clock-names = "fck";
294		assigned-clocks = <&k3_clks 42 2>;
295		assigned-clock-parents = <&k3_clks 42 3>;
296		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
297		ti,timer-pwm;
298	};
299
300	main_timer7: timer@2470000 {
301		compatible = "ti,am654-timer";
302		reg = <0x00 0x2470000 0x00 0x400>;
303		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
304		clocks = <&k3_clks 43 2>;
305		clock-names = "fck";
306		assigned-clocks = <&k3_clks 43 2>;
307		assigned-clock-parents = <&k3_clks 43 3>;
308		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
309		ti,timer-pwm;
310	};
311
312	main_uart0: serial@2800000 {
313		compatible = "ti,am64-uart", "ti,am654-uart";
314		reg = <0x00 0x02800000 0x00 0x100>;
315		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
316		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
317		clocks = <&k3_clks 146 0>;
318		clock-names = "fclk";
319		status = "disabled";
320	};
321
322	main_uart1: serial@2810000 {
323		compatible = "ti,am64-uart", "ti,am654-uart";
324		reg = <0x00 0x02810000 0x00 0x100>;
325		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
326		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
327		clocks = <&k3_clks 152 0>;
328		clock-names = "fclk";
329		status = "disabled";
330	};
331
332	main_uart2: serial@2820000 {
333		compatible = "ti,am64-uart", "ti,am654-uart";
334		reg = <0x00 0x02820000 0x00 0x100>;
335		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
336		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
337		clocks = <&k3_clks 153 0>;
338		clock-names = "fclk";
339		status = "disabled";
340	};
341
342	main_uart3: serial@2830000 {
343		compatible = "ti,am64-uart", "ti,am654-uart";
344		reg = <0x00 0x02830000 0x00 0x100>;
345		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
346		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
347		clocks = <&k3_clks 154 0>;
348		clock-names = "fclk";
349		status = "disabled";
350	};
351
352	main_uart4: serial@2840000 {
353		compatible = "ti,am64-uart", "ti,am654-uart";
354		reg = <0x00 0x02840000 0x00 0x100>;
355		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
356		power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
357		clocks = <&k3_clks 155 0>;
358		clock-names = "fclk";
359		status = "disabled";
360	};
361
362	main_uart5: serial@2850000 {
363		compatible = "ti,am64-uart", "ti,am654-uart";
364		reg = <0x00 0x02850000 0x00 0x100>;
365		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
366		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
367		clocks = <&k3_clks 156 0>;
368		clock-names = "fclk";
369		status = "disabled";
370	};
371
372	main_uart6: serial@2860000 {
373		compatible = "ti,am64-uart", "ti,am654-uart";
374		reg = <0x00 0x02860000 0x00 0x100>;
375		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
376		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
377		clocks = <&k3_clks 158 0>;
378		clock-names = "fclk";
379		status = "disabled";
380	};
381
382	main_i2c0: i2c@20000000 {
383		compatible = "ti,am64-i2c", "ti,omap4-i2c";
384		reg = <0x00 0x20000000 0x00 0x100>;
385		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
386		#address-cells = <1>;
387		#size-cells = <0>;
388		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
389		clocks = <&k3_clks 102 2>;
390		clock-names = "fck";
391		status = "disabled";
392	};
393
394	main_i2c1: i2c@20010000 {
395		compatible = "ti,am64-i2c", "ti,omap4-i2c";
396		reg = <0x00 0x20010000 0x00 0x100>;
397		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
398		#address-cells = <1>;
399		#size-cells = <0>;
400		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
401		clocks = <&k3_clks 103 2>;
402		clock-names = "fck";
403		status = "disabled";
404	};
405
406	main_i2c2: i2c@20020000 {
407		compatible = "ti,am64-i2c", "ti,omap4-i2c";
408		reg = <0x00 0x20020000 0x00 0x100>;
409		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
410		#address-cells = <1>;
411		#size-cells = <0>;
412		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
413		clocks = <&k3_clks 104 2>;
414		clock-names = "fck";
415		status = "disabled";
416	};
417
418	main_i2c3: i2c@20030000 {
419		compatible = "ti,am64-i2c", "ti,omap4-i2c";
420		reg = <0x00 0x20030000 0x00 0x100>;
421		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
422		#address-cells = <1>;
423		#size-cells = <0>;
424		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
425		clocks = <&k3_clks 105 2>;
426		clock-names = "fck";
427		status = "disabled";
428	};
429
430	main_spi0: spi@20100000 {
431		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
432		reg = <0x00 0x20100000 0x00 0x400>;
433		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
434		#address-cells = <1>;
435		#size-cells = <0>;
436		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
437		clocks = <&k3_clks 141 0>;
438		status = "disabled";
439	};
440
441	main_spi1: spi@20110000 {
442		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
443		reg = <0x00 0x20110000 0x00 0x400>;
444		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
445		#address-cells = <1>;
446		#size-cells = <0>;
447		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
448		clocks = <&k3_clks 142 0>;
449		status = "disabled";
450	};
451
452	main_spi2: spi@20120000 {
453		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
454		reg = <0x00 0x20120000 0x00 0x400>;
455		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
456		#address-cells = <1>;
457		#size-cells = <0>;
458		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
459		clocks = <&k3_clks 143 0>;
460		status = "disabled";
461	};
462
463	main_gpio_intr: interrupt-controller@a00000 {
464		compatible = "ti,sci-intr";
465		reg = <0x00 0x00a00000 0x00 0x800>;
466		ti,intr-trigger-type = <1>;
467		interrupt-controller;
468		interrupt-parent = <&gic500>;
469		#interrupt-cells = <1>;
470		ti,sci = <&dmsc>;
471		ti,sci-dev-id = <3>;
472		ti,interrupt-ranges = <0 32 16>;
473	};
474
475	main_gpio0: gpio@600000 {
476		compatible = "ti,am64-gpio", "ti,keystone-gpio";
477		reg = <0x0 0x00600000 0x0 0x100>;
478		gpio-controller;
479		#gpio-cells = <2>;
480		interrupt-parent = <&main_gpio_intr>;
481		interrupts = <190>, <191>, <192>,
482			     <193>, <194>, <195>;
483		interrupt-controller;
484		#interrupt-cells = <2>;
485		ti,ngpio = <92>;
486		ti,davinci-gpio-unbanked = <0>;
487		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
488		clocks = <&k3_clks 77 0>;
489		clock-names = "gpio";
490	};
491
492	main_gpio1: gpio@601000 {
493		compatible = "ti,am64-gpio", "ti,keystone-gpio";
494		reg = <0x0 0x00601000 0x0 0x100>;
495		gpio-controller;
496		#gpio-cells = <2>;
497		interrupt-parent = <&main_gpio_intr>;
498		interrupts = <180>, <181>, <182>,
499			     <183>, <184>, <185>;
500		interrupt-controller;
501		#interrupt-cells = <2>;
502		ti,ngpio = <52>;
503		ti,davinci-gpio-unbanked = <0>;
504		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
505		clocks = <&k3_clks 78 0>;
506		clock-names = "gpio";
507	};
508
509	sdhci0: mmc@fa10000 {
510		compatible = "ti,am62-sdhci";
511		reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
512		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
513		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
514		clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
515		clock-names = "clk_ahb", "clk_xin";
516		assigned-clocks = <&k3_clks 57 6>;
517		assigned-clock-parents = <&k3_clks 57 8>;
518		mmc-ddr-1_8v;
519		mmc-hs200-1_8v;
520		ti,trm-icp = <0x2>;
521		bus-width = <8>;
522		ti,clkbuf-sel = <0x7>;
523		ti,otap-del-sel-legacy = <0x0>;
524		ti,otap-del-sel-mmc-hs = <0x0>;
525		ti,otap-del-sel-ddr52 = <0x5>;
526		ti,otap-del-sel-hs200 = <0x5>;
527		ti,itap-del-sel-legacy = <0xa>;
528		ti,itap-del-sel-mmc-hs = <0x1>;
529		status = "disabled";
530	};
531
532	sdhci1: mmc@fa00000 {
533		compatible = "ti,am62-sdhci";
534		reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
535		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
536		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
537		clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
538		clock-names = "clk_ahb", "clk_xin";
539		ti,trm-icp = <0x2>;
540		ti,otap-del-sel-legacy = <0x8>;
541		ti,otap-del-sel-sd-hs = <0x0>;
542		ti,otap-del-sel-sdr12 = <0x0>;
543		ti,otap-del-sel-sdr25 = <0x0>;
544		ti,otap-del-sel-sdr50 = <0x8>;
545		ti,otap-del-sel-sdr104 = <0x7>;
546		ti,otap-del-sel-ddr50 = <0x4>;
547		ti,itap-del-sel-legacy = <0xa>;
548		ti,itap-del-sel-sd-hs = <0x1>;
549		ti,itap-del-sel-sdr12 = <0xa>;
550		ti,itap-del-sel-sdr25 = <0x1>;
551		ti,clkbuf-sel = <0x7>;
552		bus-width = <4>;
553		status = "disabled";
554	};
555
556	sdhci2: mmc@fa20000 {
557		compatible = "ti,am62-sdhci";
558		reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
559		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
560		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
561		clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
562		clock-names = "clk_ahb", "clk_xin";
563		ti,trm-icp = <0x2>;
564		ti,otap-del-sel-legacy = <0x8>;
565		ti,otap-del-sel-sd-hs = <0x0>;
566		ti,otap-del-sel-sdr12 = <0x0>;
567		ti,otap-del-sel-sdr25 = <0x0>;
568		ti,otap-del-sel-sdr50 = <0x8>;
569		ti,otap-del-sel-sdr104 = <0x7>;
570		ti,otap-del-sel-ddr50 = <0x8>;
571		ti,itap-del-sel-legacy = <0xa>;
572		ti,itap-del-sel-sd-hs = <0xa>;
573		ti,itap-del-sel-sdr12 = <0xa>;
574		ti,itap-del-sel-sdr25 = <0x1>;
575		ti,clkbuf-sel = <0x7>;
576		status = "disabled";
577	};
578
579	usbss0: dwc3-usb@f900000 {
580		compatible = "ti,am62-usb";
581		reg = <0x00 0x0f900000 0x00 0x800>;
582		clocks = <&k3_clks 161 3>;
583		clock-names = "ref";
584		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
585		#address-cells = <2>;
586		#size-cells = <2>;
587		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
588		ranges;
589		status = "disabled";
590
591		usb0: usb@31000000 {
592			compatible = "snps,dwc3";
593			reg =<0x00 0x31000000 0x00 0x50000>;
594			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
595				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
596			interrupt-names = "host", "peripheral";
597			maximum-speed = "high-speed";
598			dr_mode = "otg";
599		};
600	};
601
602	usbss1: dwc3-usb@f910000 {
603		compatible = "ti,am62-usb";
604		reg = <0x00 0x0f910000 0x00 0x800>;
605		clocks = <&k3_clks 162 3>;
606		clock-names = "ref";
607		ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
608		#address-cells = <2>;
609		#size-cells = <2>;
610		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
611		ranges;
612		status = "disabled";
613
614		usb1: usb@31100000 {
615			compatible = "snps,dwc3";
616			reg =<0x00 0x31100000 0x00 0x50000>;
617			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
618				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
619			interrupt-names = "host", "peripheral";
620			maximum-speed = "high-speed";
621			dr_mode = "otg";
622		};
623	};
624
625	fss: bus@fc00000 {
626		compatible = "simple-bus";
627		reg = <0x00 0x0fc00000 0x00 0x70000>;
628		#address-cells = <2>;
629		#size-cells = <2>;
630		ranges;
631
632		ospi0: spi@fc40000 {
633			compatible = "ti,am654-ospi", "cdns,qspi-nor";
634			reg = <0x00 0x0fc40000 0x00 0x100>,
635			      <0x05 0x00000000 0x01 0x00000000>;
636			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
637			cdns,fifo-depth = <256>;
638			cdns,fifo-width = <4>;
639			cdns,trigger-address = <0x0>;
640			clocks = <&k3_clks 75 7>;
641			assigned-clocks = <&k3_clks 75 7>;
642			assigned-clock-parents = <&k3_clks 75 8>;
643			assigned-clock-rates = <166666666>;
644			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
645			#address-cells = <1>;
646			#size-cells = <0>;
647			status = "disabled";
648		};
649	};
650
651	cpsw3g: ethernet@8000000 {
652		compatible = "ti,am642-cpsw-nuss";
653		#address-cells = <2>;
654		#size-cells = <2>;
655		reg = <0x00 0x08000000 0x00 0x200000>;
656		reg-names = "cpsw_nuss";
657		ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
658		clocks = <&k3_clks 13 0>;
659		assigned-clocks = <&k3_clks 13 3>;
660		assigned-clock-parents = <&k3_clks 13 11>;
661		clock-names = "fck";
662		power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
663
664		dmas = <&main_pktdma 0xc600 15>,
665		       <&main_pktdma 0xc601 15>,
666		       <&main_pktdma 0xc602 15>,
667		       <&main_pktdma 0xc603 15>,
668		       <&main_pktdma 0xc604 15>,
669		       <&main_pktdma 0xc605 15>,
670		       <&main_pktdma 0xc606 15>,
671		       <&main_pktdma 0xc607 15>,
672		       <&main_pktdma 0x4600 15>;
673		dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
674			    "tx7", "rx";
675
676		ethernet-ports {
677			#address-cells = <1>;
678			#size-cells = <0>;
679
680			cpsw_port1: port@1 {
681				reg = <1>;
682				ti,mac-only;
683				label = "port1";
684				phys = <&phy_gmii_sel 1>;
685				mac-address = [00 00 00 00 00 00];
686				ti,syscon-efuse = <&wkup_conf 0x200>;
687			};
688
689			cpsw_port2: port@2 {
690				reg = <2>;
691				ti,mac-only;
692				label = "port2";
693				phys = <&phy_gmii_sel 2>;
694				mac-address = [00 00 00 00 00 00];
695			};
696		};
697
698		cpsw3g_mdio: mdio@f00 {
699			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
700			reg = <0x00 0xf00 0x00 0x100>;
701			#address-cells = <1>;
702			#size-cells = <0>;
703			clocks = <&k3_clks 13 0>;
704			clock-names = "fck";
705			bus_freq = <1000000>;
706			status = "disabled";
707		};
708
709		cpts@3d000 {
710			compatible = "ti,j721e-cpts";
711			reg = <0x00 0x3d000 0x00 0x400>;
712			clocks = <&k3_clks 13 3>;
713			clock-names = "cpts";
714			interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
715			interrupt-names = "cpts";
716			ti,cpts-ext-ts-inputs = <4>;
717			ti,cpts-periodic-outputs = <2>;
718		};
719	};
720
721	hwspinlock: spinlock@2a000000 {
722		compatible = "ti,am64-hwspinlock";
723		reg = <0x00 0x2a000000 0x00 0x1000>;
724		#hwlock-cells = <1>;
725	};
726
727	mailbox0_cluster0: mailbox@29000000 {
728		compatible = "ti,am64-mailbox";
729		reg = <0x00 0x29000000 0x00 0x200>;
730		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
731			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
732		#mbox-cells = <1>;
733		ti,mbox-num-users = <4>;
734		ti,mbox-num-fifos = <16>;
735	};
736
737	ecap0: pwm@23100000 {
738		compatible = "ti,am3352-ecap";
739		#pwm-cells = <3>;
740		reg = <0x00 0x23100000 0x00 0x100>;
741		power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
742		clocks = <&k3_clks 51 0>;
743		clock-names = "fck";
744		status = "disabled";
745	};
746
747	ecap1: pwm@23110000 {
748		compatible = "ti,am3352-ecap";
749		#pwm-cells = <3>;
750		reg = <0x00 0x23110000 0x00 0x100>;
751		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
752		clocks = <&k3_clks 52 0>;
753		clock-names = "fck";
754		status = "disabled";
755	};
756
757	ecap2: pwm@23120000 {
758		compatible = "ti,am3352-ecap";
759		#pwm-cells = <3>;
760		reg = <0x00 0x23120000 0x00 0x100>;
761		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
762		clocks = <&k3_clks 53 0>;
763		clock-names = "fck";
764		status = "disabled";
765	};
766
767	main_mcan0: can@20701000 {
768		compatible = "bosch,m_can";
769		reg = <0x00 0x20701000 0x00 0x200>,
770		      <0x00 0x20708000 0x00 0x8000>;
771		reg-names = "m_can", "message_ram";
772		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
773		clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
774		clock-names = "hclk", "cclk";
775		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
776			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
777		interrupt-names = "int0", "int1";
778		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
779		status = "disabled";
780	};
781
782	main_rti0: watchdog@e000000 {
783		compatible = "ti,j7-rti-wdt";
784		reg = <0x00 0x0e000000 0x00 0x100>;
785		clocks = <&k3_clks 125 0>;
786		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
787		assigned-clocks = <&k3_clks 125 0>;
788		assigned-clock-parents = <&k3_clks 125 2>;
789	};
790
791	main_rti1: watchdog@e010000 {
792		compatible = "ti,j7-rti-wdt";
793		reg = <0x00 0x0e010000 0x00 0x100>;
794		clocks = <&k3_clks 126 0>;
795		power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
796		assigned-clocks = <&k3_clks 126 0>;
797		assigned-clock-parents = <&k3_clks 126 2>;
798	};
799
800	main_rti2: watchdog@e020000 {
801		compatible = "ti,j7-rti-wdt";
802		reg = <0x00 0x0e020000 0x00 0x100>;
803		clocks = <&k3_clks 127 0>;
804		power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
805		assigned-clocks = <&k3_clks 127 0>;
806		assigned-clock-parents = <&k3_clks 127 2>;
807	};
808
809	main_rti3: watchdog@e030000 {
810		compatible = "ti,j7-rti-wdt";
811		reg = <0x00 0x0e030000 0x00 0x100>;
812		clocks = <&k3_clks 128 0>;
813		power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
814		assigned-clocks = <&k3_clks 128 0>;
815		assigned-clock-parents = <&k3_clks 128 2>;
816	};
817
818	main_rti15: watchdog@e0f0000 {
819		compatible = "ti,j7-rti-wdt";
820		reg = <0x00 0x0e0f0000 0x00 0x100>;
821		clocks = <&k3_clks 130 0>;
822		power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
823		assigned-clocks = <&k3_clks 130 0>;
824		assigned-clock-parents = <&k3_clks 130 2>;
825	};
826
827	epwm0: pwm@23000000 {
828		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
829		#pwm-cells = <3>;
830		reg = <0x00 0x23000000 0x00 0x100>;
831		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
832		clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
833		clock-names = "tbclk", "fck";
834		status = "disabled";
835	};
836
837	epwm1: pwm@23010000 {
838		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
839		#pwm-cells = <3>;
840		reg = <0x00 0x23010000 0x00 0x100>;
841		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
842		clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
843		clock-names = "tbclk", "fck";
844		status = "disabled";
845	};
846
847	epwm2: pwm@23020000 {
848		compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
849		#pwm-cells = <3>;
850		reg = <0x00 0x23020000 0x00 0x100>;
851		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
852		clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
853		clock-names = "tbclk", "fck";
854		status = "disabled";
855	};
856
857	mcasp0: audio-controller@2b00000 {
858		compatible = "ti,am33xx-mcasp-audio";
859		reg = <0x00 0x02b00000 0x00 0x2000>,
860		      <0x00 0x02b08000 0x00 0x400>;
861		reg-names = "mpu", "dat";
862		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
863			     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
864		interrupt-names = "tx", "rx";
865
866		dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
867		dma-names = "tx", "rx";
868
869		clocks = <&k3_clks 190 0>;
870		clock-names = "fck";
871		assigned-clocks = <&k3_clks 190 0>;
872		assigned-clock-parents = <&k3_clks 190 2>;
873		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
874		status = "disabled";
875	};
876
877	mcasp1: audio-controller@2b10000 {
878		compatible = "ti,am33xx-mcasp-audio";
879		reg = <0x00 0x02b10000 0x00 0x2000>,
880		      <0x00 0x02b18000 0x00 0x400>;
881		reg-names = "mpu", "dat";
882		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
883			     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
884		interrupt-names = "tx", "rx";
885
886		dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
887		dma-names = "tx", "rx";
888
889		clocks = <&k3_clks 191 0>;
890		clock-names = "fck";
891		assigned-clocks = <&k3_clks 191 0>;
892		assigned-clock-parents = <&k3_clks 191 2>;
893		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
894		status = "disabled";
895	};
896
897	mcasp2: audio-controller@2b20000 {
898		compatible = "ti,am33xx-mcasp-audio";
899		reg = <0x00 0x02b20000 0x00 0x2000>,
900		      <0x00 0x02b28000 0x00 0x400>;
901		reg-names = "mpu", "dat";
902		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
903			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
904		interrupt-names = "tx", "rx";
905
906		dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
907		dma-names = "tx", "rx";
908
909		clocks = <&k3_clks 192 0>;
910		clock-names = "fck";
911		assigned-clocks = <&k3_clks 192 0>;
912		assigned-clock-parents = <&k3_clks 192 2>;
913		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
914		status = "disabled";
915	};
916};
917