1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 27 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 28 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 29 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x0 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock@4130 { 59 compatible = "ti,am62-epwm-tbclk", "syscon"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 }; 64 65 dmss: bus@48000000 { 66 compatible = "simple-mfd"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 dma-ranges; 70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 71 72 ti,sci-dev-id = <25>; 73 74 secure_proxy_main: mailbox@4d000000 { 75 compatible = "ti,am654-secure-proxy"; 76 #mbox-cells = <1>; 77 reg-names = "target_data", "rt", "scfg"; 78 reg = <0x00 0x4d000000 0x00 0x80000>, 79 <0x00 0x4a600000 0x00 0x80000>, 80 <0x00 0x4a400000 0x00 0x80000>; 81 interrupt-names = "rx_012"; 82 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <4 68 36>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>; 105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 106 msi-parent = <&inta_main_dmss>; 107 #dma-cells = <3>; 108 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <26>; 111 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 112 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 113 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 114 }; 115 116 main_pktdma: dma-controller@485c0000 { 117 compatible = "ti,am64-dmss-pktdma"; 118 reg = <0x00 0x485c0000 0x00 0x100>, 119 <0x00 0x4a800000 0x00 0x20000>, 120 <0x00 0x4aa00000 0x00 0x40000>, 121 <0x00 0x4b800000 0x00 0x400000>; 122 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 123 msi-parent = <&inta_main_dmss>; 124 #dma-cells = <2>; 125 126 ti,sci = <&dmsc>; 127 ti,sci-dev-id = <30>; 128 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 129 <0x24>, /* CPSW_TX_CHAN */ 130 <0x25>, /* SAUL_TX_0_CHAN */ 131 <0x26>; /* SAUL_TX_1_CHAN */ 132 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 133 <0x11>, /* RING_CPSW_TX_CHAN */ 134 <0x12>, /* RING_SAUL_TX_0_CHAN */ 135 <0x13>; /* RING_SAUL_TX_1_CHAN */ 136 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 137 <0x2b>, /* CPSW_RX_CHAN */ 138 <0x2d>, /* SAUL_RX_0_CHAN */ 139 <0x2f>, /* SAUL_RX_1_CHAN */ 140 <0x31>, /* SAUL_RX_2_CHAN */ 141 <0x33>; /* SAUL_RX_3_CHAN */ 142 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 143 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 144 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 145 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 146 }; 147 }; 148 149 dmsc: system-controller@44043000 { 150 compatible = "ti,k2g-sci"; 151 ti,host-id = <12>; 152 mbox-names = "rx", "tx"; 153 mboxes = <&secure_proxy_main 12>, 154 <&secure_proxy_main 13>; 155 reg-names = "debug_messages"; 156 reg = <0x00 0x44043000 0x00 0xfe0>; 157 158 k3_pds: power-controller { 159 compatible = "ti,sci-pm-domain"; 160 #power-domain-cells = <2>; 161 }; 162 163 k3_clks: clock-controller { 164 compatible = "ti,k2g-sci-clk"; 165 #clock-cells = <2>; 166 }; 167 168 k3_reset: reset-controller { 169 compatible = "ti,sci-reset"; 170 #reset-cells = <2>; 171 }; 172 }; 173 174 crypto: crypto@40900000 { 175 compatible = "ti,am62-sa3ul"; 176 reg = <0x00 0x40900000 0x00 0x1200>; 177 power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 181 182 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 183 <&main_pktdma 0x7507 0>; 184 dma-names = "tx", "rx1", "rx2"; 185 }; 186 187 main_pmx0: pinctrl@f4000 { 188 compatible = "pinctrl-single"; 189 reg = <0x00 0xf4000 0x00 0x2ac>; 190 #pinctrl-cells = <1>; 191 pinctrl-single,register-width = <32>; 192 pinctrl-single,function-mask = <0xffffffff>; 193 }; 194 195 main_uart0: serial@2800000 { 196 compatible = "ti,am64-uart", "ti,am654-uart"; 197 reg = <0x00 0x02800000 0x00 0x100>; 198 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 199 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 200 clocks = <&k3_clks 146 0>; 201 clock-names = "fclk"; 202 }; 203 204 main_uart1: serial@2810000 { 205 compatible = "ti,am64-uart", "ti,am654-uart"; 206 reg = <0x00 0x02810000 0x00 0x100>; 207 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 208 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 209 clocks = <&k3_clks 152 0>; 210 clock-names = "fclk"; 211 }; 212 213 main_uart2: serial@2820000 { 214 compatible = "ti,am64-uart", "ti,am654-uart"; 215 reg = <0x00 0x02820000 0x00 0x100>; 216 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 217 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 218 clocks = <&k3_clks 153 0>; 219 clock-names = "fclk"; 220 }; 221 222 main_uart3: serial@2830000 { 223 compatible = "ti,am64-uart", "ti,am654-uart"; 224 reg = <0x00 0x02830000 0x00 0x100>; 225 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 226 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 227 clocks = <&k3_clks 154 0>; 228 clock-names = "fclk"; 229 }; 230 231 main_uart4: serial@2840000 { 232 compatible = "ti,am64-uart", "ti,am654-uart"; 233 reg = <0x00 0x02840000 0x00 0x100>; 234 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 235 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 236 clocks = <&k3_clks 155 0>; 237 clock-names = "fclk"; 238 }; 239 240 main_uart5: serial@2850000 { 241 compatible = "ti,am64-uart", "ti,am654-uart"; 242 reg = <0x00 0x02850000 0x00 0x100>; 243 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 244 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 245 clocks = <&k3_clks 156 0>; 246 clock-names = "fclk"; 247 }; 248 249 main_uart6: serial@2860000 { 250 compatible = "ti,am64-uart", "ti,am654-uart"; 251 reg = <0x00 0x02860000 0x00 0x100>; 252 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 253 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 254 clocks = <&k3_clks 158 0>; 255 clock-names = "fclk"; 256 }; 257 258 main_i2c0: i2c@20000000 { 259 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 260 reg = <0x00 0x20000000 0x00 0x100>; 261 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 265 clocks = <&k3_clks 102 2>; 266 clock-names = "fck"; 267 }; 268 269 main_i2c1: i2c@20010000 { 270 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 271 reg = <0x00 0x20010000 0x00 0x100>; 272 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 276 clocks = <&k3_clks 103 2>; 277 clock-names = "fck"; 278 }; 279 280 main_i2c2: i2c@20020000 { 281 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 282 reg = <0x00 0x20020000 0x00 0x100>; 283 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 287 clocks = <&k3_clks 104 2>; 288 clock-names = "fck"; 289 }; 290 291 main_i2c3: i2c@20030000 { 292 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 293 reg = <0x00 0x20030000 0x00 0x100>; 294 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 298 clocks = <&k3_clks 105 2>; 299 clock-names = "fck"; 300 }; 301 302 main_spi0: spi@20100000 { 303 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 304 reg = <0x00 0x20100000 0x00 0x400>; 305 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 309 clocks = <&k3_clks 172 0>; 310 }; 311 312 main_spi1: spi@20110000 { 313 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 314 reg = <0x00 0x20110000 0x00 0x400>; 315 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 319 clocks = <&k3_clks 173 0>; 320 }; 321 322 main_spi2: spi@20120000 { 323 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 324 reg = <0x00 0x20120000 0x00 0x400>; 325 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 329 clocks = <&k3_clks 174 0>; 330 }; 331 332 main_gpio_intr: interrupt-controller@a00000 { 333 compatible = "ti,sci-intr"; 334 reg = <0x00 0x00a00000 0x00 0x800>; 335 ti,intr-trigger-type = <1>; 336 interrupt-controller; 337 interrupt-parent = <&gic500>; 338 #interrupt-cells = <1>; 339 ti,sci = <&dmsc>; 340 ti,sci-dev-id = <3>; 341 ti,interrupt-ranges = <0 32 16>; 342 }; 343 344 main_gpio0: gpio@600000 { 345 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 346 reg = <0x0 0x00600000 0x0 0x100>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-parent = <&main_gpio_intr>; 350 interrupts = <190>, <191>, <192>, 351 <193>, <194>, <195>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 ti,ngpio = <87>; 355 ti,davinci-gpio-unbanked = <0>; 356 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 357 clocks = <&k3_clks 77 0>; 358 clock-names = "gpio"; 359 }; 360 361 main_gpio1: gpio@601000 { 362 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 363 reg = <0x0 0x00601000 0x0 0x100>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-parent = <&main_gpio_intr>; 367 interrupts = <180>, <181>, <182>, 368 <183>, <184>, <185>; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 ti,ngpio = <88>; 372 ti,davinci-gpio-unbanked = <0>; 373 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 374 clocks = <&k3_clks 78 0>; 375 clock-names = "gpio"; 376 }; 377 378 sdhci0: mmc@fa10000 { 379 compatible = "ti,am62-sdhci"; 380 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 381 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 382 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 383 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 384 clock-names = "clk_ahb", "clk_xin"; 385 assigned-clocks = <&k3_clks 57 6>; 386 assigned-clock-parents = <&k3_clks 57 8>; 387 mmc-ddr-1_8v; 388 mmc-hs200-1_8v; 389 ti,trm-icp = <0x2>; 390 bus-width = <8>; 391 ti,clkbuf-sel = <0x7>; 392 ti,otap-del-sel-legacy = <0x0>; 393 ti,otap-del-sel-mmc-hs = <0x0>; 394 ti,otap-del-sel-ddr52 = <0x9>; 395 ti,otap-del-sel-hs200 = <0x6>; 396 }; 397 398 sdhci1: mmc@fa00000 { 399 compatible = "ti,am62-sdhci"; 400 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 401 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 402 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 404 clock-names = "clk_ahb", "clk_xin"; 405 ti,trm-icp = <0x2>; 406 ti,otap-del-sel-legacy = <0x0>; 407 ti,otap-del-sel-sd-hs = <0x0>; 408 ti,otap-del-sel-sdr12 = <0xf>; 409 ti,otap-del-sel-sdr25 = <0xf>; 410 ti,otap-del-sel-sdr50 = <0xc>; 411 ti,otap-del-sel-sdr104 = <0x6>; 412 ti,otap-del-sel-ddr50 = <0x9>; 413 ti,itap-del-sel-legacy = <0x0>; 414 ti,itap-del-sel-sd-hs = <0x0>; 415 ti,itap-del-sel-sdr12 = <0x0>; 416 ti,itap-del-sel-sdr25 = <0x0>; 417 ti,clkbuf-sel = <0x7>; 418 bus-width = <4>; 419 }; 420 421 sdhci2: mmc@fa20000 { 422 compatible = "ti,am62-sdhci"; 423 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 424 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 425 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 427 clock-names = "clk_ahb", "clk_xin"; 428 ti,trm-icp = <0x2>; 429 ti,otap-del-sel-legacy = <0x0>; 430 ti,otap-del-sel-sd-hs = <0x0>; 431 ti,otap-del-sel-sdr12 = <0xf>; 432 ti,otap-del-sel-sdr25 = <0xf>; 433 ti,otap-del-sel-sdr50 = <0xc>; 434 ti,otap-del-sel-sdr104 = <0x6>; 435 ti,otap-del-sel-ddr50 = <0x9>; 436 ti,itap-del-sel-legacy = <0x0>; 437 ti,itap-del-sel-sd-hs = <0x0>; 438 ti,itap-del-sel-sdr12 = <0x0>; 439 ti,itap-del-sel-sdr25 = <0x0>; 440 ti,clkbuf-sel = <0x7>; 441 }; 442 443 fss: bus@fc00000 { 444 compatible = "simple-bus"; 445 reg = <0x00 0x0fc00000 0x00 0x70000>; 446 #address-cells = <2>; 447 #size-cells = <2>; 448 ranges; 449 450 ospi0: spi@fc40000 { 451 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 452 reg = <0x00 0x0fc40000 0x00 0x100>, 453 <0x05 0x00000000 0x01 0x00000000>; 454 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 455 cdns,fifo-depth = <256>; 456 cdns,fifo-width = <4>; 457 cdns,trigger-address = <0x0>; 458 clocks = <&k3_clks 75 7>; 459 assigned-clocks = <&k3_clks 75 7>; 460 assigned-clock-parents = <&k3_clks 75 8>; 461 assigned-clock-rates = <166666666>; 462 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 }; 467 468 cpsw3g: ethernet@8000000 { 469 compatible = "ti,am642-cpsw-nuss"; 470 #address-cells = <2>; 471 #size-cells = <2>; 472 reg = <0x00 0x08000000 0x00 0x200000>; 473 reg-names = "cpsw_nuss"; 474 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 475 clocks = <&k3_clks 13 0>; 476 assigned-clocks = <&k3_clks 13 3>; 477 assigned-clock-parents = <&k3_clks 13 11>; 478 clock-names = "fck"; 479 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 480 481 dmas = <&main_pktdma 0xc600 15>, 482 <&main_pktdma 0xc601 15>, 483 <&main_pktdma 0xc602 15>, 484 <&main_pktdma 0xc603 15>, 485 <&main_pktdma 0xc604 15>, 486 <&main_pktdma 0xc605 15>, 487 <&main_pktdma 0xc606 15>, 488 <&main_pktdma 0xc607 15>, 489 <&main_pktdma 0x4600 15>; 490 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 491 "tx7", "rx"; 492 493 ethernet-ports { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 497 cpsw_port1: port@1 { 498 reg = <1>; 499 ti,mac-only; 500 label = "port1"; 501 phys = <&phy_gmii_sel 1>; 502 mac-address = [00 00 00 00 00 00]; 503 ti,syscon-efuse = <&wkup_conf 0x200>; 504 }; 505 506 cpsw_port2: port@2 { 507 reg = <2>; 508 ti,mac-only; 509 label = "port2"; 510 phys = <&phy_gmii_sel 2>; 511 mac-address = [00 00 00 00 00 00]; 512 }; 513 }; 514 515 cpsw3g_mdio: mdio@f00 { 516 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 517 reg = <0x00 0xf00 0x00 0x100>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&k3_clks 13 0>; 521 clock-names = "fck"; 522 bus_freq = <1000000>; 523 }; 524 525 cpts@3d000 { 526 compatible = "ti,j721e-cpts"; 527 reg = <0x00 0x3d000 0x00 0x400>; 528 clocks = <&k3_clks 13 3>; 529 clock-names = "cpts"; 530 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "cpts"; 532 ti,cpts-ext-ts-inputs = <4>; 533 ti,cpts-periodic-outputs = <2>; 534 }; 535 }; 536 537 hwspinlock: spinlock@2a000000 { 538 compatible = "ti,am64-hwspinlock"; 539 reg = <0x00 0x2a000000 0x00 0x1000>; 540 #hwlock-cells = <1>; 541 }; 542 543 mailbox0_cluster0: mailbox@29000000 { 544 compatible = "ti,am64-mailbox"; 545 reg = <0x00 0x29000000 0x00 0x200>; 546 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 548 #mbox-cells = <1>; 549 ti,mbox-num-users = <4>; 550 ti,mbox-num-fifos = <16>; 551 }; 552 553 ecap0: pwm@23100000 { 554 compatible = "ti,am3352-ecap"; 555 #pwm-cells = <3>; 556 reg = <0x00 0x23100000 0x00 0x100>; 557 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 558 clocks = <&k3_clks 51 0>; 559 clock-names = "fck"; 560 }; 561 562 ecap1: pwm@23110000 { 563 compatible = "ti,am3352-ecap"; 564 #pwm-cells = <3>; 565 reg = <0x00 0x23110000 0x00 0x100>; 566 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 567 clocks = <&k3_clks 52 0>; 568 clock-names = "fck"; 569 }; 570 571 ecap2: pwm@23120000 { 572 compatible = "ti,am3352-ecap"; 573 #pwm-cells = <3>; 574 reg = <0x00 0x23120000 0x00 0x100>; 575 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 53 0>; 577 clock-names = "fck"; 578 }; 579 580 main_mcan0: can@20701000 { 581 compatible = "bosch,m_can"; 582 reg = <0x00 0x20701000 0x00 0x200>, 583 <0x00 0x20708000 0x00 0x8000>; 584 reg-names = "m_can", "message_ram"; 585 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 586 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 587 clock-names = "hclk", "cclk"; 588 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "int0", "int1"; 591 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 592 }; 593 594 epwm0: pwm@23000000 { 595 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 596 #pwm-cells = <3>; 597 reg = <0x00 0x23000000 0x00 0x100>; 598 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 599 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 600 clock-names = "tbclk", "fck"; 601 }; 602 603 epwm1: pwm@23010000 { 604 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 605 #pwm-cells = <3>; 606 reg = <0x00 0x23010000 0x00 0x100>; 607 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 608 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 609 clock-names = "tbclk", "fck"; 610 }; 611 612 epwm2: pwm@23020000 { 613 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 614 #pwm-cells = <3>; 615 reg = <0x00 0x23020000 0x00 0x100>; 616 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 617 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 618 clock-names = "tbclk", "fck"; 619 }; 620}; 621